System Verilog Question & Answers

1 Difference between static function and function

static Static Function:
Static functions share the same storage space for all function calls.
Function static:
The variables used inside the methods are static in nature.
2 Difference between static and automatic
function/task Static Function:
Static functions share the same storage space for all function calls.
Automatic Function:
Automatic functions allocate unique, stacked storage for each function call.
Static tasks
Static tasks share the same storage space for all task calls.
Automatic tasks
Automatic tasks allocate unique, stacked storage for each task call.
3 Difference between unique if and priority if
Unique if: Evaluate conditions in any order and does following:
Report an error when none of the if conditions match unless there is an explicit
else.
Report an erorr when there is more than 1 match found in the if else
conditions priority if: Evaluate all conditions in sequential order and violation is
reported when: None of the conditions are true or if there's no else clause to the final
if construct
4 Difference between unique case and priority
case Unique case
unique case evaluates all the conditions parallel
simulator issue a run time error/warning in following condition
i)More than one alternative is true
ii)No alternatives is true and if doesn’t have default else statement
priority case
Priority case evaluates all the condition in sequential order
simulator issue a run time error/warning in following condition
i) No alternatives is match or doesn’t have corresponding default case.

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5 What is the use of rand case and rand sequence
Randcase is a case statement that randomly selects one of its branches just like a case
statement in Verilog but here as its randcase so it will pick statements randomly.
randcase can be used in class or modules.
The randcase item expressions are non-negative integral values that constitute the
branch weights.
An item weight divided by the sum of all weights gives the probability of taking that
branch.
Let’s understand through the example below:
randcase
9 : x = 10;
5 : x = 11;
7 : x = 12;
endcase
In the above-mentioned example, the sum of all weights is 21; therefore, the
probability of taking the first branch is (9/21) i.e. 0.428.
The probability of taking the second is (5/21) i.e. 0.238, and the probability of taking
the third is (7/21) i.e. 0.333.
If a branch specifies a zero weight, then that branch is not taken. If all randcase_items
specify zero weights, then no branch is taken and a warning can be issued.
Randsequence:
The random sequence generator is useful for randomly generating structured
sequences of stimulus such as instructions or network traffic patterns.
By randomizing a packet, it will generate the most unlikely scenarios which are not
interested. This type of sequence of scenarios can be generated using randsequence.
randsequence is composed of one or more productions.
Each production contains a name and one or more production_list.
Production_list contains one or more production_item.
Production_items of production_list are further classified into terminals and non-
terminals.
A terminal is an indivisible item that needs no further definition than its associated
code block.
Ultimately, every non-terminal is decomposed into its terminals.

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Ex:
program rand_sequence();
initial begin
repeat(5) begin
randsequence( main )
main : one two three ;
one : {$write("one");};
two : {$write(" two");};
three: {$display(" three");};
endsequence
end
end
endprogram : rand_sequence
o/p
one two three
one two three
one two three
one two three
one two three
6 Difference between fork, join , join_any and
join_none fork join:
Fork-Join will start all the processes inside it parallel and wait for the completion of
all the processes.
fork join_any:
Fork-Join_any will be unblocked after the completion of any of the Processes.
fork join_none:
As in the case of Fork-Join and Fork-Join_any fork block is blocking, but in case of
Fork-Join_none fork block will be non-blocking.
Processes inside the fork-join_none block will be started at the same time, fork block
will not wait for the completion of the Process inside the fork-join_none.
7 What is callback?
It is a mechanism to changing the behavior of a verification component such as driver,
generator or monitor without actually changing the code of that component.

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8 Explain the difference between data types logic and reg and wire (Data types)
Wire are Reg are present in the verilog and system verilog adds one more data type
called logic.
Wire : Wire data type is used in the continuous assignments or ports list. It is treated
as a wire So it can not hold a value. It can be driven and read. Wires are used for
connecting different modules.
Reg : Reg is a date storage element in system verilog. Its not a actual hardware
register but it can store values. Register retain there value until next assignment
statement.
Logic : System verilog added this additional datatype extends the rand eg type so it
can be driven by a single driver such as gate or module. The main difference between
logic dataype and reg/wire is that a logic can be driven by both continuous assignment
or blocking/non blocking assignment.

9 What is need of clocking block?

 It is used to specify synchronization characteristics of the design
 It Offers a clean way to drive and sample signals
 Provides race-free operation if input skew > 0
 Helps in testbench driving the signals at the right time
10 What are the ways to avoid race condition between testbench and RTL using
SystemVerilog?
here are mainly following ways to avoid the race condition between testbench and
RTL using system verilog
Program Block.
Clocking Block.
Using non blocking assignments.
11 What are the types of coverage available in SV ?
Functional coverage
Code coverage or Structural coverage
12 What is the need of virtual interfaces?
An interface encapsulate a group of inter-related wires, along with their directions (via
modports) and synchronization details (via clocking block). The major usage of
interface is to simplify the connection between modules.

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But Interface can't be instantiated inside program block, class (or similar non-module
entity in SystemVerilog). But they needed to be driven from verification environment
like class. To solve this issue virtual interface concept was introduced in SV.
Virtual interface is a data type (that implies it can be instantiated in a class) which
hold reference to an interface (that implies the class can drive the interface using the
virtual interface). It provides a mechanism for separating abstract models and test
programs from the actual signals that make up the design. Another big advantage of
virtual interface is that class can dynamically connect to different physical interfaces
in run time.
13 Explain Abstract classes and virtual methods.
Abstract classes:
SystemVerilog class declared with the keyword virtual is referred to as an abstract
class.
An abstract class sets out the prototype for the sub-classes.
An abstract class cannot be instantiated, it can only be derived.
An abstract class can contain methods for which there are only a prototype and no
implementation, just a method declaration.
virtual methods:
SystemVerilog Methods declared with the keyword virtual are referred to as virtual
methods.
Virtual Methods are
Virtual Functions
Virtual Tasks
Virtual Functions
A function declared with a virtual keyword before the function keyword is referred to
as virtual Function
Virtual Task
Task declared with a virtual keyword before the task keyword is referred to as virtual
task

14 What is the difference between mailbox and queue?

 A queue is a variable-size, ordered collection of homogeneous elements. A Queue
is analogous to one dimensional unpacked array that grows and shrinks

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automatically. Queues can be used to model a last in, first out buffer or first in,
first out buffer.
 A mailbox is a communication mechanism that allows messages to be exchanged
between processes. Data can be sent to a mailbox by one process and retrieved by
another.
 Mailbox is a build-in class around queue that uses semaphores to access control.
One to many component we can transfer through mail box but queue supports
only one to one transfer.
15 What is the use of pre and post randomizes method?
These are built-in callback functions supported in SystemVerilog language to perform
an action immediately either before every randomize call or immediately after
randomize call.
A pre_randomize() is useful for setting or overriding any constraints while a
post_randomize() is useful to override results of randomization.
16 What is the difference between always_comb and always@(*)
always_comb get executed once at time 0, always @* waits till a change
occurs on a signal in the inferred sensitivity list
Statement within always_comb can't have blocking timing, event control, or
fork-join statement. No such restriction of always @*
Optionally EDA tool might perform additional checks to warn if the behavior
within always_comb procedure doesn't represent combinatorial logic
Variables on the left-hand side of assignments within an always_comb
procedure, including variables from the contents of a called function, shall not
be written to by any other processes, whereas always @* permits multiple
processes to write to the same variable.
always_comb is sensitive to changes within content of a function, whereas
always @* is only sensitive to changes to the arguments to the function.
17 What is the use of packages? How will you access anything from package?
In Verilog declaration of data/task/function within modules are specific to the module
only. They can't be shared between two modules. Agreed, we can achieve the same
via cross module referencing or by including the files, both of which are known to be
not a great solution.

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The package construct of SystemVerilog aims in solving the above issue. It allows
having global data/task/function declaration which can be used across modules. It can
contain module/class/function/task/constraints/covergroup and many more
declarations .
The content inside the package can be accessed using either scope resolution operator
(::), or using import (with option of referencing particular or all content of the
package).
18 What is the use of $cast?
Type casting in SV can be done either via static casting (', ', ') or dynamic casting via
$cast task/function. $cast is very similar to dynamic_cast of C++. It checks whether
the casting is possible or not in run-time and errors-out if casting is not possible.
It is always legal to assign a child class variable to a variable of a class higher in the
inheritance tree (parent class).
parent_class = child_class; //allowed
It is never legal to directly assign a super-class (parent class) variable to a variable of
one of its sub classes (child class).
child_class = parent_class; //not-allowed
However, it is legal to assign a super-class (parent class) handle to a subclass (child
class) variable if the super-class (parent class) handle refers to an object of the given
subclass(child class).
parent_class = child_class ;
child_class = parent_class;
//allowed because parent_class is pointing to child_class.
Though parent_class is pointing to the child_class, we will get a compilation error
saying its not compatible type for the assignment.
This we can over come by make use of $cast method, i.e,

$cast(child_class,parent_class);

19 How to call the task which is defined in parent object into derived class ?

super.task_name();

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20 What is the difference between rand and randc?
rand - Random Variable, same value might come before all the the possible value
have been returned. Analogous to throwing a dice.
randc - Random Cyclic Variable, same value doesn't get returned until all possible
value have been returned. Analogous to picking of card from a deck of card without
replacing. Resource intensive, use sparingly/judiciously
21 What are bi-directional constraints?
Constraints by-default in SystemVerilog are bi-directional. That implies that the
constraint solver doesn't follow the sequence in which the constraints are specified.
All the variables are looked simultaneously. Even the procedural looking constrains
like if ... else ... and -> constrains, both if and else part are tried to solve concurrently.
For example (a==0) -> (b==1) shall be solved as all the possible solution of (!(a==0) ||
(b==1)).
22 What is solve...before constraint?
In the case where the user want to specify the order in which the constraints solver
shall solve the constraints, the user can specify the order via solve before construct. i.e.

constraint XYZ
{ a inside
{[0:100]|; b < 20;
a + b > 30; solve
a before b;
}

The solution of the constraint doesn't change with solve before construct. But the
probability of choosing a particular solution change by it.

23 Without using randomize method or rand, generate an array of unique values?

int UniqVal[10];
foreach(UniqVal[i]) UniqVal[i] = i;
UniqVal.shuffle();

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24 Explain about pass by ref and pass by value?
 Pass by value is the default method through which arguments are passed into
functions and tasks. Each subroutine retains a local copy of the argument. If the
arguments are changed within the subroutine declaration, the changes do not
affect the caller.
 In pass by reference functions and tasks directly access the specified variables
passed as arguments. Its like passing pointer of the variable. The changes
happening inside the function will reflect outside.
25 What is the difference between bit[7:0] sig_1; and byte sig_2;
byte is signed whereas bit [7:0] is unsigned.
byte is a signed variable which means it can only be used to count values till 127.

26 How will you declare parameterized class? How will you override class
parameter?
// Declare parameterzied class
Class <name_of_class> #(<parameters>);
Class Trans #(addr=32);
//Override class parameter
<name_of_class> #(<parameters>) <name_of_inst>;
Trans #(.addr(16)) obj;

27 Mention the Difference Between a Virtual and Pure Virtual Function in System
Verilog
A virtual function allows the overriding of implementation of a function in a given
derived class. Therefore, the base class doesn’t need to implement the virtual function.
On the other hand, a pure virtual function only has the declaration and lacks any
implementation. Therefore, any derivative class must implement the function.

28 What Is The Difference Between $random() And $urandom()?

$random system function returns a 32-bit signed random number each time it is
called
$urandom system function returns a 32-bit unsigned random number each time it is
called. (newly added in SV, not present in verilog)

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29 What Is $root?
$root is the root of the instantiation tree. SystemVerilog introduced the concept of
$root as a global scope that allowed any kind of declaration (data types, classes,
variables) along with module definitions nested in that global scope. Any un-
instantiated module is implicitly instantiated in $root.
$root refers to the top level instance in
SystemVerilog package ABC;
$root.A; // top level instance A
$root.A.B.C; // item C within instance B within top level instance A
30 What is the difference between program block and module?
Program block is newly added in SystemVerilog. It serves these
purposes It separates testbench from DUT
It helps in ensuring that testbench doesn't have any race condition with
DUT It provides an entry point for execution of testbench
It provides syntactic context (via program ... endprogram) that specifies
scheduling in the Reactive Region.
31 What is the use of modports?
Modports are part of Interface. Modports are used for specifying the direction of the
signals with respect to various modules the interface connects to.
interface my_intf;
wire x, y, z;
modport master (input x, y, output z);

modport slave (output x, y, input z);

32 What is forward referencing and how to avoid this problem?

Any datatype used inside the code without declaring it, compiler will not
recognizance it and it will through compilation error. To over come that need to
define that variable using ‘typedef’ key word before using that inside the code, so
compiler understand that the declaration of the datatype is implemented later portion
of the code.
33 What is cross coverage?

Cross allows keeping track of information which is received simultaneous on

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more than one cover point.
Cross coverage is specified using the cross construct.
34 How to kill a process in fork/join?

Processes can be terminated at any time using a keyword disable.

35 Difference between immediate and concurrent Assertions?
 Immediate assertions check for a condition at the current simulation time.
 It checks the sequence of events spread over multiple clock cycles.
36 How to randomize dynamic arrays of objects?
class packet;
rand byte data [];
constraint dvalues { foreach( data[j] ) data[j] > 10; }
constraint dsize { data.size == 5; }
endclass
37 Types of cover bins?
Automatic bins or implicit
bins Explicit bins
Transition bins
Ignore bins
Illegal bins
Wildcard bins
38 Functional coverage-50 and code-100 / code coverage-50 & functional-100, What
it is means?
FC->50% & CC->100%
Redundant bins are there. Lot of unnecessary coverage points are written or need to
implement more features in design.
FC->100% & CC->50%
Coverage point listed is less need to add more relevant points and need to write test
cases to cover the uncovered portion of the code

39 Why always block is not allowed in program block?

The program block came from the Vera verification language. In Vera, a program was
a single procedure that represented the "test". Your test was started at time 0 and when

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the test terminated, the program terminated the simulation. If you needed multiple test
threads, you either had to use the fork statement to start it, or use multiple programs.
When the last program terminated, the simulation terminated.
As part of the integration with SystemVerilog, the program was turned into a module-
like construct with ports and initial blocks are now used to start the test procedure.
Because an always block never terminates, it was kept out of the program block so
the concept of test termination would still be there.
40 Which is best to use to model transaction? Struct or class why?
Class. A class variable holds just a reference and a new call is required to create a
class object. But struct variables like array variables directly hold values.
41 Difference between assert and expect statements?
The expect directive is not counted by coverage metrics. That is to say that a failure
does not the test failed, just that you were testing something to occur and it didn't
happen. Think of expect as a temporal-if statement.
The expect directive is blocks the current thread until it either passes or fails. An
assert directive has no impact on the current thread.
42 What is shallow copy? What the limitation. What is deep copy?
shallow copy
An object will be created only after doing new to a class handle,
packet pkt_1;
pkt_1 = new();

packet pkt_2;
pkt_2 = new pkt_1
In the last statement, pkt_2 is created and class properties were copied from
pkt_1 to pkt_2, this is called as “shallow copy”.
Shallow copy allocates the memory, copies the variable values and returns the
memory handle.
In shallow copy, All of the variables are copied across: integers, strings,
instance handles, etc.
limitation
Objects will not be copied, only their handles will be copied.

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deep copy:
SystemVerilog deep copy copies all the class members and its nested class members.
unlike in shallow copy, only nested class handles will be copied. In shallow copy,
Objects will not be copied, only their handles will be copied. to perform a full or deep
copy, the custom method needs to be added.
In the custom method, a new object is created, all the class properties will be copied
to a new handle and the new handle will be returned.

43 What ‘this’ and ‘super’ keywords indicates?

 The “super” keyword is used from within a sub-class to refer to properties and
methods of the base class. It is mandatory to use the super keyword to access
properties and methods if they have been overridden by the sub-class.
 “this” pointer refers to current instance
44 What is "scope resolution operator"?
extern keyword allows out-of-body method declaration in classes. Scope resolution
operator ( :: ) links method declaration to class declaration.
class XYZ;
// SayHello() will be declared outside the body of the
class extern void task SayHello();
endclass : XYZ
void task XYZ :: SayHello();

$Message("Hello !!!n");

endtask : SayHello
45 What is the use of extern keyword?

Class definitions can become very long with a lot of lines between class and
end class.This makes difficult to understand what all function and variables
exist within the class because each of function and task occupy quite a lot of
lines
Using extern qualifier in method declaration indicates that the implementation
is done outside the body of this class.

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46 What is the difference between bits and logic?
bits is 2-(state) valued (1/0) and logic is 4-(state) valued (0/1/x/z)
47 What is the difference between $rose and posedge?
posedge return an event, whereas $rose returns a Boolean value. Therefore they are
not interchangeable.
48 What is coverage driven verification?
Coverage Driven Verification is a result-oriented approach to functional verification.
In a nut shell, you define your functional coverage points, and then in an iterative
process you run tests, analyze the functional coverage and close in on the remaining
functional coverage.
49 What data structure is used to store data in your environment and why?
Class data structure is used to create testbench environment because it is dynamic in
nature.
50 What is streaming operator and what is its use?
Streaming operator ‘<<‘ & ‘>>’ are used to pack or unpack the data in specified order.
The packing or unpacking can be done on a matching data-type or by type-casting to a
particular data-type that match the Widths. If the packed data consists of 4-State type
of variable & 2-State type of variable, the result is inferred as 4-state type.
logic a, b, c, d;

logic [3:0] e;

assign e = (>>{a,b,c,d}); // packs a stream of a,b,c,d

{{>>e}}; // unpacks/generates stream of a,b,c,d

{{<<e}}; // unpacks/generates stream of d,c,b,a

(>>{a,b,c,d}) = e; // unpack d=e[0], c=e[1], b=e[2], a=e[3];

The streaming operator uses the terminology pack when you take multiple variables
and stream them into a single variable. And conversely, unpack is when you stream a
single variable into multiple variables.
51 What is a void function?
Void functions are simply functions that have no return value. The can be used
wherever a statement is allowed. They cannot be used as part of an expression. There
are typically used to set up or initialize a group of variables. A function must not

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block and executes in 0 time.
52 What is the difference between initial block and final block?
There are many difference between initial and final block. I am listing the few
differences that is coming to mind now.
 The most obvious one : Initial blocks get executed at the beginning of the
simulation, final block at the end of simulation
 Final block has to be executed in zero time, which implies it can't have any delay,
wait, or non-blocking assignments. Initial block doesn't have any such restrictions
of execution in zero time (and can have delay, wait and non-blocking statements)
 Final block can be used to display statistical/genaral information regarding the
status of the execution like this:-

final begin
$display("Simulation Passed");
$display("Final value of xyz = %h",xyz);
$display("Bye :: So long, and Thanks for all the fishes");
end
53 How to check weather a handles is holding object or not?
It is basically checking if the object is initialized or not. In SystemVerilog all
uninitialized object handles have a special value of null, and therefore whether it is
holding an object or not can be found out by comparing the object handle to null. So
the code will look like:-
usb_packet My_usb_packet;
if(My_usb_packet == null) begin
// This loop will get exited if the handle is not holding any
object end else begin
//Hurray ... the handle is holding an
object end
54 What are semaphores?
A semaphore is a bucket. When a semaphore is allocated ,a bucket that contains a
fixed number of keys is created .Processes using semaphores must first procure a key

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from the bucket before they can continue to execute. If a specific process requires a
key, only a fixed number of occurrences of that process can be in progress
simultaneously. All others must wait until a sufficient number of keys is returned to
the bucket. Semaphores are typically used for mutual exclusion, access control to
shared resources, and basic synchronization.
55 What is the use of always_ff?
SV adds an always_ff to indicate sequential logic.
56 How you will assign elements of an array directly in systemverilog?
//declaration of array’s
int array1[6];
int array2[5:0];
int array3[2:0][3:0];

//array initialization
array1 = '{0,1,2,3,4,5};
array2 = '{0,1,2,3,4,5};
array3 = '{'{0,1,2,3},'{4,5,6,7},'{8,9,10,11}};

57 What are the types of arrays in systemverilog?

Fixed array , dynamic array, associative array, queues
Fixed Array - It has fixed size of data, we cant change in run time
Packed Array - It represents continuous set of bits ,can be made of single bit data
types such as bit,logic,reg , dimensions declared before the object
syntax : bit[3:0] data ;
Unpacked Array - It does not represent continuous set of bits , can be made of any
data type ,can be made of any data type,dimensions are declared after the object
syntax : logic data [3:0];
Dynamic Array - It doesnt have any fixed data , it changes dynamically at run
time ,it is an unpacked array
syntax : bit [7:0] arr[ ]
-A dynamic array dimensions are specified by the empty square
brackets Methods in Dynamic Array
delete ()- delete entire array

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new[] - allocates a size for the array
size() - returns the size
- We can increase dynamic array size by overriding and retaining old values
Associative Array - It is sparse array, allocates randomly, the size of associative array
is unknown
syntax : [datatype] array_name[ * ] Methods in Associative
array Num()- returns number of entries Delete(index)- delete
particular element in an array Exist(index)- returns 1 if an
element exists in particular index First(var)- assigns first
index to variable var

Last(var) -assigns last index to variable var Next

(var) - assigns next index to variable var
Previous(var)- assigns previous index to variable
var Queues
- Collection of homogeneous elements , it supports adding/removing elements in an
array
- Queues are unpacked arrays
- these are bounded/unbounded
syntax : [data type] queue_name [$]
$ - specifies the array-size
Methods in Queue
delete () - delete particular element in an queue
insert() - inserts an element at particular index
push-front()-inserts an element at front of queue
pop-front()-removes an element at front of queue
push-back()-inserts an element at end of queue pop-
back()- removes an element at end of the queue

58 Why are assertions used?

Assertions are used to codify the requirements that render a program correct or not by
testing conditions (Boolean expressions) for true values, and notifying the developer
when such conditions are false. Using assertions can greatly increase your confidence

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in the correctness of your code.

59 What are the different types of constraints in systemverilog?

Inside constraints
Weighted Distribution constraints
Implication constraints
If else constraints
Iterative constraints
Inline constraints
Soft constraints
Unique constraints
Solve before constraints

60 What are inputs and output skews in clocking block?

If an input skew is specified then the signal is sampled at skew time units
before the clock event.
Similarly ,output signals are driven skew simulation time units(output
skew)after the corresponding clock event.
61 Mention the purpose of dividing time slots in systemverilog?
The purpose of dividing a time slot into these ordered regions is to provide predictable
interaction between the design and testbench code.

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62 What is static variable?
When a variable inside class is declared as static, that variable will be the only copy
in all class instance
Ex: static int static_ptr=0;

63 What is encapsulation, What is public declaration? What is difference between

local and protected.
In systemverilog, more likely to say, in OOPS, encapsulation is a process of hiding a
class members (properties/methods) from being accessed outside of class.
By default, members of class are public, so it can be accessible outside of class
directly using class handle and dot operator. But OOPS provides a feature to protect
or hide properties/methods of class from outside world.

In systemverilog, two keywords are specified to hide a class member.

local: This will ensure that the member is available only to the method of the same
class. Even, a local member will not be available to its extended classes. protected: If
we want to make the properties accessible in the extended classes but not outside the
classes. We can declare the properties as protected.

64 What is chandle in systemverilog ?

In System Verilog, ‘chandle’ is used to pass C pointers as arguments to DPI functions
or tasks.
65 What is DPI in systemverilog?
DPI (Direct Programming Interface) is used to call C, C++, System C functions inside
SV code.
66 What is a mailbox? What are all the methods available?
Mailboxes are a message-based process synchronization and communication
mechanism provided in SV. It allows messages to be exchanged between processes.
Conceptually, mailboxes behave like real mailboxes with delivery and retrieval of
messages. In this, data can be sent to mailbox by one process and retrieved by another.
Bounded and Unbounded Mailboxes
If maximum capapcity of the mailbox is specified along with the constructor, it is
called bounded mailbox. If you do not pass a value to constructor, it would be an

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unbounded mailbox. A bounded mailbox becomes full when it reaches the maximum
number of messages. But unbounded mailbox can never be full, as it has unlimited
capacity.
Following built-in methods are available to do communication using mailboxes.
new() : Create a mailbox
put() : Place a message in a mailbox
try_put() : Try to place a message in a mailbox without blocking
get() : Retrieve a message from a mailbox
try_get() : Try to retrieve a message from a mailbox without blocking
peek() : Copy a message from a mailbox without removing
try_peek() : Try to copy a message from a mailbox without blocking & removing
num() : Retrieve the number of messages in the mailbox
67 What is covergroup?
SystemVerilog covergroup is a user-defined type that encapsulates the specification of
a coverage model. They can be defined once and instantiated multiple times at
different places via the new function.

68 Difference between Associative and dynamic arrays?

Dynamic Array:
We use dynamic array when we have no idea about the size of the array during
compile time and we have to allocate its size for storage during run time.
We basically use this array when we have to store a contiguous or Sequential
collection of data.
The array indexing should be always integer type.
To allocate size of a dynamic array, we have to use new[] operator.
Example:
int my_array [];
initial
begin
my_array = new[4]; //Allocated 4 elements
end
Associative Array:
It is also allocated during run time.

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This is the array, where data stored in random fashion.
It is used when we don’t have to allocate contiguous collection of data, or data in a
proper sequence or index.
In associative array, the index itself associates the data. So it is called so.
Indexing is not regular, can be accessed using indexing like integer or string type or
any scalar.
Example:
my_array ["name"]; // “name”, Index type is a string
my_array[address]; // address, Index type is an integer (here address is an //integer).
my_array[my_class]; // my_class, Index type is a class.
my_array[s_array]; // s_array, Index type is an array.
It is better to use associative array, when size of the array is unknown & data space is
random or irregular or sparse.
69 How to check whether randomization is successful or not?
We can ensure that randomization has succeeded by using assert() function.
If randomization succeeds randomize() will return 1,else 0.
70 What is property in SVA?
It contains Boolean expressions and sequence. With help of sequence we can write the
property to check in assertion.
71 What are Assertion severity system level task? What happens if we won't specify
these tasks?
By default,the severity of an assertion failure is error. If we didn’t mention it, we
won’t get error if that statement fails.
72 In which event region concurrent assertions will be evaluated?
The concurrent assertions are sampled in prepone region and evaluated in the
observed region.
73 What is ## indicates?
##-Its indicate default one clock cycle in assertion
a ##1 b // a must be true on the current clock tick and b on the next clock tick a
##N b // Check b on the Nth clock tick after a
74 Difference between Queue and
array Queue
A Queue is a variable-size,ordered collection of homogeneous elements

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Queue support adding and removing elements in anywhere
Like a dynamic array, Queue can grow and shrink
Array is the collection of similar data items.
75 What is inheritance?
Inheritance is an OOP concept that allows the user to create classes that are built upon
existing classes.
The new class will be with new properties and methods along with having access to
all the properties and methods of the original class.
Example:

Class eth_good_pkt extends eth_pkt;

76 What is polymorphism?
Polymorphism allows an entity to take a variety of representations. Polymorphism
means the ability to request that the same Operations be performed by a wide range of
different types of things. Effectively, this means that you can ask many different
objects to perform the same action. Override polymorphism is an override of existing
code. Subclasses of existing classes are given a "replacement method" for methods in
the superclass. Superclass objects may also use the replacement methods when
dealing with objects of the subtype. The replacement method that a subclass provides
has exactly the same signature as the original method in the superclass.
Polymorphism allows the redefining of methods for derived classes
while enforcing a common interface. To achieve polymorphism the 'virtual' identifier
must be used when defining the base class and method(s) within that class.
77 What is the difference between function overloading and function overriding?
Function overloading is a feature that allows us to have same function more than
once in a program. Overloaded functions have same name but their signature must be
different.
Function overriding is a feature of OOPs Programming that allows us to override a
function of parent class in child class
78 What is the difference between “forever” ,“for” and “foreach” in SystemVerilog?
The “forever” loop repeatedly executes a statement without any limit. The only way

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execution can stop is by using a break statement. A forever loop if used without any
timing controls (like clock or time delay) can result in a zero-delay infinite loop and
cause hang in simulation.
The “for” loop is used for executing a statement for a defined number of times based
on conditions that are defined.
Foreach
Iterates over all elements of an array
Array can be fixed-size, dynamic, or associative
79 Difference between import and include
1) we use import for importing a package. Using import you can select components
of a package like a class or a task or "*" to import complete package.
2) we use include to physically place the code of a file while compiling. With include,
you just get entire code here but cannot have part of the include file.
80 Difference between module & class based TB?
In module based TB all constructs are static in nature, it required lot of memory space
and have less features to implement TB, but classes based TB is dynamic in nature
and involving oops concept to implement TB easily.
81 Difference between get() and peek() methods in mailbox.
get():
Blocking method until it can retrieve one message from the mailbox, if empty
blocks the process
Remove message from mailbox in FIFO order
peek():
Copies one message(in FIFO order) from the mailbox without removing
the message from the mailbox queue.
82 List out the coverage options and its usages.
at_least

A minimum number of hits for each bin. A bin with a hit count that is less than
the number is not considered covered. the default value is ‘1’.

auto_bin_max

A maximum number of automatically created bins when no bins are explicitly

defined for a coverpoint. the default value is ‘64’.

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cross_auto_bin_max

A maximum number of automatically created cross product bins for a cross. there
is no default value, it is unbounded.
83 What is the use of generator component in SV?
Generates the stimulus (create and randomize the transaction class) and send it to
Driver
84 What is the use of driver component in System Verilog TB?
Receives the stimulus (transaction) from a generator and drives the packet level data
inside the transaction into pin level to DUT
85 What is the functionality of monitor component in SV based TB?
Observes pin level activity on interface signals and converts into packet level which
is sent to the components such as scoreboard
86 What is the use of `define compiler directive, How is it differ from parameter?
The `define compiler directive is used to perform global macro substitution and
remain active for all files read/compiled after the macro definition.
It will available until another macro definition changes the value or until the macro is
undefined using the `undef compiler directive.
Parameter
Parameters must be defined within module boundaries using the keyword parameter.
A parameter is a constant that is local to a module that can optionally be redefined on
an instance. Parameters are typically used to specify the width of variables and time
delays.
87 Where can we use the compiler directives like `ifdef , `ifndef and `else
The `ifdef compiler directive checks for the definition of a text_macro_name. If the
text_macro_name is defined, then the lines following the `ifdef directive are included.
If the text_macro_name is not defined and an `else directive exists, then this source is
compiled.
The `ifndef compiler directive checks for the definition of a text_macro_name. If the
text_macro_name is not defined, then the lines following the `ifndef directive are
included. If the text_macro_name is defined and an `else directive exists, then this
source is compiled.

88 What are the ways can we trigger the covergroup?

There is two ways to trigger coverage collection in a covergroup

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Use sample() method of a particular covergroup to sample coverpoints
within that group.
Mention the event at which the covergroup should be sampled (ex. @posedge
clk)
89 Why do we need to define illegal and ignore bins?
Ignore bins are filtered from coverage including values included in other bins.
A set of values or transitions associated with a coverage-point can be
explicitly excluded from coverage by specifying them as ignore_bins.
Illegal bins are same as ignore_bins but they are trigger a runtime error
message. A set of values or transitions associated with a coverage-point can be
marked as illegal by specifying them as illegal_bins.

90 What is mean by implicit and explicit bins?

Automatic Bins or Implicit Bins
An automatically single bin will be created for each value of the coverpoint variable
range. These are called automatic, or implicit, bins.
Explicit bins
“bins” keyword is used to declare the bins explicitly to a variable.
A separate bin is created for each value in the given range of variable or a
single/multiple bins for the rage of values.

91 How will you define a transition bins?

The transition of coverage point can be covered by specifying the sequence,
value1 => value2
It represents transition of coverage point value from value1 to value2.
sequence can be single value or range,
value1 => value2 => value3 ….
range_list_1 => range_list_2
bins b1 = (10=>20=>30); // transition from 10->20->30
92 What are the types of code coverage?
Statement coverage /line
coverage Block/segment coverage
Conditional coverage

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Branch coverage
Toggle coverage
Path coverage
Fsm coverage
93 List the system tasks that will be used in functional coverage.
System Verilog provides set of system tasks to help manage coverage data collection
as shown bellow
 $set_coverage_db_name(name)
 $load_coverage_db(name)
 $get_coverage()
94 What is the difference between assert, assume and cover?
Assert
The assert statement is used to enforce a property as a verifier. It can report an
action based on the pass or failure of the assertions.
The assert statement is one of the key directives in verification because it
makes a statement about what the desired property should be.
The tool is responsible for reporting errors and for maintaining statistics about
the assertions.
This statement specifies if the property holds correct.
Assume
The purpose of the assume statement is to allow properties to be considered
as assumptions or constraints for formal analysis, as well as for dynamic
simulation tools.
When an expression or a property is assumed, the formal verification tools
constrain the design inputs so that the property holds.
This statement specifies property as assumption for the verification
enviroment. This is more usefull with formal verification tools.

Cover :
This statement monitors property for the sake of coverage. Coverage can be
made to be reported at the end of simulation.

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95 What are the type of implication used inside the property for assertion?
Overlapped implication(|->)

Non- overlapped implication(|=>)

96 What is the use of $onehot, $onehot0, $isunknown and $countones?

$onehot(expression)
 checks that only one bit of the expression can be high on any given clock
edge.
$onehot0(expression)
 checks only one bit of the expression can be high or none of the bits can be
high on any given clock edge.
$isunknown(expression)
 checks if any bit of the expression is X or Z.
$countones(expression)
 counts the number of bits that are high in a vector.
97 Mention some methods that will be use for array manipulation.
find() Returns all elements satisfying the given expression
find_index() Returns the indices of all elements satisfying the given
expression
find_first() Returns the first element satisfying the given expression
find_first_index() Returns the index of the first element satisfying the given
expression
find_last()Returns the last element satisfying the given expression
find_last_index() Returns the index of the last element satisfying the
given expression
98 For this Array, [5:0]Arr[3:0];
What is the value for $bits(Arr), $size(Arr,1), $right(Arr,1),$left(Arr,1)
and $increment(Arr,1) and $dimensions(Arr)
bit [5:0]arr [3:0];
$bits(Arr):24
$size(Arr,1):4
$right(Arr,1):0

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$left(Arr,1):3
$increment(Arr,1): 1
$dimensions(Arr): 2
99 What is the use ‘break’ and ‘continue’ constructs?
break
The execution of a break statement leads to the end of the loop.
break shall be used in all the loop constructs (while, do-while, foreach, for,
repeat and forever).
continue
Execution of continue statement leads to skip the execution of statements
followed by continue and jump to next loop or iteration value.
100 What are the ways we can pass the arguments to a function?
Argument pass by value
Argument pass by
reference Argument pass
by name
Argument pass by position

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