VTU 3rd SEM

DDCO | BCS302

Model Question Paper-2

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Test benches are used to simulate your design without the need of any physical hardware.
Before you can simulate your design you must first write a test bench.

//Design code // Testbench Code

module half_adder(a, b, sum, carry);
module half_adder_tb;
input a,b; reg a,b;
output sum,carry; wire sum,carry;
assign carry=a&b; half_adder dut ( .a(a),.b(b),.sum(sum), .carry(carry));
assign sum=a^b;
initial begin
endmodule
a=1'b0;b=1'b0;
#100 a=1'b0;b=1'b1;
#100 a=1'b1;b=1'b0;
#100 a=1'b1;b=1'b1;
#100 a=1'b0;b=1'b0;
#100 $finish;
end

endmodule
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CD
CD AB 00 01 11 10
AB 00 01 11 10
00 1 0 0 0
00 1 0 0 0 0 1 3 2
0 1 3 2
01 0 0 0 1
01 0 0 0 1 4 5 7 6
4 5 7 6
11 0 1 0 1
11 0 1 0 1 12 13 15 14
12 13 15 14
1 0 0 0
10
1 0 0 0 10
8 9 11 10
8 9 11 10
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CD CD
00 01 11 10 AB 00 01 11 10
AB

00 0 0 0 1 00 0 0 0 1
0 1 3 2 0 1 3 2

01 1 0 0 0 01 1 0 0 0
4 5 7 6 4 5 7 6

11 0 0 0 0 11 0 0 0 0
12 13 15 14 12 13 15 14

0 0 0 1 10
0 0 0 1
10 8
8 9 11 10 9 11 10
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 CD Click here for Explanation
00 01 11 10 CD
AB 00 01 11 10
AB
00 1 1 1 0 00 1 1 0 1
0 1 3 2
0 1 3 2
01 0 0 1 0 01 1 1 1 1
4 5 7 6 4 5 7 6

11 0 1 1 0 0 0 1 0
11
12 13 15 14 12 13 15 14

10
1 1 0 1 0 0 0 1
8 9 11 10 10
8 9 11 10
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Dataflow modeling in Verilog is a style that uses continuous assignment statements (assign) to describe
hardware by describing the flow of data from input to output.
It's mainly used to model combinational circuits, or expressions, by describing them by their function rather
than by their gate structure.

// Design code in Dataflow

module half_adder(a, b, sum, carry);

input a, b;
output sum, carry;

assign carry = a&b;

assign sum = a^b;

endmodule
 Full Adder Click here for Explanation
▪ A full adder adds two inputs and a carried input from another adder, and also gives a two-bit Resultput (Sum and Carry
bit)
 Full Subtractor
D (Difference) Click here for Explanation
Full Subtractor
BResult (Borrow)
D BResult

Bin

A = 1 A = 0
B = -0 B = -1
BResult=0 D = 1 BResult=1 D = 1
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The octal-to-binary encoder consists of eight inputs, one for each of the eight digits, and three outputs that generate
the corresponding binary number.
Input Output B2 = (I4 + I5 + I6 + I7)
B2 B1 B0
B1 = (I2 + I3 + I6 + I7)
I0 0 0 0
B0 = (I1 + I3 + I5 + I7)
I1 0 0 1

I2 0 1 0

I3 0 1 1

I4 1 0 0

I5 1 0 1

I6 1 1 0

I7 1 1 1
 A B

4 Bit Parallel Adder / Ripple Carry Adder

C3 C2 C1 C0 4 Bit Adder
A3 A2 A1 A0
B3 B2 B1 B0
C4 S3 S2 S1 S0 C S
A3 B3 A2 B2 A1 B1 A0 B0
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C3 C2 C1
C4 Full Adder Full Adder Full Adder Full Adder C0

S3 S2 S1 S0

EXPLORE ELECTRONICS
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Here, N=7000
S=3
R = 700KHz T = (7000 X 3) / 700 KHz
=700000 cycles per sec T = 0.03
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