EE 312 :Embedded System

Assignment – 1
Devansh Singh
210108014

Utilise MOS as a variable resistor and simulate it.

Circuit Diagram in LTSpice

NetList Code :

Approach Explanation :
The NMOS transistor circuit shown creates a variable resistor by
adjusting the gate-to-source voltage (Vgs). The channel resistance
between the source and drain of the NMOS transistor is controlled by
Vgs, where higher Vgs results in lower channel resistance, and lower Vgs
leads to higher resistance. The resistance (Rds) is given by the equation:
Rds =
1 / (𝐾𝑛 × (𝑊/𝐿) × (𝑉𝑔𝑠 − 𝑉𝑡)2)

Where:
● Rds is the channel resistance in ohms

●● Kn is the NMOS transistor transconductance in 𝐴/𝑉2

W is the width of the NMOS transistor gate in metres

● L is the length of the NMOS transistor gate in metres
● Vgs is the gate-to-source voltage in volts
● Vt is the NMOS transistor threshold voltage in volts

This equation shows that varying Vgs controls the NMOS transistor
channel resistance, a ecting the overall circuit resistance.
The circuit exploits this property of the NMOS transistor to create a
variable resistor. The NMOS transistor's gate is connected to a voltage
source (Vgs) controlled by a potentiometer. Rotating the potentiometer
changes Vgs, altering the resistance of the NMOS transistor channel.

● High Vgs results in low channel resistance and high current ow. ●
Low Vgs leads to high channel resistance and low current ow.
● Rotating the potentiometer adjusts Vgs, varying the NMOS
transistor channel resistance and the circuit's current.

This simple circuit produces a variable resistor with a wide range of

resistance values. The range depends on the NMOS transistor
characteristics and the Vgs voltage range.
The plot depicting id versus Vds illustrates how the drain current (id)
changes concerning the drain-to-source voltage (Vds) in the NMOS
transistor for varying gate-to-source voltage (Vgs) values. The graph indicates
that as the Vgs voltage rises, the id versus Vds curve becomes steeper,
implying a decrease in the resistance of the NMOS transistor channel.

In summary, the outcomes a rm the functionality of the variable resistor

circuit. The circuit operates as anticipated, with the gate-to-source voltage
(Vgs) e ectively controlling the resistance of the variable resistor. Notably,
the variable resistor exhibits a broad range of resistance values.

Task 2 : Utilise MOS as a variable capacitor and simulate it.

Circuit Diagram :
NetList Code :

In this setup, the MOSFET is con gured in a common-source

arrangement, where the gate and source are connected to ground, and
the drain is linked to a voltage source (Vds).
The capacitance of the MOSFET relies on the MOSFET geometry and
the gate-to-source voltage (Vgs). The capacitance increases with higher
Vgs and diminishes with shorter channel length (L) and width (W) of
the MOSFET.
The capacitance of the MOSFET is given by the equation:

Cgs =
𝐾𝑛 × (𝑊/𝐿) × (𝑉𝑔𝑠 − 𝑉𝑡)2

Where:

● Cgs is the gate-to-source capacitance in farads ● Kn is the NMOS

transistor transconductance in 𝐴/𝑉2

● W is the width of the NMOS transistor gate in metres

● L is the length of the NMOS transistor gate in metres
● Vgs is the gate-to-source voltage in volts
● Vt is the NMOS transistor threshold voltage in volts.

The graph illustrates the dependency of MOSFET capacitance on the

voltage source (Vds), with higher Vds resulting in increased capacitance
and lower Vds leading to reduced capacitance.
The graph below illustrates the Capacitance vs Voltage (C-V) curve for the
MOSFET capacitor circuit, with capacitance measured at the gate and drain
of the MOSFET.

In the presented circuit, the MOSFET is employed as a capacitor by

grounding the gate and source, while the drain connects to a voltage source
(Vds). The voltage source (Vds) serves to manipulate the capacitance of the
MOSFET.

● A high Vds elevates the gate-to-source voltage (Vgs), resulting in

increased MOSFET capacitance.
● A low Vds diminishes the Vgs, leading to reduced MOSFET
capacitance.

By adjusting the voltage source (Vds), the capacitance of the MOSFET

becomes controllable, allowing the creation of a variable capacitor with a
broad range of capacitance values.
The graph depicting the relationship between gate voltage (Vg) and
frequency reveals a decline in MOSFET capacitor capacitance as frequency
increases. This decline stems from the MOSFET capacitor not being a purely
capacitive element but possessing some inherent resistance. The resistance of
the MOSFET channel rises with frequency, leading to a reduction in
capacitor capacitance.

To counteract this frequency-dependent decrease in capacitance, a solution

involves connecting the MOSFET capacitor in parallel with a xed capacitor.
The xed capacitor's value should be carefully selected to ensure that, at the
desired frequency, the total capacitance of the circuit matches the intended
capacitance.

Conclusion:
The outcomes a rm the functionality of the MOSFET capacitor circuit.
The capacitance of the MOSFET capacitor is e ectively modulated by
adjusting the voltage source (Vds), showcasing a wide range of capacitance
values.
Task 3 : Design and simulate the SRAM and DRAM circuits.

SRAM ( Static Random Access Memory) :

Circuit Diagram :

NetList Code :

Theory and Approach:

A 6T SRAM cell, a form of static random-access memory (SRAM), utilizes six

transistors to store a single bit. It employs two cross-coupled inverters controlled
by a word line (WL) to store and amplify data. Transistors M5 and M6 enable
controlled access and sensing.
Simulation:

To simulate the 6T SRAM circuit in LTspice, con gure transistors, add

components, connect as per the provided diagram, set MOSFET parameters, apply
a 5V voltage source, and perform a transient analysis.

Results:

The word line signal is followed by the 6T SRAM circuit's output, according to
the simulation result for wordline vs. output. Depending on the value of the data
bit stored in the cell, the output of the SRAM cell is stable at either Vdd or GND
while the word line is low. The output of the SRAM cell is ampli ed by the
sensing ampli er and output to the output terminal when the word line is high.

The outcome of the simulation also demonstrates how little time there is between
the word line and the output. This is a result of the 6T SRAM circuit's extreme
speed. It has incredibly quick reading and writing speeds.
The simulation result for wordline vs output shows that the output of the 6T
SRAM circuit follows the word line signal. When the word line is low, the output
of the SRAM cell is stable at either Vdd or GND, depending on the value of the
data bit that is stored in the cell. When the word line is high, the output of the
SRAM cell is ampli ed by the sense ampli er and output to the output terminal.

Simulation con rms the 6T SRAM circuit's functionality, demonstrating stable

storage and e cient data read/write operations. The output closely tracks the word
line signal, and the sense ampli er e ectively ampli es small voltage di erences,
ensuring rapid response times.

Conclusion:

The 6T SRAM circuit, with its minimal delay and simplicity, emerges as an e
cient means of storing a single bit. The simulation a rms its successful operation,
making it a viable choice for SRAM memory simulations in LTspice.

DRAM ( Dynamic Random Access Memory) :

Circuit Diagram :
NetList Code :

Theory and Approach:

A DRAM cell, a variant of dynamic random-access memory (DRAM), utilizes a

single transistor and a capacitor to store one bit. The transistor functions as a
switch, controlling charge ow into and out of the capacitor, which holds the data as
charge.
For reading, the transistor is activated, and the capacitor's charge is sensed. A
charged capacitor indicates a data bit of 1, while a discharged capacitor represents a
0.

Writing involves activating the transistor and charging the capacitor to a speci ed
voltage. For a desired bit of 1, the capacitor is charged to a high voltage, and for a
bit of 0, it is charged to a low voltage.

Approach:

The DRAM circuit uses a single transistor (M1) and a capacitor (C1) to store one
bit. The word line (WL) controls cell access. When WL is low, M1 is o , isolating
C1. When WL is high, M1 is on, connecting C1 to the bit line (BL) and bit bar line
(BLB). A sense ampli er ampli es the voltage di erence between BL and BLB,
outputting the data bit.

Simulation:

Simulating the DRAM circuit in LTspice involves creating a schematic, adding

components (M1, C1), a voltage source (Vdd), and ground (GND). Connect
components, set parameters per the datasheet, set Vdd to 5V, and run a transient
analysis.
Results:

When the word line (WL) is low, the output is stable at either Vdd or GND,
depending on the value of the data bit that is stored in the DRAM cell. When the
word line (WL) is high, the output follows the bit line signal, but is delayed by a
small amount of time due to the propagation delay of the sense ampli er M6.

Simulation con rms the DRAM circuit's functionality. With WL low, C1 is isolated.
With WL high, C1 connects to BL and BLB. Reading involves WL going high, and
a sense ampli er ampli es the voltage di erence between BL and BLB, yielding the
data bit.

Writing entails setting WL high and adjusting the voltage on BL. C1 then charges
to match BL voltage.

Conclusion:

The DRAM circuit o ers a straightforward means to store one bit of data. Its
implementation in LTspice facilitates simulation, showcasing the e ective operation
of DRAM memory.

References :
1. https://www.allaboutcircuits.com/technical-articles/introduction-
t o-dram-dynamic-random-access-memory/
2. https://electronics.stackexchange.com/questions/499446/simulati
n g-nmos-as-capacitor-example
3. https://www.researchgate.net/ gure/The-plot-of-CV-curves-at-di
erent-scan-rates_ g2_346810833
4. https://www.wikipedia.org/