ABDELRAHMAN KHALED ABDELBADEE

Address: Haram, Giza| +201121751664| abdo.khaled.2022Comm@gmail.com

EDUCATION
Cairo University – Faculty of Engineering – B.Sc. Electronics and electrical communications [2017 - 2022]
❖ Graduation year: 2022
❖ Last year grade: Very Good
❖ Cumulative grade: Very Good [78 %]
❖ Graduation Project grade: Excellent

EXPERIENCE

Digital design internship at Si-Vision covers the following topics: [ Sep 2021]
Electronics and logic basics, RTL coding using Verilog HDL, understanding timing concepts and constrains
in digital systems.

COURSES

Digital ASIC course

❖ Concepts of logic synthesis flow explaining Timing concepts, and how to implement timing constraints.
❖ Basic concepts of ASIC implementation flow explaining the stages of ASIC flow, such as [ Floor planning,
Power planning, Placement, CTS, and Routing], and the main concepts in each stage.

Digital Verification Course

❖ Basic concepts of verification
❖ System Verilog HDL explaining the differences between SV and Verilog HDL. New concepts like classes,
Randomization, Coverage, etc.
❖ UVM hierarchy, Components, Objects, etc. Building full UVM environment.

PROJECTS

Graduation Project
❖ Title: Automated flow for fast generation & verification of custom CNN AI Accelerators on FPGA
Prototyping Systems, Sponsored by Siemens.
❖ Description: Project is considered a tool that takes any CNN model and generates the corresponding
accelerator RTL in Verilog, that is verified and ready to run on FPGA. The tool supports RTL generation of
any custom model consists of the following layers [ Convolution (Normal - Winograd - Depth wise),
 Pooling (Average, Max), Dense Layer], and following features [ Batch normalization – Dropout - Stride
1,2 – Padding - Flatten]. Also, the tool supports parallelism that increases computation units to increase
accelerator performance. Generation of Accelerator RTL is automated using Perl scripting.
❖ Supervisors: Dr Mohamed AbdelSalam & Dr Karim Osama Abbas.

SPI Communication protocol [Slave Model]

❖ Design: A SPI Slave, that has 2 operations [Write mode – Read mode] depending on the received frame.
The received frame consists of 3 arguments. The first argument is the command, which selects the
intended operation. The second argument is the address where the data is written or read. The third
argument is the data being received or transmitted to SPI master. Also, the slave supports Multi-Write
and Multi-Read transactions.
❖ Verification: Develop a UVM environment that verifies SPI operations.

32-Bit general purpose MIPS-like processor with RISC ISA Code of the processor is written using VHDL then
synthesized and implemented on Xilinx ISE program. The processor is then tested with simple factorial
calculator on simulation in Xilinx ISE program it consists of 3 main parts:

❖ VHDL in this part the code of the processor was written then synthesized on Xilinx ISE program

❖ Assembler Written in C program takes the assembly code as text file of the application and outputs
the binary which is then used in processor.
❖ PCB

SKILLS

• HDL Verilog, System Verilog

• Software: C programming, C++, MATLAB, Perl

• Simulation tools: QuestaSim, Xilinx ISE, Xilinx Vivado, ModelSim, Multisim, Proteus, Altium designer
• Language Very good in speaking and writing English

• Personal skills: Self Motivated, Cooperative and team worker, Good communications skills and Ability for self-learning
on different fields
PERSONAL INFO

• Birth Date: 1/1/2000

• Military Status: Completed [ Oct 2022 – Dec 2023]