IM34M06P12-02E Us

Instruction
Manual
Sequence CPU Instruction
Manual - Functions
(for F3SP21, F3SP25 and
F3SP35)
IM 34M6P12-02E
IM 34M6P12-02E
3rd Edition
Yokogawa Electric Corporation
Blank Page
i
Applicable Product:
● Range-free Multi-controller FA-M3
• Model Name: F3SP21, F3SP25, F3SP35, F3SP05-0P, F3SP08-0P
• Name: Sequence CPU Modules
The document number and document code for this manual are as follows:
Refer to the document number in all communications; also refer to the document number or
the document model code when purchasing copies of this manual.
• Document No.: IM34M6P12-02E
• Document Code: DOCIM
CAUTION
The functions of the F3SP28, F3SP38, F3SP53 and F3SP58 sequence CPU modules
are not explained in this manual. For information on these functions, refer to Sequence
CPU Instruction Manual - Functions (for F3SP28, F3SP38, F3SP53 and F3SP58)
(IM34M6P13-01E).
Media No. IM 34M6P12-02E (CD) 3rd Edition : Oct 2001 (AR) IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00
All Rights Reserved Copyright © 1998, Yokogawa Electric Corporation
ii
Important
■ About This Manual
- This Manual should be passed on to the end user.
- Before using the controller, read this manual thoroughly to have a clear understanding
of the controller.
- This manual explains the functions of this product, but there is no guarantee that they
will suit the particular purpose of the user.
- Under absolutely no circumstances may the contents of this manual be transcribed or
copied, in part or in whole, without permission.
- The contents of this manual are subject to change without prior notice.
- Every effort has been made to ensure accuracy in the preparation of this manual.
However, should any errors or omissions come to the attention of the user, please
contact the nearest Yokogawa Electric representative or sales office.
■ Safety Precautions when Using/Maintaining the Product

- The following safety symbols are used on the product as well as in this manual.
Danger. This symbol on the product indicates that the operator must follow the instruc-
tions laid out in this instruction manual to avoid the risk of personnel injuries, fatalities,
or damage to the instrument. The manual describes what special care the operator
must exercise to prevent electrical shock or other dangers that may result in injury or
the loss of life.
Protective Ground Terminal. Before using the instrument, be sure to ground this
terminal.
Function Ground Terminal. Before using the instrument, be sure to ground this
terminal.
Alternating current. Indicates alternating current.
Direct current. Indicates direct current.
IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

iii
The following symbols are used only in the instruction manual.
WARNING
Indicates a “Warning”.
Draws attention to information essential to prevent hardware damage, software
damage or system failure.
CAUTION
Indicates a “Caution”
Draws attention to information essential to the understanding of operation and func-
tions.
TIP
Indicates a “TIP”
Gives information that complements the present topic.
SEE ALSO
Indicates a “SEE ALSO” reference.
Identifies a source to which to refer.
- For the protection and safe use of the product and the system controlled by it, be sure
to follow the instructions and precautions on safety stated in this manual whenever
handling the product. Take special note that if you handle the product in a manner
other than prescribed in these instructions, the protection feature of the product may
be damaged or impaired. In such cases, Yokogawa cannot guarantee the quality,
performance, function and safety of the product.
- When installing protection and/or safety circuits such as lightning protection devices
and equipment for the product and control system as well as designing or installing
separate protection and/or safety circuits for fool-proof design and fail-safe design of
processes and lines using the product and the system controlled by it, the user should
implement it using devices and equipment, additional to this product.
- If component parts or consumable are to be replaced, be sure to use parts specified
by the company.
- This product is not designed or manufactured to be used in critical applications which
directly affect or threaten human lives and safety - such as nuclear power
equipment, devices using radioactivity, railway facilities, aviation equipment, air
navigation facilities, aviation facilities or medical equipment. If so used, it is the user’s
responsibility to include in the system additional equipment and devices that ensure
personnel safety.
- Do not attempt to modify the product.
■ Exemption from Responsibility

- Yokogawa Electric Corporation (hereinafter simply referred to as Yokogawa Electric)
makes no warranties regarding the product except those stated in the WARRANTY
that is provided separately.
- Yokogawa Electric assumes no liability to any party for any loss or damage, direct or
indirect, caused by the user or any unpredictable defect of the product.

iv
■ Software Supplied by the Company
- Yokogawa Electric makes no other warranties expressed or implied except as pro-
vided in its warranty clause for software supplied by the company.
- Use the software with one computer only. You must purchase another copy of the
software for use with each additional computer.
- Copying the software for any purposes other than backup is strictly prohibited.
- Store the original media, such as floppy disks, that contain the software in a safe
place.
- Reverse engineering, such as decompiling of the software, is strictly prohibited.
- No portion of the software supplied by Yokogawa Electric may be transferred, ex-
changed, or sublet or leased for use by any third party without prior permission by
Yokogawa Electric.

v
■ General Requirements for Using the FA-M3 Controller
● Avoid installing the FA-M3 controller in the following locations:

- Where the instrument will be exposed to direct sunlight, or where the operating tem-
perature exceeds the range 0°C to 55°C (0°F to 131°F).
- Where the relative humidity is outside the range 10 to 90%, or where sudden tempera-
ture changes may occur and cause condensation.
- Where corrosive or flammable gases are present.
- Where the instrument will be exposed to direct mechanical vibration or shock.
- Where the instrument may be exposed to extreme levels of radioactivity.
● Use the correct types of wire for external wiring:

- Use copper wire with temperature ratings greater than 75°C.
● Securely tighten screws:

- Securely tighten module mounting screws and terminal screws to avoid problems
such as faulty operation.
- Tighten terminal block screws with the correct tightening torque as given in this
manual.
● Securely lock connecting cables:

- Securely lock the connectors of cables, and check them thoroughly before turning on
the power.
● Interlock with emergency-stop circuitry using external relays:

- Equipment incorporating the FA-M3 controller must be furnished with emergency-stop
circuitry that uses external relays. This circuitry should be set up to interlock correctly
with controller status (stop/run).
● Ground for low impedance:

- For safety reasons, connect the [FG] grounding terminal to a Japanese Industrial
Standards (JIS) Class D Ground*1 (Japanese Industrial Standards (JIS) Class 3
Ground). For compliance to CE Marking, use cables such as twisted cables which can
ensure low impedance even at high frequencies for grounding.
*1
Japanese Industrial Standards (JIS) Class D Ground means grounding resistance of 100Ω max.
● Configure and route cables with noise control considerations:

- Perform installation and wiring that segregates system parts that may likely become
noise sources and system parts that are susceptible to noise. Segregation can be
achieved by measures such as segregating by distance, installing a filter or
segregating the grounding system.
● Configure for CE Marking Conformance:

- For compliance to CE Marking, perform installation and cable routing according to
the description on compliance to CE Marking in the “Hardware Manual”
(IM34M6C11-01E).

vi
● Keep spare parts on hand:
- Stock up on maintenance parts including spare modules, in advance.
● Discharge static electricity before operating the system:

- Because static charge can accumulate in dry conditions, first touch grounded metal to
discharge any static electricity before touching the system.
● Never use solvents such as paint thinner for cleaning:

- Gently clean the surfaces of the FA-M3 controller with a cloth that has been soaked in
water or a neutral detergent and wringed.
- Do not use volatile solvents such as benzine or paint thinner or chemicals for cleaning,
as they may cause deformity, discoloration, or malfunctioning.
● Avoid storing the FA-M3 controller in places with high temperature or

humidity:
- Since the CPU module has a built-in battery, avoid storage in places with high
temperature or humidity.
- Since the service life of the battery is drastically reduced by exposure to high
temperatures, take special care (storage temperature should be from -20°C to 75°C).
- There is a built-in lithium battery in a CPU module and temperature control module
which serves as backup power supply for programs, device information and
configuration information. The service life of this battery is more than 10 years in
standby mode at room temperature. Take note that the service life of the battery
may be shortened when installed or stored at locations of extreme low or high
temperatures. Therefore, we recommend that modules with built-in batteries be stored
at room temperature.
● Always turn off the power before installing or removing modules:

- Failing to turn off the power supply when installing or removing modules, may result in
damage.
● Do not touch components in the module:

- In some modules you can remove the right-side cover and install ROM packs or
change switch settings. While doing this, do not touch any components on the
printed-circuit board, otherwise components may be damaged and modules may fail
to work.

vii
Waste Electrical and Electronic Equipment
Waste Electrical and Electronic Equipment (WEEE), Directive 2002/96/EC
(This directive is only valid in the EU.)
This product complies with the WEEE Directive (2002/96/EC) marking requirement.
The following marking indicates that you must not discard this electrical/electronic product
in domestic household waste.
Product Category
With reference to the equipment types in the WEEE directive Annex 1, this product is
classified as a “Monitoring and Control instrumentation” product.
Do not dispose in domestic household waste.
When disposing products in the EU, contact your local Yokogawa Europe B. V. office.

viii
Introduction
■ Overview of the Manual
This manual describes the sequencing functions of the F3SP21, F3SP25 and F3SP35
sequence CPU modules designed for use with the FA-M3 Range-free Multi-controller
and the F3SP05-0P and F3SP08-0P sequence CPU module designed for use with
small-scale controllers.
■ Structure of the Manual

This manual consists of three parts:
● Part A: Standard Version

The main part of this manual explains the functions of the sequence CPU modules, exclud-
ing the F3SP05-0P and the F3SP08-0P, for use with the FA-M3 system.
● Part B: F3SP05-0P Sequence CPU for FA-M3 Value

The second part of this manual explains the functions specific to the F3SP05-0P sequence
CPU module.
● Part C: F3SP08-0P Sequence CPU for FA-M3 Value II

The third part of this manual explains the functions specific to the F3SP08-0P sequence
CPU module.
Chapters corresponding to Chapters A3 to A8 of Part A “Standard Version” are not included
in Part B and Part C. When using the F3SP05-0P sequence CPU and the F3SP08-0P,
assume the F3SP05-0P and the F3SP08-0P to be Model F3SP21 and refer to the relevant
paragraphs of these chapters where the F3SP21 is discussed.

ix
■ How to Read the Manual
If you are a first-time reader of this manual, first go through this paragraph, “How to Read
the Manual,” and proceed to Chapter A1, then Chapter A3.
For efficiency, read only the relevant remaining chapters according to your flow of work,
from system design to system operation.
The chart below shows the regular work flow, from system design to system operation, as
well as chapters you should refer to in each step.
● Work Flow from System Design to System Operation, and Chapters to Be

Referred to
Target machine
Design
Start
Start
Determination of system configuration

System design Chapter A2, "System Configuration" Wiring
Assignment of I/Os, registers and relays Input: Verification of I/Os with LED lamps
Basic design I/O verification Output: Forced SET and RESET instructions
Chapter A4, "Devices," and
Chapter A6, "Functions"
Chapter A5, "Programs"
Program downloading
Coding Configuration of a ladder diagram
Ladder symbols Debugging Program modification

Programming Mnemonic language
Trial operation Chapter A6, "Functions"
Chapter 1, "Overview of Instruction Words,"
Chapter 2, "Basic Instructions," and
Chapter 3, "Advanced Instructions,"
in the Instructions volume of the 2nd or later ? End of flow?
edition of the Sequence CPUs instruction
manual Program storage on floppy/hard disk or
End in ROM pack
Program input for Verification of basic logic
simulation Program modification
Performance check Chapter A6, "Functions"
? End of flow?
Program storage on floppy/hard disk or

End in ROM pack F000001.EPS

x
■ Notational Conventions
● Symbol Marks Used in This Manual

The following symbol marks are used in this manual.
F3SP21
F3SP25 : Refers to a topic that applies to the F3SP21, F3SP25 and F3SP35.
F3SP35
F3SP25
F3SP35 : Refers to a topic that applies to the F3SP25 and F3SP35.
In the absence of any symbol mark, it should be assumed that the topic applies to the
F3SP21, F3SP25 and F3SP35.
■ Other Instruction Manuals
CAUTION
The functions of the F3SP28, F3SP38, F3SP53 and F3SP58 sequence CPU modules are
not explained in this manual. For information on these functions, refer to the instruction
manual (IM34M6P13-01E), Sequence CPU Instruction Manual - Functions (for F3SP28,
F3SP38, F3SP53 and F3SP58).
Be sure to read each of the following manuals, in addition to this manual.
● For information on the instructions used with sequence CPUs, refer to:
• Sequence CPU Instruction Manual - Instructions (IM34M6P12-03E).
● For information on the specifications*, configuration, installation, wiring,

trial operation, maintenance and inspection of the FA-M3, as well as infor-
mation on the system-wide limitation of module installation, refer to:
• Hardware Manual (IM34M6C11-01E) .
* For information on the specifications of products other than the power supply module, base module, I/O module,
cable and terminal block unit, refer to their respective instruction manuals.
● When creating programs using ladder language, refer to:

• FA-M3 Programming Tool WideField Instruction Manual (IM34M6Q14-01E); and
• FA-M3 Programming Tool WideField - Instruction Manual-Applications
(IM34M6Q14-02E).
- or -
• Ladder Diagram Support Program M3 Instruction Manual (IM34M6Q13-01E).
Read the following instruction manuals, as necessary.

xi
● For information on the functions of fiber-optic FA-bus modules, refer to:
• Fiber-optic FA-bus Module and Fiber-optic FA-bus Type 2 Module Instruction Manual
(IM34M6H45-01E) .
● For information on the functions of FA link H and fiber-optic FA link H

modules, refer to:
• FA Link H Module F3LP02-0N Fiber-optic FA Link H Module F3LP12-0N
(IM34M6H43-01E).
● For information on the functions of F3SP28, F3SP38, F3SP53 and F3SP58

sequence CPU modules, refer to:
• Sequence CPU Instruction Manual - Functions (for F3SP28, F3SP38, F3SP53 and
F3SP58) (IM34M6P13-01E).
● For information on the functions of BASIC CPU modules, refer to:

• BASIC CPU Modules and YM-BASIC/FA Programming Language Instruction Manual
(IM34M6Q22-01E).
● For information on the functions of the F3FP36 sequence CPU module,

refer to:
• Sequence CPU - Functions Instruction Manual (for F3FP36) (IM34M6P22-01E).

xii
Copyright and Trademarks

■ Copyrights
Copyrights of the programs and online manual included in this CD-ROM belong to
Yokogawa Electric Corporation.
This online manual may be printed but PDF security settings have been made to prevent
alteration of its contents.
This online manual may only be printed and used for the sole purpose of operating this
product. When using a printed copy of the online manual, pay attention to possible
inconsistencies with the latest version of the online manual. Ensure that the edition
agrees with the lateat CE-ROM version.
Copying, passing selling or distribution (including transferring over computer networks)
of the contents of the online manual, in part or in whole, to any third party, is strictly
prohibited. Registering or recording onto videotapes and other media is also prohibited
without expressed permission of Yokogawa Electric Corporation.
■ Trademarks
The trade names and company names referred to in this manual are either trademarks
or registered trademarks of their respective companies.

Toc-1
Sequence CPU Instruction Manual - Functions

(for F3SP21, F3SP25 and F3SP35)
IM 34M6P12-02E 3rd Edition
CONTENTS
Applicable Product ............................................................................................... i
Important ...............................................................................................................ii
Introduction ........................................................................................................ viii
Copyrights and Trademarks ...............................................................................xii
PART A for F3SP21, F3SP25 and F3SP35

A1. Specification and Basic Configuration ................................................ A1-1
A1.1 Overview ........................................................................................................ A1-1
A1.1.1 CPU Modules ................................................................................. A1-1
A1.2 Specification ................................................................................................. A1-3
A1.2.1 Table of Performance Data .............................................................. A1-3
A1.2.2 Device List ...................................................................................... A1-5
A1.2.3 Configuration .................................................................................. A1-7
A1.2.4 Components and Their Functions ................................................. A1-12
A1.2.5 External Dimensions ..................................................................... A1-13
A1.3 Basic configuration .................................................................................... A1-14
A1.3.1 Unit ............................................................................................... A1-14
A1.3.2 Slot Number ................................................................................. A1-15
A1.3.3 I/O Relay Number ......................................................................... A1-17
A2. System Configuration .......................................................................... A2-1
A2.1 Basic System Configuration ........................................................................ A2-1
A2.2 Multi-CPU System Configuration ................................................................. A2-1
A2.2.1 Multi-CPU System Configuration .................................................... A2-1
A2.2.2 Handling I/O Modules in Multi-CPU System .................................... A2-2
A2.3 Extended System Configuration .................................................................. A2-3
A2.3.1 Remote I/O System ........................................................................ A2-3
A2.3.2 Personal Computer Link System ..................................................... A2-3
A2.3.3 FA Link System ............................................................................... A2-4
A2.4 Programming Tools ....................................................................................... A2-5
A2.4.1 WideField ....................................................................................... A2-5
A2.4.2 Ladder Diagram Support Program M3 ............................................ A2-7

Toc-2
A3. Basic CPU Operations .......................................................................... A3-1
A3.1 Operation Modes of CPU .............................................................................. A3-1
A3.2 Operation at Power-on/off ............................................................................ A3-2
A3.2.1 Operation at Power-on .................................................................... A3-2
A3.2.2 Operation at Power-off .................................................................... A3-2
A3.3 Operation in Case of Momentary or Complete Power Failure .................... A3-3
A3.3.1 Operation in Case of Momentary Power Failure .............................. A3-3
A3.3.2 Specifying the Momentary Power Failure Detection Mode ............... A3-3
A3.3.3 Operation in Case of Complete Power Failure ................................. A3-4
A3.3.4 Specifying the Range of Devices to Be Latched in Case of
Complete Power Failure .................................................................. A3-4
A3.4 Computation Method .................................................................................... A3-6
A3.5 Method of I/O Processing ............................................................................. A3-8
A3.5.1 Method of I/O Processing ............................................................... A3-8
A3.5.2 Response Delay ............................................................................. A3-9
A3.5.3 I/O Processing in Multi-CPU System ............................................... A3-9
A3.6 Method of Executing Commands from the Programming Tool ................ A3-10
A3.6.1 Tool Service .................................................................................. A3-10
A3.7 Method of Executing Commands through Personal Computer Link ....... A3-11
A3.7.1 Link Service .................................................................................. A3-11
A3.8 Method of CPU-to-CPU Data Communication ........................................... A3-12
A3.8.1 Shared Refreshing ........................................................................ A3-12
A3.8.2 CPU Service ................................................................................. A3-14
A3.9 Method of Link Data Updating .................................................................... A3-15
A3.9.1 Link Refreshing ............................................................................. A3-15
A3.10 Method of Interrupt Processing ................................................................. A3-17
A3.10.1 Interrupt Processing ..................................................................... A3-17
A3.10.2 Interrupt Processing Control ......................................................... A3-18
A4. Devices.................................................................................................. A4-1
A4.1 I/O Relays (X/Y).............................................................................................. A4-1
A4.1.1 Input Relays (X) .............................................................................. A4-1
A4.1.2 Output Relays (Y) ........................................................................... A4-2
A4.1.3 Allocation of I/O Addresses ............................................................. A4-2
A4.1.4 Configuring DI/O Modules ............................................................... A4-3
A4.2 Internal Relays (I), Shared Relays (E) and Extended Shared Relays (E) .... A4-5
A4.2.1 Internal Relays (I) ........................................................................... A4-5
A4.2.2 Shared Relays (E) and Extended Shared Relays (E) ...................... A4-6
A4.2.3 Configuring Internal Relays (I), Shared Relays (E) and Extended Shared
Relays (E) ....................................................................................... A4-9

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A4.3 Link Relays (L) and Link Registers (W) ...................................................... A4-11
A4.3.1 Link Relays (L) .............................................................................. A4-11
A4.3.2 Link Registers (W) ........................................................................ A4-16
A4.3.3 Configuring Link Relays (L) and Registers (W) .............................. A4-21
A4.4 Special Relays (M) ....................................................................................... A4-22
A4.4.1 Block Start Status ......................................................................... A4-22
A4.4.2 Utility Relays ................................................................................. A4-23
A4.4.3 Sequence Operation and Mode Status Relays .............................. A4-24
A4.4.4 Self-diagnosis Status Relays ........................................................ A4-25
A4.4.5 FA Link Module Status Relays ...................................................... A4-26
A4.5 Timers (T) .................................................................................................... A4-27
A4.5.1 1-ms, 10-ms, and 100-ms Timers .................................................. A4-27
A4.5.2 100-ms Continuous Timer ............................................................. A4-28
A4.5.3 Selecting Timers ........................................................................... A4-29
A4.6 Counters (C) ................................................................................................ A4-30
A4.6.1 Selecting Counters ....................................................................... A4-31
A4.7 Data Registers (D), Shared Registers (R),
and Extended Shared Registers (R) ........................................................... A4-32
A4.7.1 Data Registers (D) ........................................................................ A4-32
A4.7.2 Shared Registers (R) and Extended Shared Registers (R) ............ A4-33
A4.7.3 Configuring Data Registers (D), Shared Registers (R)
and Extended Shared Registers (R) ............................................. A4-36
A4.7.4 Setting Initial Data ......................................................................... A4-38
A4.8 Special Registers (Z) ................................................................................... A4-39
A4.8.1 Sequence Operation Status Registers .......................................... A4-39
A4.8.2 Self-diagnosis Status Registers .................................................... A4-40
A4.8.3 Utility Registers ............................................................................. A4-42
A4.8.4 FA Link Module Status Registers .................................................. A4-43
A4.8.5 CPU Module Status Registers ...................................................... A4-44
A4.9 Index Registers (V) ...................................................................................... A4-45
A4.10 File Registers (B) (F3SP25, F3SP35) .......................................................... A4-46
A5. Programs .............................................................................................. A5-1
A5.1 Programming Language ............................................................................... A5-1
A5.1.1 Structured Ladder Language .......................................................... A5-1
A5.1.2 Mnemonic Language ...................................................................... A5-2
A5.2 Program Types and Configuration ............................................................... A5-3
A5.2.1 Blocks and Executable Programs .................................................... A5-3
A5.2.2 Programs Composing an Executable Program ................................ A5-5
A5.3 Program Memory .......................................................................................... A5-9

Toc-4
A6. Functions .............................................................................................. A6-1
A6.1 Function List ................................................................................................. A6-1
A6.2 Operation Setup Function ............................................................................ A6-3
A6.3 Constant Scan ............................................................................................... A6-5
A6.3.1 Setting the Constant Scan Time ...................................................... A6-5
A6.4 Executing All Blocks/Specified Blocks ........................................................ A6-6
A6.4.1 Executing All Blocks ........................................................................ A6-6
A6.4.2 Executing Specified Blocks ............................................................. A6-7
A6.4.3 Operation when Specified Blocks Are Enabled ............................... A6-8
A6.4.4 Operation when Specified Blocks Are Disabled ............................. A6-10
A6.4.5 Operation When Specified Blocks Are Executed ........................... A6-11
A6.5 Debugging Functions ................................................................................. A6-13
A6.5.1 Step Operation ............................................................................. A6-13
A6.5.2 Scan Operation ............................................................................. A6-14
A6.5.3 Partial Operation ........................................................................... A6-15
A6.5.4 Forced SET/RESET .................................................................... A6-15
A6.5.5 Changing Setpoints, Current Values and Data Values ................. A6-16
A6.5.6 Stopping Refreshing ..................................................................... A6-16
A6.6 Protecting Programs ................................................................................... A6-17
A6.6.1 Executable Program Protection ..................................................... A6-17
A6.6.2 Block Protection ............................................................................ A6-18
A6.7 Online Editing ............................................................................................. A6-19
A6.8 Making Programs Resident Using ROM Writer Functions ........................ A6-20
A6.8.1 Making Programs Resident in ROM .............................................. A6-20
A6.8.2 Setting Devices’ Current Values to Be Made Resident in ROM ...... A6-23
A6.8.3 ROM Writer Functions and ROM Writer Mode ............................... A6-24
A6.9 Exclusive Access Right .............................................................................. A6-26
A6.10 Sampling Trace Function ............................................................................ A6-27
A6.11 Personal Computer Link Function ............................................................. A6-31
A6.11.1 System Configuration ................................................................... A6-32
A6.11.2 Differences from Personal Computer Link Module ........................ A6-33
A6.11.3 Specification of Personal Computer Link Function ........................ A6-34
A6.11.4 Setting Up the Personal Computer Link Function .......................... A6-35
A6.11.5 Communication Procedure ........................................................... A6-37
A6.11.6 Commands and Responses ......................................................... A6-39
A6.12 Device Management Function .................................................................... A6-47
A6.13 Macro Instructions ...................................................................................... A6-48
A6.13.1 What Are Macro Instructions? ....................................................... A6-48
A6.13.2 Specification of Macro Instructions ................................................ A6-50
A6.13.3 Devices Dedicated to Macro Instructions ...................................... A6-51

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A6.13.4 Nesting Macro Instructions ........................................................... A6-53
A6.13.5 Handling Macro Instruction Errors ................................................. A6-55
A6.13.6 Protecting Macro Instructions ....................................................... A6-56
A6.13.7 Debugging Operation .................................................................... A6-56
A6.14 User Log Management Function ................................................................ A6-57
A7. I/O Response Time Based on Scan Time ............................................. A7-1
A7.1 Scan Time ...................................................................................................... A7-1
A7.2 Setting Scan Time Monitoring Time ............................................................. A7-2
A7.3 Examples of Calculating the Scan Time ...................................................... A7-3
A7.4 Examples of Calculating the I/O Response Time ........................................ A7-5
A7.5 Instruction Execution Time ........................................................................... A7-6
A8. RAS Features ........................................................................................ A8-1
A8.1 Self-diagnosis ............................................................................................... A8-1
A8.1.1 Setting Operation Mode in Case of Failure
and External Output Mode in Case of Sequence Stop .................... A8-9
A8.2 Recovering Normal Operation after Correcting Moderate/
Minor Failures ............................................................................................. A8-10
PART B for CPU module designed for the FA-M3 Value

system (F3SP05-0P)
B1. Specification and Basic Configuration ................................................ B1-1
B1.1 Overview ........................................................................................................ B1-1
B1.2 Specification ................................................................................................. B1-3
B1.2.1 Performance Data ........................................................................... B1-3
B1.2.2 Device List ...................................................................................... B1-5
B1.2.3 Configuration .................................................................................. B1-6
B1.2.4 Components and Their Functions ................................................... B1-8
B1.2.5 External Dimensions ....................................................................... B1-9
B1.3 Basic Configuration .................................................................................... B1-10
B1.3.1 Units ............................................................................................. B1-10
B1.3.2 Slot Number ................................................................................. B1-11
B1.3.3 I/O Relay Number ......................................................................... B1-11
B2. System Configuration .......................................................................... B2-1
B2.1 Basic System Configuration ........................................................................ B2-1
B2.2 Extended System Configuration .................................................................. B2-2
B2.2.1 Remote I/O System ........................................................................ B2-2
B2.2.2 Personal Computer Link System ..................................................... B2-3
B2.2.3 FA Link System ............................................................................... B2-3
B2.3 Programming Tools ....................................................................................... B2-4
B2.3.1 WideField ....................................................................................... B2-4
B2.3.2 Ladder Diagram Support Program M3 ............................................ B2-6

Toc-6
PART C for CPU module designed for the FA-M3 Value II

system (F3SP08-0P)
C1. Specification and Basic Configuration ................................................ C1-1
C1.1 Overview ........................................................................................................ C1-1
C1.2 Specification ................................................................................................. C1-3
C1.2.1 Performance Data ........................................................................... C1-3
C1.2.2 Device List ...................................................................................... C1-5
C1.2.3 Configuration .................................................................................. C1-6
C1.2.4 Components and Their Functions ................................................... C1-8
C1.2.5 External Dimensions ....................................................................... C1-9
C1.3 Basic Configuration .................................................................................... C1-10
C1.3.1 Units ............................................................................................. C1-10
C1.3.2 Slot Number ................................................................................. C1-11
C1.3.3 I/O Relay Number ......................................................................... C1-11
C2. System Configuration .......................................................................... C2-1
C2.1 Basic System Configuration ........................................................................ C2-1
C2.2 Extended System Configuration .................................................................. C2-2
C2.2.1 Remote I/O System ........................................................................ C2-2
C2.2.2 Personal Computer Link System ..................................................... C2-3
C2.2.3 FA Link System ............................................................................... C2-3
C2.3 Programming Tools ....................................................................................... C2-4
C2.3.1 WideField ....................................................................................... C2-4
Appendix 1. Special Relays (M) ..............................................................App.1-1
Appendix 1.1 Block Start Status ......................................................................... App.1-1
Appendix 1.2 Utility Relays .................................................................................. App.1-2
Appendix 1.3 Sequence Operation and Mode Status Relays ............................ App.1-4
Appendix 1.4 Self-diagnosis Status Relays ........................................................ App.1-5
Appendix 1.5 FA Link Module Status Relays ...................................................... App.1-7
Appendix 2. Special Registers (Z) ..........................................................App.2-1
Appendix 2.1 Sequence Operation Status Registers ......................................... App.2-1
Appendix 2.2 Self-diagnosis Status Registers ................................................... App.2-2
Appendix 2.3 Utility Registers ............................................................................. App.2-4
Appendix 2.4 FA Link Module Status Registers ................................................. App.2-5
Appendix 2.5 CPU Module Status Registers ...................................................... App.2-6
Appendix 3. Forms for System Design ..................................................App.3-1
Index ........................................................................................................... Index-1
Revision Information ............................................................................................ i

Toc-A1

PART A for F3SP21, F3SP25 and F3SP35
CONTENTS
A1. Specification and Basic Configuration ................................................ A1-1
A1.1 Overview ........................................................................................................ A1-1
A1.1.1 CPU Modules ................................................................................. A1-1
A1.2 Specification ................................................................................................. A1-3
A1.2.1 Table of Performance Data .............................................................. A1-3
A1.2.2 Device List ...................................................................................... A1-5
A1.2.3 Configuration .................................................................................. A1-7
A1.2.4 Components and Their Functions ................................................. A1-12
A1.2.5 External Dimensions ..................................................................... A1-13
A1.3 Basic configuration .................................................................................... A1-14
A1.3.1 Unit ............................................................................................... A1-14
A1.3.2 Slot Number ................................................................................. A1-15
A1.3.3 I/O Relay Number ......................................................................... A1-17
A2. System Configuration .......................................................................... A2-1
A2.1 Basic System Configuration ........................................................................ A2-1
A2.2 Multi-CPU System Configuration ................................................................. A2-1
A2.2.1 Multi-CPU System Configuration .................................................... A2-1
A2.2.2 Handling I/O Modules in Multi-CPU System .................................... A2-2
A2.3 Extended System Configuration .................................................................. A2-3
A2.3.1 Remote I/O System ........................................................................ A2-3
A2.3.2 Personal Computer Link System ..................................................... A2-3
A2.3.3 FA Link System ............................................................................... A2-4
A2.4 Programming Tools ....................................................................................... A2-5
A2.4.1 WideField ....................................................................................... A2-5
A2.4.2 Ladder Diagram Support Program M3 ............................................ A2-7
A3. Basic CPU Operations .......................................................................... A3-1
A3.1 Operation Modes of CPU .............................................................................. A3-1
A3.2 Operation at Power-on/off ............................................................................ A3-2
A3.2.1 Operation at Power-on .................................................................... A3-2
A3.2.2 Operation at Power-off .................................................................... A3-2

Toc-A2
A3.3 Operation in Case of Momentary or Complete Power Failure .................... A3-3
A3.3.1 Operation in Case of Momentary Power Failure .............................. A3-3
A3.3.2 Specifying the Momentary Power Failure Detection Mode ............... A3-3
A3.3.3 Operation in Case of Complete Power Failure ................................. A3-4
Complete Power Failure .................................................................. A3-4
A3.4 Computation Method .................................................................................... A3-6
A3.5 Method of I/O Processing ............................................................................. A3-8
A3.5.1 Method of I/O Processing ............................................................... A3-8
A3.5.2 Response Delay ............................................................................. A3-9
A3.5.3 I/O Processing in Multi-CPU System ............................................... A3-9
A3.6 Method of Executing Commands from the Programming Tool ................ A3-10
A3.6.1 Tool Service .................................................................................. A3-10
A3.7 Method of Executing Commands through Personal Computer Link ....... A3-11
A3.7.1 Link Service .................................................................................. A3-11
A3.8 Method of CPU-to-CPU Data Communication ........................................... A3-12
A3.8.1 Shared Refreshing ........................................................................ A3-12
A3.8.2 CPU Service ................................................................................. A3-14
A3.9 Method of Link Data Updating .................................................................... A3-15
A3.9.1 Link Refreshing ............................................................................. A3-15
A3.10 Method of Interrupt Processing ................................................................. A3-17
A3.10.1 Interrupt Processing ..................................................................... A3-17
A3.10.2 Interrupt Processing Control ......................................................... A3-18
A4. Devices.................................................................................................. A4-1
A4.1 I/O Relays (X/Y).............................................................................................. A4-1
A4.1.1 Input Relays (X) .............................................................................. A4-1
A4.1.2 Output Relays (Y) ........................................................................... A4-2
A4.1.3 Allocation of I/O Addresses ............................................................. A4-2
A4.1.4 Configuring DI/O Modules .............................................................. A4-3
A4.2 Internal Relays (I), Shared Relays (E) and Extended Shared Relays (E) .... A4-5
A4.2.1 Internal Relays (I) ........................................................................... A4-5
A4.2.2 Shared Relays (E) and Extended Shared Relays (E) ...................... A4-6
A4.2.3 Configuring Internal Relays (I), Shared Relays (E) and Extended Shared
Relays (E) ....................................................................................... A4-9
A4.3 Link Relays (L) and Link Registers (W) ...................................................... A4-11
A4.3.1 Link Relays (L) .............................................................................. A4-11
A4.3.2 Link Registers (W) ........................................................................ A4-16
A4.3.3 Configuring Link Relays (L) and Registers (W) .............................. A4-21

Toc-A3
A4.4 Special Relays (M) ....................................................................................... A4-22
A4.4.1 Block Start Status ......................................................................... A4-22
A4.4.2 Utility Relays ................................................................................. A4-23
A4.4.3 Sequence Operation and Mode Status Relays .............................. A4-24
A4.4.4 Self-diagnosis Status Relays ........................................................ A4-25
A4.4.5 FA Link Module Status Relays ...................................................... A4-26
A4.5 Timers (T) .................................................................................................... A4-27
A4.5.1 1-ms, 10-ms, and 100-ms Timers .................................................. A4-27
A4.5.2 100-ms Continuous Timer ............................................................. A4-28
A4.5.3 Selecting Timers ........................................................................... A4-29
A4.6 Counters (C) ................................................................................................ A4-30
A4.6.1 Selecting Counters ....................................................................... A4-31
A4.7 Data Registers (D), Shared Registers (R),
and Extended Shared Registers (R) ........................................................... A4-32
A4.7.1 Data Registers (D) ........................................................................ A4-32
A4.7.2 Shared Registers (R) and Extended Shared Registers (R) ............ A4-33
A4.7.3 Configuring Data Registers (D), Shared Registers (R)
and Extended Shared Registers (R) ............................................. A4-36
A4.7.4 Setting Initial Data ......................................................................... A4-38
A4.8 Special Registers (Z) ................................................................................... A4-39
A4.8.1 Sequence Operation Status Registers .......................................... A4-39
A4.8.2 Self-diagnosis Status Registers .................................................... A4-40
A4.8.3 Utility Registers ............................................................................. A4-42
A4.8.4 FA Link Module Status Registers .................................................. A4-43
A4.8.5 CPU Module Status Registers ...................................................... A4-44
A4.9 Index Registers (V) ...................................................................................... A4-45
A4.10 File Registers (B) (F3SP25, F3SP35) .......................................................... A4-46
A5. Programs .............................................................................................. A5-1
A5.1 Programming Language ............................................................................... A5-1
A5.1.1 Structured Ladder Language .......................................................... A5-1
A5.1.2 Mnemonic Language ...................................................................... A5-2
A5.2 Program Types and Configuration ............................................................... A5-3
A5.2.1 Blocks and Executable Programs .................................................... A5-3
A5.2.2 Programs Composing an Executable Program ................................ A5-5
A5.3 Program Memory .......................................................................................... A5-9
A6. Functions .............................................................................................. A6-1
A6.1 Function List ................................................................................................. A6-1
A6.2 Operation Setup Function ............................................................................ A6-3
A6.3 Constant Scan ............................................................................................... A6-5
A6.3.1 Setting the Constant Scan Time ...................................................... A6-5

Toc-A4
A6.4 Executing All Blocks/Specified Blocks ........................................................ A6-6
A6.4.1 Executing All Blocks ........................................................................ A6-6
A6.4.2 Executing Specified Blocks ............................................................. A6-7
A6.4.3 Operation when Specified Blocks Are Enabled ............................... A6-8
A6.4.4 Operation when Specified Blocks Are Disabled ............................. A6-10
A6.4.5 Operation When Specified Blocks Are Executed ........................... A6-11
A6.5 Debugging Functions ................................................................................. A6-13
A6.5.1 Step Operation ............................................................................. A6-13
A6.5.2 Scan Operation ............................................................................. A6-14
A6.5.3 Partial Operation ........................................................................... A6-15
A6.5.4 Forced SET/RESET .................................................................... A6-15
A6.5.5 Changing Setpoints, Current Values and Data Values ................. A6-16
A6.5.6 Stopping Refreshing ..................................................................... A6-16
A6.6 Protecting Programs ................................................................................... A6-17
A6.6.1 Executable Program Protection ..................................................... A6-17
A6.6.2 Block Protection ............................................................................ A6-18
A6.7 Online Editing ............................................................................................. A6-19
A6.8 Making Programs Resident Using ROM Writer Functions ........................ A6-20
A6.8.1 Making Programs Resident in ROM .............................................. A6-20
A6.8.2 Setting Devices’ Current Values to Be Made Resident in ROM ...... A6-23
A6.8.3 ROM Writer Functions and ROM Writer Mode ............................... A6-24
A6.9 Exclusive Access Right .............................................................................. A6-26
A6.10 Sampling Trace Function ............................................................................ A6-27
A6.11 Personal Computer Link Function ............................................................. A6-31
A6.11.1 System Configuration ................................................................... A6-32
A6.11.2 Differences from Personal Computer Link Module ........................ A6-33
A6.11.3 Specification of Personal Computer Link Function ........................ A6-34
A6.11.4 Setting Up the Personal Computer Link Function .......................... A6-35
A6.11.5 Communication Procedure ........................................................... A6-37
A6.11.6 Commands and Responses ......................................................... A6-39
A6.12 Device Management Function .................................................................... A6-47
A6.13 Macro Instructions ...................................................................................... A6-48
A6.13.1 What Are Macro Instructions? ....................................................... A6-48
A6.13.2 Specification of Macro Instructions ................................................ A6-50
A6.13.3 Devices Dedicated to Macro Instructions ...................................... A6-51
A6.13.4 Nesting Macro Instructions ........................................................... A6-53
A6.13.5 Handling Macro Instruction Errors ................................................. A6-55
A6.13.6 Protecting Macro Instructions ....................................................... A6-56
A6.13.7 Debugging Operation .................................................................... A6-56
A6.14 User Log Management Function ................................................................ A6-57

Toc-A5
A7. I/O Response Time Based on Scan Time ............................................. A7-1
A7.1 Scan Time ...................................................................................................... A7-1
A7.2 Setting Scan Time Monitoring Time ............................................................. A7-2
A7.3 Examples of Calculating the Scan Time ...................................................... A7-3
A7.4 Examples of Calculating the I/O Response Time ........................................ A7-5
A7.5 Instruction Execution Time ........................................................................... A7-6
A8. RAS Features ........................................................................................ A8-1
A8.1 Self-diagnosis ............................................................................................... A8-1
A8.1.1 Setting Operation Mode in Case of Failure
and External Output Mode in Case of Sequence Stop .................... A8-9
A8.2 Recovering Normal Operation after Correcting Moderate/
Minor Failures ............................................................................................. A8-10

Blank Page
A1-1
A1. Specification and Basic Configuration

This chapter explains the CPU module specifications and the basic configuration of
the FA-M3 Range-free Multi-controller.
A1.1 Overview F3SP21

F3SP25
F3SP35
A1.1.1 CPU Modules
■ Overview
Models F3SP21-0N, F3SP25-2N and F3SP35-5N are CPU modules with built-in memory
for use with the FA-M3.
In addition to high-speed operation and large memory capacity, these modules have many
more features that help increase your development and maintenance efficiency.
■ Features
• Has a compact body, allowing for space saving within the cabinet.
• Support for high-speed processes and responses of the module's maximum instruc-
tion processing speed.
• Operates large-capacity programs and has large device sizes, enabling it to cope with
advanced, complex control applications.
• Uses index modification and structured ladder language for easy program design and
maintenance.
• Allows the device size and operating method to be flexibly configured according to
your application needs.
• Provides various functions, e.g., a forced SET/RESET function and scan operation
independent of program computation results, for easy program debugging and main-
tenance.
• Has a carefully designed self-diagnosis function, in addition to a highly reliable design.
• Provides macro instruction functions to allow you to create and register new instruc-
tions (F3SP25 and F3SP35 only).
• Has a sampling trace function capable of acquiring and displaying the states of a
maximum of 1024 scans' worth of devices (F3SP25 and F3SP35 only).
• Can connect to a host computer or a monitor without the need for a personal computer
link module, as the programming tool connection port supports a personal computer
link function.
• Has a logging function capable of recording errors encountered in a program, as well
as messages created and registered in advance.
• Allows you to mount F3SP21, F3SP25 or F3SP35 modules in slots 2 to 4 of the main
unit, for use as add-on CPU modules for sequence processes added to the main CPU
module (F3SP21, F3SP25 and F3SP35).
• Allows you to attach a ROM pack so that you can perform ROM-based operation and
store programs.
• Has a program protection function to ensure security.

A1-2
■ Major Functions
• Configuration (setup of parameters, including device size, range of devices to be
latched in case of power failure, and external output to be retained in case of se-
quence stop)
• Constant scan (at an interval of 1 to 190 ms, in 0.1 ms increments)
• Sampling trace (F3SP25 and F3SP35 only)
• Debugging (forced SET/RESET instructions, online editing, scan operation, etc.)
• Error logging, user logging
• Clock (year, month, day, hour, minute, second, and day of the week)
• Support for programming tool connection port with the personal computer link function
• Program protection
• Program/data storage in ROM pack
See Section A1.2, "Specification," for more information.

A1-3
A1.2 Specification
A1.2.1 Table of Performance Data
Table A1.1 Performance Data
Specifications
Item
F3SP21 F3SP25 F3SP35
Control method Repetitive computation based on stored programs
I/O computation method Refreshing by direct I/O instructions
Programming language Structured ladder language and mnemonic language
Number of I/O points 2048 max. 4096 max. 8192 max.,
including remote I/O points
Number of internal relays (I) 4096 8192 16384
Number of shared relays (E) 2048
Number of extended shared relays (E) 0 2048
Number of link relays (L) 2048 8192 (*)
Number of special relays (M) 2048 9984
Number of timers (T) 256 1024 2048
Number of counters (C) 256 1024
Number of data registers (D) 5120 8192
Number of shared registers (R) 1024
Number of extended shared registers (R) 0 3072
Number of file registers (B) 0 32768
Number of link registers (W) 2048 8192(*)
Number of special registers (Z) 256 512
Number of labels 64 256
Number of interruption processing routines 4
16-bit instruction: -32768 to 32767

Decimal constant
Hexadecimal constant 16-bit instruction: $0 to $FFFF (hexadecimal number)

Constants 32-bit instruction: $0 to $FFFFFFFF (hexadecimal number)
Character-string constant 16-bit instruction: "AB", "YOKO", etc.

32-bit instruction: "ABCD", "YOKOGAWA", etc.
32-bit instruction: "1.23", "-3.21", etc.

Floating-point constant Approximately -3.4 3 1038 to 3.4 3 1038
10 K steps max., 20 K steps max., 100 K steps max.,

Program size
ROM-able ROM-able ROM-able
Number of program blocks 32 max. 128 max. 1024 max.
Number of Basic instruction 25

instructions Application instruction 227 307
Instruction Basic instruction 0.18 to 0.36 µs/instruction 0.12 to 0.24 µs/instruction 0.09 to 0.18 µs/instruction
execution time Application instruction 0.36µs min./instruction 0.24 µs min./instruction 0.18 µs min./instruction
Number of HRD/HWR instructions 64, respectively
Sampling trace function Not available Available
User logging function Available
Support for personal computer link function

Available
by programming tool connection port
* : Application instructions, which contain any of the link relays L20001 to L21024 and L70001 to L71024 or any of the link registers
W20001 to W21024 and W70001 to W71024, are excluded from high-speed processing.
TA010201.EPS

A1-4
Table A1.1 Performance Data (Continued)
Specifications
Item
Number of personal computer link modules 2 max. 6 max.
Macro instruction function Not available Available
Scan time monitoring time Variable from 10 to 200ms
Automatic
Startup at power-on or recovery from power failure (Auto-logging of power-on time, power-off time and momentary power failure time)
Debugging operation Step operation, scan operation and partial operation

Constant scan Interval of 1 to 190 ms, in 0.1ms increments
Self-diagnosis Detection of memory failure, CPU failure and I/O module failure,syntax checking,etc.
Link function FA link,personal computer link and remote I/O link (fiber-optic FA-bus and µ-bus)
• Online editing
• Forced SET/RESET instructions
• Clock (year, month, day, hour, minute, second, and day of the week
• Configuration (setup of parameters, including device size, range of devices to
Other functions be latched in case of power failure and external outputs to be latched in case
of sequence stop)
• Stop of refreshing
TA010202.EPS
See Also
"Section A1.7" "High-speed Processing of Application Instructions," in Sequence CPU Instruction Manual
- Instructions (IM34M6P12-03E), for more information on the high-speed processing of application
instructions.

A1-5
A1.2.2 Device List

Table A1.2 Device List
Device Code Remaks
Range Quantity Range Quantity Range Quantity
X00201 to X00201 to X00201 to
Input relay X X71664 X71664 X71664
(discontinuous) (discontinuous) (discontinuous) The range to be used
2048 4096 8192 differs depending on the
Y00201 to Y00201 to Y00201 to module type.
Output relay Y Y71664 Y71664 Y71664
(discontinuous) (discontinuous) (discontinuous)
Correlative with shared
I0001 to I0001 to I00001 to and extended shared (E)
Internal relay I I4096 4096 I8192 8192 I16384 16384 relays in terms of
configuration limitations.
Correlative with internal
Shared (I) relays in terms of
E0001 to 2048 E0001 to 2048 E0001 to 2048 configuration limitations
relay E2048 E2048 E2048 (Note).
Non- The quantity of these
latching E devices is zero by
Ext- type default. Be sure to
ended configure the devices
0 E2049 to 2048 E2049 to 2048 when using the CPU
shared –
E4096 E4096 module in multi-CPU
relay configuration.
Link Non- L0001 to L00001 to L0001 to Used for FA link

relay latching L L11024 2048 L71024 8192 L71024 8192 communication.
type (discontinuous) (discontinuous) (discontinuous)
M001 to M0001 to M0001 to
Special relay M M2048
2048 M9984
9984 M9984
9984
100-µs T0001 to T0001 to T0001 to Configurable for up to 16

timer timers.
T0016 T0016 T0016
1-ms
timer
512 2048 3072
Timer 10-ms
timer T in in in Correlative with counters
total total total (C) in terms of
T0001 to T0001 to T0001 to configuration limitations
100-ms T512 T2048 T3072 (Note).
timer
Con- 100-ms
tinuous timer
timer
C0001 to C0001 to C0001 to Correlative with timers (T)
Latching in terms of configuration
Counter type C C512 C2048 C3072 limitations (Note).
Correlative with shared
Data Latching D001 to D0001 to D00001 to and extended shared (R)
register type D D5120
5120 D8192
8192 D8192
8192 registers in terms of
configuration limitations
File Latching 0 B00001 to 32768 B00001 to 32768
register B –
type B32768 B32768
Link Non- W0001 to W00001 to W00001 to Used for FA link

register latching W W11024 2048 W71024 2048 W71024 8192 communication.
type (discontinuous) (discontinuous) (discontinuous)
Z0001 to 512 Z001 to 512 Z001 to 512
Special register Z
Z512 Z512 Z512
Index register V V01 to V32 32 V01 to V32 32 V01 min 32

Correlative with data (D)
Shared R0001 to R0001 to R0001 to registers in terms of
register 1024 1024 1024 configuration limitations
R1024 R1024 R1024
Non- (Note).
R The quantity of these
Ex- latching devices is zero by default.
tended type R1025 to R1025 to Be sure to configure the
– 0 0 3072
shared R4096 R4096 devices when using the
register CPU module in multi-CPU
configuration.
Note: Device Size Defaults and Configuration limitations TA010205.EPS

A1-6

Device Code Device Configuration Device Configuration Device Configuration
Size Size Size
Default limitations Default limitations Default limitations
Sum of internal relays Sum of internal relays Sum of internal relays

Internal relay I 4096 and shared/extended 8192 and shared/extended 16384 and shared/extended
shared relays: 4096 shared relays: 8192 shared relays: 16834
points max. points max. points max.
Maximum number of Maximum number of Maximum number of
shared/extended shared/extended shared/extended
E shared relays: 2048 shared relays: 2048 shared relays: 2048
Shared relay 0 points 0 points 0 points
Sum of timers and Sum of timers and

Timer T 256 counters: 512 points 1024 2048 counters: 3072 points
Sum of timers and
max. counters: 2048 points max.
Initial quantity of 1-ms max. Initial quantity of 1-ms
Counter C 256 timers: 0 1024 1024 timers: zero
5120 Sum of data registers 8192 Sum of data registers 8192 Sum of data registers
Data register D and shared/extended and shared/extended and shared/extended
shared registers: 5120 shared registers: 8192 shared registers: 8192
points max. points max. points max.
Maximum number of Maximum number of Maximum number of
shared/extended shared/extended shared/extended
Shared register R 0 shared registers: 1024 0 shared registers: 1024 0 shared registers: 1024
points points points
Extended 2048 points max. 2048 points max.

E – – 0 0
shared relay
Extended
R – – 0 3072 points max. 0 3072 points max.
shared register
TA010206.EPS

A1-7
A1.2.3 Configuration
■ Configuration Function
The sequence CPU contains the predefined defaults of device sizes and operation
methods.You can use these defaults to run programs. In some applications, however, they
may not suit your specific purpose of use. In such a case, flexibility allows for defaults to be
changed to meet your needs. Changing the defaults is called “configuration” and can be
performed through a programming tool*.
*FA-M3 Programming Tool WideField or Ladder Diagram Support Program M3
■ Tables of Configuration Ranges

Table A1.3 Configuration Ranges (1 of 4)
F3SP21 F3SP25, F3SP35
Item
Default Configuration Range Default Configuration Range
2048 points max. in 32 2048 points max. in 32
Shared relay (E) 0 points increments for 0 points increments for
all CPUs combined all CPUs combined
Configuration 2048 points max. in 32 2048 points max. in 32

Extended shared points increments for points increments for
of the range 0 0
relay (E) all CPUs combined all CPUs combined
of E and R
shared relays 1024 points max. in 2 1024 points max. in 2
and registers Shared register points increments for points increments for
0 0
to be used (R) all CPUs combined all CPUs combined
Extended shared points increments for points increments for
0 0
register (R) all CPUs combined all CPUs combined

1024 points points increments (Note) 1024 points points increments (Note)
Configuration Link relays for each link for all links combined for each link for all links combined
of the range
Device
of L and W
size
link relays
and registers 2048 points max. in 1 8192 points max. in 1
to be used 1024 points point increments (Note) 12024 points point increments (Note)
Link register for each link for all links combined for each link for all links combined
1-ms timer 0 2048 points in 1 point 0 3072 points in 1 point

increments for timers increments for timers
10-ms timer 512 and counters 1024 and counters
100-ms timer 448 combined; 896 combined;
Configuration 16 points max. for 1- 16 points max. for 1-
of timers/ 100-ms ms timers;Timer ms timers;Timer
counters 64 numbers are 128 numbers are
continuous timer
2048 points in 1 point 3072 points in 1 point

Counter 1024 increments for timers 1024 increments for timers
and counters combined and counters combined
TA010209.EPS

A1-8
F3SP21 F3SP25, F3SP35
Item
I0001 to I0001 to
Internal relay (I) Configurable in 32 Configurable in 32
I1024 I1024
points basis; points basis;
Shared and
Non-latching continuous from the Non-latching continuous from the
extended shared starting number starting number
type type
relays (E)
Link relay (L) Non-latching Configurable in 16 Non-latching Configurable in 16

type points basis (Note) type points basis (Note)
Non-latching Non-latching
type type
Range of Timer (T) (except for Configurable in 1 point (except for Configurable in
Extended devices to be continuous basis; continuous 1 point basis;
device latched in timers) continuous from the timers) continuous from the
configuration case of All latched starting number All latched starting number
power failure Counter (C) (C0001 to (C0001 to
C1024) C1024)
All latched All latched
Data register
(D00001 toConfigurable in 2 (D00001 to Configurable in
(D)
D16384) points basis; D32768) 2 points basis;
Shared and continuous from the continuous from the
Non-latching starting number (Note) Non-latching starting number (Note)
extended shared
type type
registers (R)
Link register Non-latching Configurable in 16 Non-latching Configurable in 16

(W) type points basis (Note) type points basis (Note)
TA010210.EPS
Note: The configuration range of each of the shared and extended shared relays and shared and extended
shared registers to be latched in case of power failure is assigned numbers continuous from the starting
number. However, if the number of shared relays is smaller than 2048, the last of them is followed by the
first extended shared relay numbered E2049. Likewise, if the number of shared registers is smaller than
1024, the last of them is followed by the first extended shared register numbered R1025.
Example)
In a case where there are 1024 shared relays and 2048 extended shared relays:
f you define the starting number as 513 and the number of units as 1024 for the range of devices to be
latched in case of power failure, then the devices included in the latching are:
E513 to E1024 shared relays; and
E2049 to E2560 extended shared relays.
Note: The configuration range of each link relay and register to be latched in case of power failure is assigned
numbers continuous from the starting number.
However, the following exceptions apply.
The number following L/W01024 is L/W10001.
(The rules noted above are true when the number of link relays or registers to be used is defined as 1024.
If the number is 2048, the number following L/W02048 is L/W10001.)
Example)
When there are 1024 link relays each for link 1, link 2 and link 3:
If you define the starting number as 10513 and the number of units as 1024 for the range of devices to be
latched in case of power failure, then the devices included in the latching are:
L10513 to L11024 link relays for link 1; and
L20001 to L20512 link relays for link 2.

A1-9
Item Configuration Configuration Configuration
Default Default Default
Range Range Range
Configurable for Configurable for Configurable for
up to 1024 points up to 1024 points up to 1024 points
Initial data setting None continuously from None continuously from None continuously from
Data register (D) the starting the starting the starting
number; initial number; initial number; initial
data configurable data configurable data configurable
Configurable from Configurable from Configurable from

Scan time monitoring time 200ms 10 to 200 ms in 200ms 10 to 200 ms in 200ms 10 to 200 ms in
10 ms increments 10 ms increments 10 ms increments
Configurable from Configurable from Configurable from

Constant scan time Unused 1.0 to 190.0 ms in Unused. 1.0 to 190.0 ms in Unused. 1.0 to 190.0 ms in
0.1 ms increments 0.1 ms increments 0.1 ms increments
Operation I/O module

mode Stop Stop Stop
failure
in case
of failure I/O collation
failure Stop Stop Stop
Instruction
processing Stop Stop Stop
failure Selectable from Selectable from Selectable from
Stop and Stop and Stop and
Scan timeout Stop Continue options. Stop Continue options. Stop Continue options.
Operation
control
Subroutine Stop Stop Stop
error
Interrupt error Stop Stop Stop

Subunit Con- Con- Con-
transmission tinuation tinuation tinuation
line failure
All blocks All or selected All blocks All or selected All blocks All or selected
Program execution mode are blocks are are blocks are are blocks are
executed. executed. executed. executed. executed. executed.
Effective only if
Momentary F3PU10-0N,
power F3PU20-0N or Standard or Standard or Standard or
failure F3PU26-0N Standard immediate Standard immediate Standard immediate
detection power supply mode detection mode mode detection mode mode detection mode
mode module is
used.
Reset/hold; Reset/hold; Reset/hold;
Output mode in case Reset configurable on a Reset configurable on a configurable on a
of sequence stop Reset
module basis module basis module basis
DIO BIN/BCD; BIN/BCD; BIN/BCD;
Data code BIN configurable in 16 BIN configurable in 16 BIN configurable in 16
points type
I/O module point increments point increments point increments
Input sampling 16 ms/1 ms; 16 ms/1 ms; 16 ms/1 ms;
interval 16ms configurable on a 16ms configurable on a 16ms configurable on a
module basis module basis module basis
Devices'
current Data register Configurable for Configurable for Configurable for
values to (D) up to 5120 points up to 5120 points up to 5120 points
ROM be made None continuously from None continuously from None continuously from
File register
resident in (B) the starting the starting the starting
ROM number number number
TA010211.EPS

A1-10
CAUTION
Use the R1.08 or later version of Ladder Diagram Support Program M3 to edit the configu-
ration item "Subunit Transmission Line Failure." This item is effective for the Rev.8 or later
version of the F3SP21, F3SP25 and F3SP35.
SEE ALSO
Instruction manual (IM34M6H45-01E), Fiber-optic FA-bus Module, Fiber-optic FA-bus Type 2 Module, for
more information on the subunit transmission line failure.

Range Range Range
Mode 0: Mode 0: Mode 0:

9600 bps, 9600 bps, 9600 bps,
even parity even parity even parity
CPU Mode 1: Mode 1: Mode 1:
com- Mode 0: Mode 0: Mode 0:
munication 9600 bps, 9600 bps, 9600 bps, 9600 bps, 9600 bps, 9600 bps,
Mode even parity non parity even parity non parity even parity non parity
port
Mode 2: Mode 2: Mode 2:
19200 bps, 19200 bps, 19200 bps,
even parity even parity even parity
Used/unused Unused Unused/Used Unused Unused/Used Unused Unused/Used

Com-
munication
Check sum No Yes/No No Yes/No No Yes/No
Personal
computer Terminating
link character No Yes/No No Yes/No No Yes/No
function selection
Protection No No No
function Yes/No Yes/No Yes/No
Related/Not related Related/Not related Related/Not related

Relationship between FA link Each FA link number Each FA link number Each FA link number
numbers and slot numbers No corresponds to a No corresponds to a No corresponds to a
slot number from slot number from slot number from
1 to 16 1 to 16 1 to 16
TA010212.EPS
CAUTION
Use the FA link H module and/or fiber-optic FA link H module only in combination with the
R1.08 or later version of Ladder Diagram Support Program M3 and with the Rev.8 or later

A1-11
CAUTION
For each of the F3LP02 FA link H modules and F3LP12 fiber-optic FA link H modules, you
can use a maximum of 2048 points of link relays and link registers. The configuration
limitations described below apply, however, if either of the following cases is true.
1. A case where a single CPU uses a combination of FA link H module and fiber-optic FA
link H modules, each configured with 2048 points of link relays/registers.
2. A case where a single CPU uses a combination of FA link H or fiber-optic FA link H
modules configured with 1024 points of link relays/registers set for high-speed
processing and FA link H or fiber-optic FA link H modules configured with 2048 points
of link relays/registers set for normal-speed processing.
Configuration limitations:
For FA link 1, be sure to set the number of both link relays and link registers to 2048. If you
set the number to 1024, the CPU does not operate correctly. If the number of both link
relays and link registers is set to 0 for FA link 1, be sure to set the number to 2048 for FA
link 2.
Examples of Unallowable Configuration:
Link 1: [1024]; Link 2: [2048]; Link 3: . . .
Link 1: [ 0]; Link 2: [1024]; Link 3: [2048]; . . .
Link 1: [1024]; Link 2: [ 0]; Link 3: [2048]; . . .
Examples of Allowable Configuration:
Link 1: [2048]; Link 2: . . .
Link 1: [1024]; Link 2: [1024]; Link 3: . . .
Link 1: [ 0]; Link 2: [1024]; Link 3: [1024]; . . .
Link 1: [1024]; Link 2: [ 0]; Link 3: [1024]; . . .
Link 1: [ 0]; Link 2: [2048]; Link 3: . . .

A1-12
A1.2.4 Components and Their Functions

This section describes the LED indicators, their states, and the programming tool connector
on the front side of the sequence CPU module. These features are common to the
F3SP21, F3SP25 and F3SP35 CPU modules.
Table A1.7 summarizes combinations of the LED indicators as classified by the severity of
failure.
CPU module operation status LED indicators

SP 0-0N CPU RDY (= READY, green) --------------------On = Normal
Off = Major failure
RUN (= RUN, green) ---------------------- On = Program in progress
Off = Program at a stop
ALM (= ALARM, yellow) ------------------ On = Minor failure
Off = Normal
ERR (= ERROR, red) --------------------- On = Moderate failure
Off = Normal
Major failure --------------- The CPU module is inoperable due

to a hardware failure.
Moderate failure ---------- The CPU module cannot run or
continue to run a program.
Minor failure --------------- The CPU module still can run or
continue to run a program though
it has detected a failure.
Programming tool connector

------------------- Connected to a personal computer.
A personal computer or a monitor
can be connected to this connector
when the personal computer link
function is in use.
F010201E.EPS
Table A1.7 LED Indicator Combinations Based on the Severity of Failure
Status Major Moderate Minor

Normal
LED Indicator Failure Failure Failure
RDY On Off On On
RUN On Off Off On
ALM Off On or Off On or Off On
ERR Off On On Off
TA010213.EPS
Table A1.8 Weight

Model Weight
F3SP21,F3SP25,F3SP35 130g
TA010214.EPS

A1-13
A1.2.5 External Dimensions

Unit: mm
83.2 28.9
2
100
F010202.EPS

A1-14
A1.3 Basic Configuration

A1.3.1 Unit
A unit is a system with its minimum configuration consisting of the following modules.
Install these modules on the base module to compose the unit.
Table A1.9 Unit Components (Modules)
Name Description
Base module Five types are available depending on the number of modules to be mounted.
Power supply module One power supply module must always be mounted on the base module.
At least one CPU module is required. Several types are available depending
CPU module on the functionality.
Various types are available depending on the type of I/O and the number of
I/O module I/O points.
Special module Various types are available, including analog I/O and communication modules.
TA010301.EPS
The location where you install a module is called a slot.
■ Main Unit
Install the power supply module in the leftmost slot of the base module and the CPU mod-
ule in the slot on the immediate right of the power supply module. Then, install required I/O
and special modules in the remaining slots. A system with this configuration is called a
main unit.
CPU module
Power
supply
module
I/O and special modules

F010301.EPS
Figure A1.1 Main Unit
■ Subunit
A subunit is an I/O expansion unit. It is connected to the main unit through a fiber-optic FA-
bus or fiber-optic FA-bus type 2. A maximum of seven subunits can be connected to the
main unit and are identified by their unit numbers. With fiber-optic FA-bus type 2, you can
separate any single subunit into a maximum of eight stations. For more information on the
method of separation, see the instruction manual (IM34M6H45-01E), Fiber-optic FA-bus
Module, Fiber-optic FA-bus Type 2 Module.

A1-15
A1.3.2 Slot Number

A slot number indicates the position of a slot where a module is installed. The slot number
is defined as a three-digit integer, as shown below.
Slot number
Slot positions 01 to 16 are assigned to the slot on the immediate right of

the power supply module through to the rightmost slot of a base module.
Unit number
Main unit = 0
Subunit = 1 to 7
F010302.EPS
Figure A1.2 Slot Numbers (1 of 2)

A1-16
Fiber-optic FA-bus type 2 module
(can be installed in any position)
FA-M3 main unit
001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 Slot numbers 001 to 016
Power
supply
module
Add-on CPUs (three CPUs max.)
CPU module
Subunit 1
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 Slot numbers 101 to 116
Power
supply
module
Subunit 2
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 Slot numbers 201 to 216
Power
supply
module
Subunit 3
301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 Slot numbers 301 to 316
Power
supply
module
Subunit 4
401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 Slot numbers 401 to 416
Power
supply
module
Subunit 5
501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 Slot numbers 501 to 516
Power
supply
module
Subunit 6
601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 Slot numbers 601 to 616
Power
supply
module
Subunit 7
701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 Slot numbers 701 to 716
Power
supply
module
F010303.EPS
Figure A1.3 Slot Numbers (2 of 2)
Install fiber-optic FA-bus type 2 modules in both the main unit and a subunit and connect
these modules with a fiber-optic cable. You can attach a maximum of seven subunits to the
main unit. Subunit numbers are determined by setting the rotary switch on the front panel
of each fiber-optic FA-bus type 2 module.

A1-17
A1.3.3 I/O Relay Number

Each input relay (X) and output relay (Y) numbers are defined as a slot number followed by
a terminal number. The terminal number is a number corresponding to each terminal of an
I/O module.
Example) The output relay number for terminal 6 of an F3YC08-0N module installed
in slot 005 is defined as follows.
Y005 06
Terminal number
Slot number
001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 Slot numbers
Power
supply
module
Y 08- OUT
Output relay number

Y00506
F3YC08-0N
F010304.EPS
Figure A1.4 I/O Relay Number
The input and output terminal numbers of a mixed-I/O module or multifunctional module
with 32 input and output points each are assigned as 1 to 32 and as 33 to 64, respectively.

Blank Page
A2-1
A2. System Configuration

This chapter describes the FA-M3 system configuration and programming tools.
A2.1 Basic System Configuration

The basic system configuration refers to a system consisting of a main unit only. For more
information on the main unit, see subsection A1.3.1, "Unit."
Sequence CPU module or BASIC CPU module
Power
supply
module
F020101.EPS
Figure A2.1 Example of Basic System Configuration (when a 13-slot base module is used)
A2.2 Multi-CPU System Configuration

A2.2.1 Multi-CPU System Configuration
Multi-CPU system configuration refers to a system comprising multiple CPU modules. A
maximum of four CPU modules can be installed in slots 001 to 004 on the main unit. A
CPU module installed in slot 001 serves as the main CPU module and CPU modules
installed in slots 002 to 004 serve as the add-on CPU modules.
A maximum of four sequence CPU modules can be installed at the same time, while only
one F3BP BASIC CPU module is allowed in this system configuration.
A CPU module installed in the Nth (N = 1 to 4) slot is called the Nth CPU (module) or
CPU N.
Main CPU module
Power
supply
module
001 002 003 004 005 006 007 008 009 010 011 012 013 Slot numbers
Add-on CPU modules

F020201.EPS
Figure A2.2 Example of Multi-CPU System Configuration (1 of 2)
Main CPU module
Power
supply
module
001 002 003 004 005 006 007 008 009 010 011 012 013 Slot numbers
The F3CPxx module can be installed

across slots 004 and 005. F020201.EPS
Figure A2.3 Example of Multi-CPU System Configuration (2 of 2)

A2-2
CAUTION
Be careful not to install any CPU module in the 5th or later slot and turn on the power.
Otherwise, the memory is cleared and reverts to the factory settings.
See Also
Subsection 1.1.2, “Limitation on Module Installation,” of Hardware Manual (IM34M6C11-01E) , for
information about limitations on the combination of a main CPU module and add-on CPU modules.
A2.2.2 Handling I/O Modules in Multi-CPU System
■ Input Modules
With input modules, you can read input data through multiple sequence CPUs. To do this,
configure the sequence CPUs so that they share the same input sampling interval for the
input module in question. Be careful, as the sampling interval that you can set varies
depending on the type of sequence CPU.
■ Output Modules and Multifunctional Modules Containing Y

Output Relays
It is not possible to share the same output module among multiple sequence CPUs. Con-
figure the sequence CPU that does not use the output module so that the output module is
set to “unused”.
CAUTION
In multi-CPU system configuration, it is not possible for two or more sequence CPUs to
share the same output relay of any single output module or multifunctional module with
output relays Y. Configure the sequence CPU that does not use the output
module so that the output relays of the output module is set to “Unused” on 16 points basis.
Note again that a CPU module installed in the Nth (N = 1 to 4) slot is called the Nth CPU
(module) or CPU N.
CAUTION
Be careful not to install any sequence CPU module in the 5th or later slot and turn on the
power. Otherwise, the memory is cleared and reverts to the factory settings.
IM 34M6P12-02 3rd Edition : Oct 1, 2001-00

A2-3
A2.3 Extended System Configuration

The extended system configuration refers to a system configured by adding remote I/O
modules, a personal computer link module, and an FA link module to the basic system.
A2.3.1 Remote I/O System

The remote I/O system refers to a system configured using fiber-optic FA-bus or FA-bus
type 2 communication modules.
The number of remote I/O points is included in the count of all I/O points.

Main unit
Subunit Fiber-optic cable
Subunit
Fiber-optic cable, 100-m long
F020302.EPS
Figure A2.4 Example of System Using Fiber-optic FA-bus Type 2 Modules
A2.3.2 Personal Computer Link System

The personal computer link system refers to a system configured by connecting a personal
computer or a monitor to the main unit through a personal computer link module. The
sequence CPU module can be connected directly to a personal computer or a monitor.
Personal computer or monitor

with PC interface
Main unit
Power
supply
module
Personal computer link module

F020303.EPS
Figure A2.5 Example of Personal Computer Link System

A2-4
A2.3.3 FA Link System

The FA link system refers to a system that employs FA link communication to build a net-
work system with programmable controllers.
The types of communication covered by an FA link system are:
FA link H communication (FA link H module), and
Fiber-optic FA link H communication (fiber-optic FA link H module).
Unless otherwise specified, "FA link" in this manual is a general term for these two types of
communication. For more information on the FA link, see the instruction manual
(IM34M6H43-01E), FA Link H and Fiber-optic FA Link H Modules.
FA link
Main unit Main unit Main unit
FA link H module, Fiber-optic FA link H module

F020304.EPS
Figure A2.6 Example of FA Link System

A2-5
A2.4 Programming Tools

The FA-M3 programming tool WideField , or simply WideField, and Ladder Diagram Sup-
port Program M3 are available as programming tools for the FA-M3 system.
A2.4.1 WideField
The table below presents an overview of WideField.
Description Software Model Supported CPUs

F3SP05 F3SP38
F3SP21 F3SP53
FA-M3 Programming Tool WideField SF610-ECW F3SP25 F3SP58
F3SP28 F3FP36
F3SP35
TA020401.EPS
Personal computer
Power
supply
module
FA020401.EPS
Sequence CPU module
Figure A2.7 Overview of WideField
■ Object Ladder
WideField defines "blocks" and "macros" that compose a ladder program as "objects," a
term commonly used in the computing world. The object-oriented ladder language as-
sumes responsibility for a given function and features a high degree of independence.
Consequently, the language offers higher productivity and better maintainability than a
structured programming language. It is therefore effective for the reuse of ladder programs.
■ Features
● Treatment as Components
Blocks can be reused as components. Separately define devices that are used within a
block only. WideField eliminates the chance of using the same device twice and makes it
easy to recombine blocks. You can also break down macro functions into components.

A2-6
● Index View
You can view the overall range of even a large-size program by "hiding" its unnecessary
part. This makes debugging more efficient.
Material feed Initialization Initialization

I***** I***** I***** Y***** Idling Idling
• •
I*****
+ •
CAL = •
I*****
•
• Material feed
I***** Material feed Preheating
MOVE Preheating I***** I***** I***** Y*****
Flux coating
Preheating Finish coat I***** I***** Y*****
Fixation heating
I***** I***** I***** Y***** Cleaning I***** I***** I*****
Cooling CAL = +
I***** I***** Y*****

Unloading I*****
MOVE
I***** I***** I***** •
+
CAL =
Flux coating
•
I***** Finish coat
MOVE
• Fixation heating
Cleaning
Fault-diagnosis
Flux coating Cooling
Power-off sequence
I***** I***** I***** Y*****
Unloading
•
I***** I***** Y***** •
•
I***** I***** I***** Y*****
Fault-diagnosis
I***** Y*****
Power-off sequence
F020402.EPS
● Group Tag Names

You can change the method of naming tag names from an "individual basis" to a "group
basis." This enables you to define a set of data.
SW01 SW02 SW03 SWICH

POMP01 POMP02 POMP03 Definition of POMP
OUT01 OUT02 OUT03 data structure OUT
MCN1
MCN1.SWICH MCN2.SWICH MCN3.SWICH
MCN1.POMP MCN2.POMP MCN3.POMP MCN2 Naming of a
MCN1.OUT MCN3.OUT MCN3.OUT set of data
MCN3
F040403.EPS
● Easy Data Exchange with Windows-based Applications

You can pick data items, such as device names and comments, on a Microsoft Excel
spreadsheet or other documents to import to WideField (drag-and-drop function). In
addition, you can copy ladder circuits in WideField to such applications as Microsoft Word.

A2-7
A2.4.2 Ladder Diagram Support Program M3

The table below presents an overview of Ladder Diagram Support Program M3.
Description Software Model

Windows 95
MS-DOS version
Windows NT 4.0 version
Ladder Diagram Support Program M3
SF510-E3W SF510-E3P
TA020402.EPS
Ladder Diagram Support Program M3, supports both ladder diagram input and mnemonic
input for higher programming efficiency. In addition, its wide choice of debugging functions
reduces the amount of time required for tuning work.
X00503 X00504 Y00602
Personal X00501 X00502 Y00601

computer
X00503
Power
supply
module
Sequence CPU module

FA020402.EPS
Figure A2.8 Ladder Diagram Support Program M3

Blank Page
A3-1
A3. Basic CPU Operations

This chapter describes the basic operation modes of the CPU and add-on CPU
modules, as well as their methods of program execution.
A3.1 Operation Modes of CPU

A CPU has three operation modes: Run, Debug and Stop.
■ Run Mode
The Run mode is a state in which the CPU is running a program, and is used for practical
system operation. You can monitor the operating status of the CPU or devices. However,
you can use none of the debug functions available from the programming tool. In this
mode, the RDY and RUN LED indicators come on.
■ Debug Mode
The Debug mode is used to debug and tune programs.
You can execute programs in the same way as with the Run mode. In the Debug mode,
you can use debugging functions, such as forced SET/RESET instructions and online
editing, through the programming tool. These functions affect the scan time, however.
Disable the functions when debugging and tuning are complete, and set the CPU to the
Run mode. In this mode, the RDY and RUN LED indicators turn on.
The Debug mode includes a pause state in which the CPU suspends program execution
during such debugging operation as scan operation. In this state, the RUN LED indicator
turns off and all external outputs being generated by the program are latched.
■ Stop Mode
The Stop mode is a state in which the CPU stops program execution.
In the Stop mode, you can remove programs and clear devices, in addition to using forced
SET/RESET instructions, online editing and debug operation. In this mode, the RUN LED
indicator turns off.
The external outputs being generated by the program are set to ON (hold) or OFF (reset),
according to the setting of the option "External Output in Case of Sequence Stop" of the
configuration item "DIO Setting." All of the external outputs are set to OFF if the option has
not been set up during configuration.
Table A3.1 summarizes combinations of the LED indicators as classified by the operation mode.
Operation
Mode Run Debug Stop
LED Indicator
RDY On On On
RUN On On or Off Off
ALM Off Off Off
ERR Off Off Off
TA030101.EPS

A3-2
A3.2 Operation at Power-on/off

A3.2.1 Operation at Power-on
When the power is turned on, the CPU performs an initialization process to make itself
ready for program execution.
In the initialization process, the CPU performs I/O collation and instruction analysis in order
to check that its hardware and programs are normal. The CPU begins program execution
from the first step of a program when no error is found.
If equipped with a ROM pack, the CPU reads programs from the pack and begins system
operation.
If in ROM Writer mode, however, the CPU does not read programs from the ROM pack.
Alternatively, it enters a command-wait state (e.g., waits for a ROM transfer command from
the programming tool) without executing a program.
Power-on
Self-diagnosis
NO
No error?
YES The RDY LED
indicator turns on.
YES ROM writer
mode?
NO
NO Equipped with
ROM pack?
YES
Read programs from
ROM pack
Program diagnosis
NO
No error?
Wait for command
YES
Start program Stop
The RUN LED The ERR LED

indicator turns on. indicator turns on.
F030201.EPS
Figure A3.1 Operation at Power-on
A3.2.2 Operation at Power-off

When the power is turned off, the CPU records the date and time in its error log file and
stops system operation.

A3-3
A3.3 Operation in Case of Momentary or Complete

Power Failure
A3.3.1 Operation in Case of Momentary Power Failure
There are two types of power failure detection mode for detecting a momentary power
failure: the standard mode and the immediate detection mode.
The CPU operates differently in case of a momentary power failure, depending on the type
of power failure detection mode selected.
The immediate detection mode can be selected by configuration only when the F3PU10-
0N, F3PU20-0N or F3PU26-0N power supply module is used.
■ Standard Mode
If a momentary power failure occurs, the CPU records the date and time in its error log file.
The CPU suspends processing until it recovers from the power failure. This causes a delay
in the scan time and timer update process.
When the power has recovered, the CPU restarts at the point where it suspended
processing.
A program can cope with a momentary power failure since its occurrence is reflected on a
special relay (M195).
AC voltage
Power failure detection level
Program
execution
Interruption
F030301.EPS
Figure A3.2 Operation in Case of Momentary Power Failure
■ Immediate Detection Mode

If a momentary power failure occurs, the CPU records the date and time in its error log file.
The CPU suspends processing until it recovers from the power failure. At this point the
CPU sets the external outputs being generated by a program to OFF, and actuates the FAIL
contact.
When the power has recovered, the CPU undergoes a reset-and-start sequence and
begins executing the program from its start.
A3.3.2 Specifying the Momentary Power Failure Detection Mode

This configuration item defines the type of momentary power failure detection mode. You
can select either the standard mode or the immediate detection mode. The default is the
standard mode. For more information on each of these modes, see Hardware Manual
(IM34M6C11-01E).
CAUTION
If your system has multi-CPU configuration and you have selected the immediate detection
mode, set all of the CPU modules to this mode.

A3-4
A3.3.3 Operation in Case of Complete Power Failure

If a complete power failure occurs, the CPU operates as it does at power-off.
You can configure the types and ranges of devices to be latched in case of this type of
power failure. This strategy allows the CPU to restart, when it recovers from the power
failure, at the point where it suspended processing.
When the power has recovered, the CPU executes the program from its start.

Complete Power Failure
This configuration item sets the range of devices to be latched in case of a complete power
failure. Specify the starting number and the number of units for each device type.
Table A3.2 shows the default setting and the configurable range of each device type.
Table A3.2 Configuration of Devices to Be Latched in Case of Complete Power Failure (for F3SP21
and F3SP25)
F3SP21 F3SP25
Item
I0001 to Configurable on 32 I0001 to Configurable on 32
Internal relay (I) I1024 points basis; I1024 points basis;
continuous from the continuous from the
Shared and extended Non-latching (*1)
starting number Non-latching starting number
shared relays (E) type type
Configurable on 16 Configurable on 16
Link relay (L) Non-latching points basis Non-latching points basis (*2)
type (Discontinuous) type (Discontinuous)
Non-latching Non-latching
type type
Timer (T) (except for (except for
continuous Configurable on 1 point continuous Configurable on 1 point
timers) basis; timers) basis;
All latched starting number All latched starting number
Counter (C) (C0001 to (C0001 to
C256) C1024)
All latched All latched

Data register (D) (D0001 to Configurable on (D0001 to Configurable on
D5120) 2 points basis; D8192) 2 points basis;
Non-latching starting number Non-latching starting number
Shared registers (R) type type
Configurable on 16
Link register (W) Non-latching Configurable on 16 Non-latching points basis (*2)
type points basis type (Discontinuous)
For notes *1 and *2, see those shown below Table A3.3. TA030301.EPS

A3-5
Table A3.3 Configuration of Devices to Be Latched in Case of Complete Power Failure (for
F3SP35)
F3SP35
Item
Default Configuration Range
I0001 to Configurable on 32
Internal relay (I) I1024 points basis;
continuous from the
Shared relays (E) Non-latching starting number (*1)
type
Configurable on 16
Link relay (L) Non-latching points basis (*2)
type (Discontinuous)
Non-latching
type
Timer (T) (except for
continuous Configurable on 1 point
timers) basis;
continuous from the
All latched starting number
Counter (C) (C0001 to
C1024)
All latched
Data register (D) (D0001 to Configurable on
D8192) 2 points basis;
continuous from the
starting number
Shared registers (R) Non-latching
type
Configurable on 16
Link register (W) Non-latching points basis (*2)
type (Discontinuous)
TA030302.EPS
*1: If the upper limit of the range of shared relays to be used is smaller than E2049, the last of their numbers is followed by
the first of the extended shared relay numbers. Likewise, if the upper limit of shared registers to be used is smaller than
R1025, the last of their numbers is followed by the first of the extended shared register numbers.
*2: The configuration ranges of link relays and registers to be latched in case of power failure are assigned numbers
continuous from their starting numbers. However, the following exceptions apply.
The number following L/W01024 is L/W10001

The number following L/W21024 is L/W30001 These rules are true when the number of link relays or
The number following L/W31024 is L/W40001 registers to be used is defined as 1024 (default). If the
The number following L/W41024 is L/W50001 number is 2048, the number following n2048 is n0001.

A3-6
A3.4 Computation Method

The CPU employs a stored-program iterative computation method.
In this method, a created program is stored beforehand in the memory of the sequence
CPU module. The CPU executes instructions, one at a time, from the first step of the
program. After executing the END instruction, the CPU performs required processes, such
as self-diagnosis. It then repeats the instructions from the first step.
Each of these iterative cycles is called “one scan” and the time required for one scan is
called a “scan time.”
In the case of the F3SP21, F3SP25 and F3SP35 modules, the CPU executes instructions
and peripheral processes concurrently to perform each scan in a shorter time.
Common processing, instruction execution, input refreshing, output refreshing, and
synchronization processing are classified as a system of control-related processes, while
tool service, link service, CPU service, link refreshing, and shared refreshing are classified
as a system of peripheral processes. The CPU performs these two kinds of processes
concurrently and separately to speed up the control-related processes.
Peripheral processes
Common processing
Shared
refreshing
Input refreshing
Output Peripheral
refreshing processes Link refreshing
One scan are performed
Instruction within this Command processing
execution time range. • Tool service
• Link service
• CPU service
Synchronization processing
If synchronization processing begins,
any peripheral process is interrupted
temporarily and resumes at the next scan.
Control-related process
Peripheral process
F030401.EPS
Figure A3.3 Computation Method

A3-7
● System of Control-related Processes
This system performs basic operations of the sequence CPU, such as instruction execution
and I/O refreshing. In the case of the F3SP21, F3SP25 and F3SP35 sequence CPUs,
execution of the system of control-related processes is called one scan, and the execution
time required by the system is usually called a scan time.
● System of Peripheral Processes

This system supports programming tools and performs communication between the CPU
and a personal computer or an FA link module.
The system of peripheral processes is concurrent with and independent of the system of
control-related processes. Therefore, neither the number of modules connected nor the
content of each peripheral process affects the way the system of control-related processes
works.
● Synchronization between Systems of Control-related Processes and

Peripheral Processes
The system of peripheral processes is concurrent with and independent of the system of
control-related processes. For processes related to operation control (e.g., run or stop) or
processes requiring the simultaneity of data, however, the CPU synchronizes these two
systems using a synchronization process included in the system of control-related
processes.
The time required for the synchronization process varies depending on its content. It
affects the scan time when you use a debugging function, such as online editing.
CAUTION
If the ratio of the instruction execution time to the scan time is too small, you may fail to
secure a time long enough to execute the system of peripheral processes. Consequently,
the responses of link refreshing, shared refreshing, tool service, link service and CPU
service will become extremely slow. If this happens, 1) use a constant scan with an interval
somewhat longer than the normal scan time, or 2) define the peripheral processing time to
secure a time long enough to execute the system of peripheral processes.

A3-8
A3.5 Method of I/O Processing

A3.5.1 Method of I/O Processing
As the method of I/O processing, the CPU uses batch refreshing.
In this method, the CPU acquires all data changes in the input module into the input-relay
(X) area of the CPU's data memory before executing each scan.
Thus, the CPU uses data contained in this area when performing computations.
Computation results are output to the output-relay (Y) area of the CPU's data memory each
time a computation is performed. The results are sent to the output module, collectively
and concurrently with the execution of instructions in the next scan.
External input
instrument
Input refreshing
CPU's data memory
Input-relay (X) area
Execution of computations
X00502 Y00602
X00501 X00502 Y00601
X00503 I0001 Y00603
I0002 L0001 Y00604
I0100
Computation
CPU's data memory results
External output
Output-relay (Y) area
instrument
Output refreshing
F030601.EPS
Figure A3.4 Method of I/O Processing

A3-9
A3.5.2 Response Delay

The maximum response delay of the output module against a change in the input module is
two scans. For more information, see Chapter A7, "I/O Response Time Based on Scan
Time."
External input instrument

is turned on
X00502 Y00602
"ON"
"ON"
Instruction execution Instruction execution
The change is acquired at this The change is reflected at this

moment of input refreshing. moment of output refreshing.
Response delay of
two scans
One scan One scan
Output
External output instrument

turns on.
F030602.EPS
Figure A3.5 Response Delay
A3.5.3 I/O Processing in Multi-CPU System

In a multi-CPU system, it is possible for multiple CPUs to use the same input relays. It is
not possible, however, for these CPUs to use the same output relays of any single module
or multifunctional module. With the configuration function, define I/O modules to be used
by each CPU beforehand. When performing sequencing, each CPU refreshes data ac-
cording to this definition.
Main CPU module (sequence CPU or BASIC CPU module)
Power
supply
module
Slot numbers
Add-on CPU modules
(sequence CPU or BASIC CPU modules) F030603.EPS
Figure A3.6 Example of Multi-CPU System

A3-10
A3.6 Method of Executing Commands from the

Programming Tool
The CPU uses tool services to execute commands from the programming tool. These
commands include downloading, uploading, monitoring and debugging programs.
A3.6.1 Tool Service

Tool services execute commands sent from the FA-M3 Programming Tool WideField or
Ladder Diagram Support Program M3.
Since processed concurrently with the execution of instructions, the tool services do not
affect the scan time. The CPU does not execute the tool services if there is no command to
be processed.
Monitor display
X00503 X00504 Y00602

Personal computer
X00501 X00502 Y00601
X00503
Upload Download
Power
supply
module
Sequence CPU module

Sequence CPU
Common processing
Shared refreshing
Input refreshing
Output
refreshing Link refreshing
Instruction Command processing

execution • Tool service
• Link service
• CPU service
F030701.EPS
Figure A3.7 Execution of Commands Sent from Programming Tool

A3-11
A3.7 Method of Executing Commands through

Personal Computer Link
The CPU uses link services to execute commands sent through the personal computer link.
These commands include downloading and uploading programs and reading from and
writing to devices.
A3.7.1 Link Service

Tool services execute commands sent from a personal computer or a monitor connected to
the personal computer link module.
Since processed concurrently with the execution of instructions, the link services do not
affect the scan time. The CPU does not execute the link services if there is no command to
be processed.
Personal computer
or monitor
Sequence CPU module
Power
supply
module
Sequence CPU Personal computer link module
Common processing
Shared refreshing
Input refreshing
Output
refreshing Link refreshing
Instruction Command processing

execution ¥ Tool service
¥ Link service
¥ CPU service
F030801.EPS
Figure A3.8 Execution of Commands through Personal Computer Link

A3-12
A3.8 Method of CPU-to-CPU Data Communication

CPU-to-CPU communication in a multi-CPU system configured using add-on CPUs is
carried out by means of shared refreshing and CPU services.
A3.8.1 Shared Refreshing

Data exchange between the sequence CPU and an add-on CPU is carried out through
shared relays, extended shared relays (for F3SP25 and F3SP35 only), shared registers
and extended shared registers (for F3SP25 and F3SP35 only). Shared refreshing updates
the data of these shared/extended shared relays and shared/extended shared registers
that are exchanged between the CPUs. You must configure in advance the range of shared
devices to be used with the local and remote CPUs. Shared refreshing is performed
irrespective of how the sequence CPU is combined with an add-on CPU or CPUs. Since
shared refreshing is concurrent with instruction execution, it does not affect the scan time.
Shared refreshing is not performed if there are no add-on CPUs installed.
Sequence CPU module
Sequence CPU
Common process
Output refresh
Link refresh
Instruction
Shared refresh execution
1 scan
Tool service
Link service
CPU service
Input refresh
Synchronization process
Figure A3.9 Shared Refreshing
Figure A3.10 shows an example of how shared refreshing is performed between the
sequence CPU and add-on CPU. This example assumes that shared relays and registers
are assigned to each CPU as shown below.
• Sequence CPU (CPU 1): Shared relays: E0001 to E0512
Shared registers:R0001 to R0256
• Add-on CPU (CPU 2): Shared relays: E0513 to E1024
Shared registers:R0257 to R0512

A3-13
CPU 1
X00502
MOV $100 R0001
X00501 E0513 E0001
CPU 1 CPU 2
Shared - relay area Shared - relay area
CPU 1 CPU 2
Shared - register area Shared - register area
CPU 1 CPU 2
CPU 2 Shared refresh Shared refresh
CPU 1 CPU 2
Shared - relay area Shared - relay area
CPU 1 CPU 2
Shared - register area Shared - register area
E0001 X00504
MOV R0001 D0001
X00501 T001 E0513
X00503
Figure A3.10 Shared Refreshing
CAUTION
Shared relays/registers and extended shared relays/registers are refreshed asynchro-
nously with scans performed by each CPU. The simultaneity of data is therefore not guar-
anteed.

A3-14
A3.8.2 CPU Service

CPU services exchange data and process commands, such as starting the program,
between the sequence CPU and a BASIC CPU.
CPU services are provided irrespective of how the sequence CPU is combined with an
add-on CPU or CPUs. Since processed concurrently with the execution of instructions, the
CPU services do not affect the scan time. CPU services are not provided if there are no
add-on CPUs installed.
Add-on CPU module
Sequence CPU
Common process
Output refresh
Link refresh
Instruction
1 scan
Tool service
Link service
CPU service
Input refresh
Figure A3.11 CPU Service

A3-15
A3.9 Method of Link Data Updating

A3.9.1 Link Refreshing
Data exchange with the sequence CPU of a remote station is carried out through link relays
and link registers. Link refreshing updates the data of these link relays and registers for FA
link modules. You must configure in advance, the range of link relays/registers to which you
will write data to and use for local and remote CPUs. Since link refreshing is concurrent with
instruction execution, it does not affect the scan time. Link refreshing is not performed if
there are no FA link modules installed.
FA link
Sequence CPU
Common process
Output refresh
Link refresh
Instruction
1 scan
Tool service
Link service
CPU service
Input refresh
Figure A3.12 Link Data Updating

A3-16
Figure A3.13 shows an example of how link refreshing is performed.
Station 1
X00502
MOV $100 W0001
X00501 L0033 L0001
Station-1 Station-n
Link relay area Link relay area
Station-1 Station-n
Link register area Link register area
Link refresh Link refresh

FA link
Station-1 Station-n
Link refresh Link refresh

Station n
Station-1 Station-n
Link relay area Link relay area
Station-1 Station-n
Link register area Link register area
L0003 X00504
MOV W0001 D0001
X00501 L0001 L0033
X00503
Figure A3.13 Link Refreshing
CAUTION
It is not possible for multiple CPUs to use the same FA link module. Allow only one
sequence CPU to have access to the link relays/registers of each FA link module.

A3-17
A3.10 Method of Interrupt Processing

A3.10.1 Interrupt Processing
The sequence CPU module detects the rising edge of an interrupt input signal from an
input module and executes an interrupt program. You can register a maximum of four
interrupt programs with the sequence CPU module using an INTP instruction. The module
can accept a maximum of eight interrupts at the same time. Interrupt programs are ex-
ecuted in the order in which their interrupt factors occur. If any interrupt factor occurs during
execution of an interrupt program, the factor is processed when the interrupt program
finishes.
Interrupt Factor 1
Interrupt Factor 2
Interrupt Program 1
Executed when Interrupt Program 1
has been executed.
Interrupt Program 2
FA031001.EPS
Interval of wating for completion of interrupt program 1

Figure A3.14 Interrupt Processing
CAUTION
• Do not register any interrupt program intended for a particular input module with two or
more CPU modules. This is because the modules may fail to execute input interrupt
processing.
• Do not use a TIMER instruction in any interrupt program, because the instruction may
not work correctly.

A3-18
A3.10.2 Interrupt Processing Control

You can control your execution of interrupt programs by means of programming. Use EI
and DI instructions to determine whether the interrupt program in question is "executed"
(cancellation of interrupt prohibition) or "not executed" (prohibition of interrupt). The default
is the "Executed" option. Although the sequence CPU recognizes any interrupt occurring in
a case where you have selected the "Not executed" option with a DI instruction, it does not
execute the relevant interrupt program.
Such interrupts are processed in order of their occurrence, after you have selected the
"Executed" option with an EI instruction.
A maximum of eight interrupts are accepted at the same time. Simultaneous input of nine
or more interrupts results in an interrupt error.
I0001 Y00602
An interrupt
occurs.
X00501
DI
X00503 I0002 Y00603
X00501 X00502 I0004

The interrupt program
is not executed in this I0003
period. I0005
EI
INTP X00301
IRET
FA031002.EPS
Figure A3.15 Interrupt Processing Control

A4-1
A4. Devices
This chapter describes the types and functions of devices available with the
sequence CPU modules.
A4.1 I/O Relays (X/Y)

I/O relays are devices used to exchange data with external devices. I/O-relay numbers are
determined by the position of the slot where an I/O module is installed. They are fixed,
discontinuous numbers and are assigned in increments of 64 relays for each slot. The
input-relay (X) numbers never coincide with any of the output-relay (Y) numbers. Data held
in the I/O relays is not retained when the power is turned off. For more information on I/O-
relay number definitions, refer to Section A1.3, “Basic Configuration.”
A4.1.1 Input Relays (X)

Input relays are used to input the ON and OFF states of external devices, such as
pushbuttons and limit switches. In programs, you can use these relays for contacts a and b
and advanced instructions.
Input-relay numbers are coded as Xlmmnn, where:
lmm : Slot number
l : Unit number (0 to 7) (when the F3SP21, F3SP25 or F3SP35 is used)
mm : Slot position (01 to 16)
nn : Terminal number (1 to 64)
X00502 Y00602
Input from
external X00501 X00502 Y00601
devices
X00503 X00504 Y00603
X00501 X00502 Y00604

X00503
F040101.EPS
Figure A4.1 Input Relays

A4-2
A4.1.2 Output Relays (Y)

Output relays are used to output the results of program-based control to external devices,
such as actuators. In programs, you can use these relays, for example, for contacts a and
b, coils and advanced instructions.
Output-relay numbers are represented as Ylmmnn, where:
lmm : Slot number
l : Unit number (0 to 7) (when the F3SP21, F3SP25 or F3SP35 is used)
mm : Slot position (01 to 16)
nn : Terminal number (1 to 64)
X00502 Y00602
X00501 X00502 Y00601

Output to
X00503 X00504 Y00603 external
devices
X00501 X00502 Y00604
X00503
F040102.EPS
Figure A4.2 Output Relays
A4.1.3 Allocation of I/O Addresses

There is no need to allocate I/O address through the programming tool.
I/O-relay numbers are determined by the position of the slot where an I/O module is in-
stalled. They are fixed, discontinuous numbers and assigned in increments of 64 relays for
each slot. An empty slot is regarded as being equivalent to 64 relays.
1 2 3 4 1 2 3 4
Empty Empty Empty
Empty slot slot slot slot
CPU X32 X32 Y32 32 32 32 32
64 relays 32 32
relays relays relays relays relays relays
Relay numbers X00201 to X00301 to Y00401 to

X00232 X00332 Y00432
1 2 3 4 5 1 2 3 4 5
Empty Empty
Empty slot slot Empty slot slot
CPU X64 X32 Empty Y32 64 32 32 32 32
slot 64 relays 64 relays
relays relays relays relays relays
Relay numbers X00201 to X00301 to Y00501 to

X00264 X00332 Y00532
F040103.EPS
Figure A4.3 Allocation of I/O Addresses

A4-3
A4.1.4 Configuring DI/O Modules
■ Specifying Data Code Type

Determine whether data held in I/O relays (X/Y) should be “handled as BIN data” or
“handled as BCD data” when you use them for a Compare, Arithmetic or Move instruction.
All internal computations are based on BIN data. For this reason, if you set the I/O relays to
the option “Handled as BCD Data,” the type of data code (format) of the input relays is
automatically converted from BCD to BIN, while the data format of the output relays is
automatically converted from BIN to BCD.
This option enables you to handle data easily, without having to be conscious of the data
format during programming, in cases where data handled by external devices are in BCD
format.
By default, all I/O modules are set to the option “Handled as BIN Data.” You can specify the
data code type in increments of 16 relays.
■ Specifying Input Sampling Interval

Set the input sampling interval of input modules. However, this setting is not effective for
some input modules. Refer to the data item “response time” in the specifications section of
each individual input module discussed in Hardware Manual (IM34M6C11-01E).
You can select from the two options, “16 ms” and “1.0 ms.” By default, all input modules are
set to “16 ms.” You can specify the sampling interval in increments of 16 relays. Note that if
you set any of the input modules to 1.0 ms, all of them are set to that option.
CAUTION
If a single input module (or advanced module with X input relays) is to be used
with two or more CPUs in multi-CPU system configuration, configure the CPUs so that they
share the same sampling interval for that input module. (Also reconfigure any CPU whose
input relays were set to the option “Unused,” so that their settings become equal to those of
other CPUs.)
■ Specifying Use/Non-use I/O Modules

Select either of the two options, “Used” or “Unused,” in order to determine whether or not
the I/O module in question is used in programs. In this selection, configure I/O modules on
a slot-by-slot basis. Also configure multifunctional modules containing I/O relays in the
same way as discussed here. I/O modules in slots that are included in the option “Unused”
are not I/O-refreshed at all. The results of computation given by the program, therefore, are
not reflected in any external device. By default, all I/O modules are set to the option “Used.”

A4-4
■ Holding/Resetting Output Relays When a Program Stops
Determine whether the output relays of an output module (or multifunctional module with
output relays Y) should be placed in a “Hold” state or “Reset” state when a pro-
gram stops (due to a moderate or major failure or a change to stop mode). The setting of
this configuration for a stop of programs due to a major failure is not effective for some
output modules, however. Refer to the data item “output in case of stop of programs” in the
specifications section of each individual output module discussed in Hardware Manual
(IM34M6C11-01E).
For a multifunctional module, the setting for a stop of programs due to a major failure is
always set to ineffective.
By default, all output modules are set to the option “Reset.” You can perform this configura-
tion in increments of 16 relays.
CAUTION
If a single output module (or advanced module with X output relays) is to be used
by two or more CPUs in multi-CPU system configuration, configure the CPUs so that all of
them share the same output mode, either the “Hold” or “Reset” option. (Also reconfigure
any CPU whose output relays were set to the option “Unused,” so that their settings be-
come equal to those of remote CPUs.)

A4-5
A4.2 Internal Relays (I), Shared Relays (E) and

Extended Shared Relays (E)
A4.2.1 Internal Relays (I)
Internal relays are auxiliary relays available for programs.
In programs, you can use these relays, for example, for contacts a and b, coils and ad-
vanced instructions. Unlike I/O relays however, these relays cannot directly exchange
signals with an external device. There is no limitation on the number of contacts a and b
that can be used in a program.
I0001 Y00602
X00501 X00502 I0003
X00503 I0002 Y00603
X00501 X00502 I0004

I0003
F040201.EPS
Figure A4.4 Internal Relays
With the configuration function, you can configure a range of internal relays to determine
whether or not they retain computation results when the power is turned off. If you set the
internal relays so as not to retain computation results, they are cleared to “OFF (0)” when
you:
• turn off the power once and turn it on again;
• change the operation mode to Run or Debug with the programming tool; or
• send a device clearance command from the programming tool.
If you set the internal relays so as to retain computation results, the latest data is retained
after power-off. In this case, the relays are cleared to “OFF (0)” when you send a device
clearance command from the programming tool.

A4-6
A4.2.2 Shared Relays (E) and Extended Shared Relays (E)

Shared and extended shared relays are used to perform CPU-to-CPU communication in
cases where a sequence CPU and add-on CPUs are installed.
The shared relays are available irrespective of how the sequence CPU is combined with
the add-on CPUs. The extended shared relays are available only if the F3SP25 or F3SP35
sequence CPU is combined with another one or more F3SP25 or F3SP35 sequence CPUs
installed as add-on CPUs.
In programs, you can use these relays, for example, for contacts a and b, coils and ad-
vanced instructions. In addition, you can exchange ON/OFF data between CPUs by using
shared relays of the local CPU as coils and those of the remote CPUs as contacts.
CAUTION
If you write data to a device area other than that of the local CPU, information held by
shared and extended shared relays of remote CPUs are overwritten. This results in a
failure for these shared relays to reflect the correct results of computation.
By default, no shared relays are assigned as devices. When using shared relays, set their
range by means of the configuration function. Assign the same range for all of the CPUs.
Otherwise, the shared relays are not correctly refreshed.
Note that advanced instructions that contain any extended shared relays are excluded from
high-speed processing.
SEE ALSO
Section 1.7, “High speed Processing of Application Instructions,” Sequence CPU

Instruction Manual - Instructions (IM34M6P12-03E), for details on the high-speed process-
ing of application instructions.

A4-7
Figure A4.5 shows an example of how specific shared relays are shared if you allocate
shared relays E0001-0512 to CPU1 and E0513-1024 to CPU2.
CPU I
I0001 E0010
E0513 X00502 I0003
CPU 2
X00503 E0010 Y00603
X00501 X00502 E0513

I0003
F040202.EPS
Figure A4.5 Shared Relays
With the configuration function, you can configure a range of shared relays to determine
whether or not they retain computation results when the power is turned off. By default, all
shared relays are set so as not to retain computation results. If you set the shared relays to
this option, they are cleared to “OFF (0)” when you:
• turn off the power and turn it on again;
If you set the shared relays so as to retain computation results, the latest results are re-
tained after power-off. In this case, the relays are cleared to “OFF (0)” when you send a
device clearance command from the programming tool.

A4-8
CAUTION
When using shared or extended shared relays, follow the precautions given below.
(1) Index modification of shared or extended shared relays

When applying index modification to shared or extended shared relays of the local CPU, be
careful that a relay number resulting from index modification does not exceed the range
specified by configuration for the local CPU. Otherwise, information held by shared or
extended shared relays of remote CPUs is overwritten. This results in a failure for these
shared relays to reflect the correct results of computation.
X00503 E0010 Y00703

V01
X00501 X00502 L0702
I0003
Make sure the relay number

does not exceed the range set
for the local CPU.
F040203.EPS
Figure A4.6 Precautions when Using Shared or Extended Shared Relays (1 of 2)
(2) Block move and computation of multiple devices’ data

When using shared or extended shared relays in an instruction for transferring or comput-
ing data held by multiple devices, be careful that the specified range of these relays does
not exceed the range specified by configuration for the local CPU. Otherwise, information
held by shared or extended shared relays of remote CPUs is overwritten. This results in a
failure for these shared relays to reflect the correct results of computation.
X00501 X00504
BMOV D0001 E0001 D0100
X00501 X00504
BMOV D0001 E0001 10
Make sure the range does

not exceed the range set
for the local CPU.
F040204.EPS
Figure A4.7 Precautions when Using Shared or Extended Shared Relays (2 of 2)
(3) Simultaneity of data

anteed.

A4-9
A4.2.3 Configuring Internal Relays (I), Shared Relays (E) and

Extended Shared Relays (E)
Set the range of internal, shared and extended shared relays to be used. This configuration
is necessary when an add-on CPU or CPUs are installed. Ranges are assigned to these
devices in the order of internal relays and then shared relays and on 32 points basis.
Table A4.1 Configuration of Internal and Shared Relays (for F3SP21, F3SP25 and F3SP35)

Item
Default Configuration Range Default Configuration Range Default Configuration Range
4096 points max. on 8192 points max. on 16384 points max. on

I0001 to 32 points basis for all I0001 to 32 points basis for all I0001 to 32 points basis for all
Internal relay (I) I4096 I8192 16384 internal and shared
internal and shared internal and shared
relays combined relays combined relays combined
Internal relay numbers: Internal relay numbers: Internal relay numbers:
I0001 to I4096 I0001 to I8192 I00001 to I16384
Shared relay (E) – Shared relay numbers: – Shared relay numbers: – Shared relay numbers:
E0001 to E2048 E0001 to E2048 E0001 to E2048
Configurable on 32 Configurable in on 32
Extended points basis for relay points basis for relay
shared relay (E) – – – numbers from E2049
– numbers from E2049
to E4096 to E4096
TA040201.EPS
CAUTION
The starting number of extended shared relays is always E2049, even if the range of
shared relays to be used is less than 2048.

A4-10
■ Configuring Shared and Extended Shared Relays in Multi-CPU System
Set the range of shared and extended shared relays to be used by each CPU in a multi-
CPU system when add-on CPU modules are installed.
You can allocate a desired number of relays in increments of 32 devices.
Extended shared relays are only available if one of the F3SP25, F3SP28, F3SP35,
F3SP38, F3SP53 and F3SP58 sequence CPUs is combined with another one or more of
these CPUs installed as add-on sequence CPUs.
CAUTION
Apply the same allocation of shared/extended shared relays to all CPUs. If the allocation
differs from CPU to CPU, shared refreshing is not performed correctly. This results in a
failure for these relays to reflect the correct results of computation.
Shared relays
CPU 1 CPU 2 CPU 4
E0001
256 points 256 points 256 points CPU-1
shared relays
E0257
1024 points 1024 units 1024 points
CPU-2
shared relays
E1281
shared relays
E1793
shared relays
Extended shared relays

CPU 1 CPU 2 CPU 4
E2049
1024 points 1024 points 1024 points
CPU-1
extended
shared relays
E3073 CPU-2
256 points 256 points 256 points extended
shared relays
E3329
CPU-3
shared relays
E3841 CPU-4
shared relays
F040205.EPS
Figure A4.8 Example of Allocating Shared/Extended Shared Relays when Four Sequence CPUs
Are Installed

A4-11
A4.3 Link Relays (L) and Link Registers (W)

A4.3.1 Link Relays (L)
Link relays are used to exchange data with other programmable controllers through FA link
modules.
In programs, you can use these relays, for example, for contacts a and b, coils, and ad-
vanced instructions. In addition, you can exchange ON/OFF data between CPUs by using
link relays of the local station as coils and those of remote stations as contacts.
Before using the link relays, specify the range of links for both the local station and remote
stations.
Station 1
I0001 L0010
L0513 X00502 I0003
Station n
X00603 L0010 Y00703
X00601 X00602 L0513

I0003
F040301.EPS
Figure A4.9 Link Relays
In the case of the F3SP21 sequence CPU, you can install a maximum of two units of FA link
H modules and fiber-optic FA link H modules combined.
The relay number is coded as Lmnnnn, where:
m : FA link module number –1 (0 or 1)
nnnn : Link relay number
( 1 to 1024 when 1024 points are set to “High Speed” option)
( 1 to 2048 when 2048 points are set to “Normal Speed” option)
(Total number of link relays is 2048.)
In the case of the F3SP25 and F3SP35 sequence CPUs, you can install a maximum of
eight units of FA link H modules and fiber-optic FA link H modules combined.
The relay number is coded as Lmnnnn, where:
m : FA link module number –1 (0 to 7)
nnnn : Link relay number
(Total number of link relays is 8192.)

A4-12
CAUTION
• Use the FA link H module and/or fiber-optic FA link H module only in combination with
the R1.08 or later version of Ladder Diagram Support Program M3 and with the Rev.8
or later version of the F3SP21, F3SP25 and F3SP35.
• For each of the F3LP02 FA link H module and F3LP12 fiber-optic FA link H module,
you can use a maximum of 2048 units of link relays and link registers. The configura-
tion limitations described below apply, however, if a single CPU uses a combination of
fiber-optic FA link H modules configured with 1024 units of link relays/registers set for
high-speed processing and fiber-optic FA link H modules configured with 2048 units of
link relays/registers set for normal-speed processing.
link 2.
Link 1: [1024]; Link 2: [2048]; Link 3: . . .
Link 1: [ 0]; Link 2: [1024]; Link 3: [2048]; . . .
Link 1: [1024]; Link 2: [ 0]; Link 3: [2048]; . . .

Link 1: [2048]; Link 2: . . .
Link 1: [1024]; Link 2: [1024]; Link 3: . . .
Link 1: [ 0]; Link 2: [1024]; Link 3: [1024]; . . .
Link 1: [1024]; Link 2: [ 0]; Link 3: [1024]; . . .
Link 1: [ 0]; Link 2: [2048]; Link 3: . . .
TIP
FA link module (line) numbers are in one-to-one relationship with the FA link modules
installed. The FA link modules are numbered 1, 2, and so on, in ascending order of the
numbers assigned to the slots where the modules are installed. Their link relays are num-
bered L00001 to L01024 (or L02048), L10001 to L11024 (or L12048), and so on.
With the configuration function, you can newly correlate a slot number with each FA link
module number for a slot where the FA link module is installed. The following illustration
shows an example of this configuration, as well as the relationship between the slot num-
bers and link relay numbers.
As shown in the example, this configuration allows you to use the same numbering format,
such as L1nnnn, to encode link relay numbers at each station within a given FA link. In
addition, you need not change the link relay numbers when you install an additional FA link
module.
Even if there are no FA link modules installed, you can specify a maximum of two FA link
module numbers for the F3SP21 sequence CPU module and a maximum of eight FA link
module numbers for the F3SP25/F3SP35 sequence CPU modules.

A4-13
Relationship between FA link modules and
slot numberss
Slot Number
L60001 to L61024 L70001 to L71024 FA link 1 (L00001, . . .): [2]
FA link 2 (L10001, . . .): [9]
FA link 4 (L30001, . . .): [8]
FA link 6 (L50001, . . .): [7]
FA link 8 (L70001, . . .): [6]
Slot numbers
1 2 3 4 5 6 7 8 9
F F F F F F F F F F Up to 32 F F F
3 3 3 3 3 3 3 3 3 3 stations 3 3 3
L S L L L L L L L L S L L
P P P P P P P P P P P P P
0 2 0 0 0 0 0 0 0 0 2 0 0
2 5 2 2 2 2 2 2 2 2 5 2 2
FA-M3 FA-M3 FA-M3 FA-M3
32 stations 32 stations 32 stations 32 stations

max. max. max. max.
With the configuration function,

I0001 L10010 FA link module numbers can be
correlated with slot numbers so
L10513 X00502 I0003 link relay numbers are coded to
the L1nnnn format.
X00503 L10010 Y00603
X00501 X00502 L10513
I0003
F040302.EPS
Figure A4.10 Link Relay Numbers When FA Link Module Numbers Are Correlated with Slot
Numbers Using the Configuration Function (for F3SP25 and F3SP35)

A4-14
With the configuration function, you can determine whether or not link relays retain compu-
tation results when the power is turned off. By default, all link relays are set so as not to
retain computation results. If you set the link relays to this option, they are cleared to OFF
(0) when you:
If you set the link relays so as to retain computation results, the latest results are retained
after power-off. In this case, the relays are cleared to “OFF (0)” when you send a device

A4-15
CAUTION
When using link relays, follow the precautions given below.
(1) Index modification of link relays

Do not apply index modification to link relays.
A link relay, whose number is directly specified in an instruction and to which contents of an
index register have been added, is excluded from link refreshing. This will result in incorrect
computation.
X00503 L0010 Y00602

V1
X00501 X00502 L0513
I0003
Do not apply index modification.
F040303.EPS
Figure A4.11 Precautions when Using Link Relays (1 of 2)
(2) Block move and computation of multiple devices

When using link relays in an instruction for transferring or computing multiple devices’ data,
use only literals to specify the number of devices to be included in the transfer or computa-
tion. If you specify the number indirectly, the range of link relays whose numbers are
directly specified in the instruction and link relays thus indirectly specified are excluded from
link refreshing. This will result in incorrect computation.
When using link relays in an instruction for transferring or computing multiple devices’ data,
be careful that the range of link relays, whose numbers are directly specified in the instruc-
tion and link relays included in the transfer or computation, does not exceed the range set
for the FA link module specified. Otherwise, correct operation is not guaranteed.
X00501 X00504
BMOV L0001 D0001 D0100
Do not indirectly specify the number of devices.
X00501 X00504
BMOV L0001 D0001 10
Use a literal to specify the number.

F040304.EPS
Figure A4.12 Precautions when Using Link Relays (2 of 2)
(3) Multi-CPU system configuration

It is not possible to use the same FA link module with multiple CPUs. Allow only one se-
quence CPU to access link relays of each FA link module.

A4-16
A4.3.2 Link Registers (W)

Link registers are used to exchange data with other programmable controllers through FA
link modules. In programs, you can read from or write to link registers in 16-bit or 32-bit
increments using advanced instructions.
When you use link registers on a 32-bit basis, the lower-order 16 bits are stored in the link
register with the number specified in the instruction and the higher-order 16 bits are stored
in the link register with that number incremented by 1.
Data exchange can be performed between the local station and remote stations by writing
data to link registers of the local station and reading it from the remote stations. Before
using the link registers, specify the range of links for both the local station and remote
stations.
Station 1
X00502
MOV $100 W0001
X00501 X00502 Y00601
Station n
X00503 X00504
MOV W0001 D0001
X00501 T001 Y00602
X00503
F040305.EPS
Figure A4.13 Link Registers
In the case of the F3SP21 sequence CPU, you can install a maximum of two units of FA link
H modules and fiber-optic FA link H modules combined.
The register number is coded as Wmnnnn, where:
m : FA link module number –1 (0 or 1)
nnnn : Link register number
(Total number of link registers is 2048.)
In the case of the F3SP25 and F3SP35 sequence CPUs, you can install a maximum of
eight units of FA link H modules and fiber-optic FA link H modules combined.
The register number is coded as Wmnnnn, where:
m : FA link module number –1 (0 to 7)
nnnn : Link register number
(Total number of link registers is 8192.)

A4-17
CAUTION
• Use the FA link H module and/or fiber-optic FA link H module only in combination with
the R1.08 or later version of Ladder Diagram Support Program M3 and with the Rev.8
• For each of the F3LP02 FA link H module and F3LP12 fiber-optic FA link H module,
you can use a maximum of 2048 units of link relays and link registers. The configura-
tion limitations described below apply, however, if a single CPU uses a combination of
FA link H or fiber-optic FA link H modules configured with 1024 units of link relays/
registers set for high-speed processing and FA link H or fiber-optic FA link H modules
configured with 2048 units of link relays/registers set for normal-speed processing.
link 2.
Link 1: [1024]; Link 2: [2048]; Link 3: . . .
Link 1: [ 0]; Link 2: [1024]; Link 3: [2048]; . . .
Link 1: [1024]; Link 2: [ 0]; Link 3: [2048]; . . .

Link 1: [2048]; Link 2: . . .
Link 1: [1024]; Link 2: [1024]; Link 3: . . .
Link 1: [ 0]; Link 2: [1024]; Link 3: [1024]; . . .
Link 1: [1024]; Link 2: [ 0]; Link 3: [1024]; . . .
Link 1: [ 0]; Link 2: [2048]; Link 3: . . .

A4-18
Relationship between FA link modules
and slot numbers
Slot Number
W60001 to W61024 W70001 to W71024 FA link 1 (W00001, . . .): [2]
FA link 2 (W10001, . . .): [9]
FA link 4 (W30001, . . .): [8]
FA link 6 (W50001, . . .): [7]
FA link 8 (W70001, . . .): [6]
Slot number
1 2 3 4 5 6 7 8 9
F F F F F F F F F F Up to 32 F F F
3 3 3 3 3 3 3 3 3 3 stations 3 3 3
L S L L L L L L L L S L L
P P P P P P P P P P P P P
0 5 0 0 0 0 0 0 0 0 5 0 0
2 8 2 2 2 2 2 2 2 2 8 2 2
Up to 32 Up to 32 Up to 32 Up to 32
stations stations stations stations
With the configuration function,

X00502 FA link module numbers can be
MOV $100 W10001 correlated with slot numbers so
X00501 X00502 Y00601 link register numbers are coded
to the W1nnnn format.
X00503 X00504
MOV W10001 D0001
X00501 T001 Y00602
X00503
F040306.EPS
Figure A4.14 Link Register Numbers When FA Link Module Numbers Are Correlated with Slot
Numbers Using the Configuration Function (for F3SP25 and F3SP35)

A4-19
With the configuration function, you can determine whether or not link registers retain
computation results when the power is turned off. By default, all link registers are set so as
not to retain computation results. If you set the link registers to this option, they are cleared
when you:
If you set the link registers so as to retain computation results, the latest results are retained
after power-off. In this case, the registers are cleared when you send a device clearance
command from the programming tool.

A4-20
CAUTION
When using link registers, follow the precautions given below.
(1) Index modification of link registers

Do not apply index modification to link registers.
A link register, whose number is directly specified in an instruction and to which contents of
an index register have been added, is excluded from link refreshing. This will result in
incorrect computation.
V1
X00501
MOV W0001 B0001
X00501 T001 Y00602
I0003
Do not apply index modification.

F040307.EPS
Figure A4.15 Precautions when Using Link Registers (1 of 2)

When using link registers in an instruction for transferring or computing multiple devices’
data, use only constants to specify the number of devices to be included in the transfer or
computation. If you specify the number indirectly, the range of link registers whose num-
bers are directly specified in the instruction and link registers thus indirectly specified, are
excluded from link refreshing. This will result in incorrect computation.
When using link registers in an instruction for transferring or computing multiple devices’
data, be careful that the range of link registers, whose numbers are directly specified in the
instruction and link registers included in the transfer or computation, does not exceed the
range set for the FA link module specified. Otherwise, correct operation is not guaranteed.
X00501 X00504
BMOV W0001 D0001 D0100
Do not indirectly specify the number of devices.
X00501 X00504
BMOV W0001 D0001 10
Use a constant to specify the number.

F040308.EPS
Figure A4.16 Precautions when Using Link Registers (2 of 2)
(3) Multi-CPU system configuration

It is not possible to use the same FA link module with multiple CPUs. Allow only one se-
quence CPU to access link registers of each FA link module.

A4-21
A4.3.3 Configuring Link Relays (L) and Registers (W)

Set the range of link relays and registers to be used. More specifically, specify the range of
link relays and registers to which data is written at the local station or from remote stations.
Table A4.3 Configuration of Device Sizes
F3SP21 F3SP25,F3SP35
Item Configuration Configuration
Default Range Default Range
2048 max. on 16 8192 max. on 16
Link relays for each 1024 points points basis for 1024 points points basis for
FA link module all links all links
for each link combined for each link combined
number(L)
Device size
2048 max. on 16 8192 max. on 16
Link registers for points basis for points basis for
1024 points 1024 points
each FA link module for each link all links for each link
all links
number(W) combined combined
TA040301.EPS
Table A4.4 I/O Module Settings
F3SP21 F3SP25,F3SP35
Item Configuration Configuration
Default Range Default Range
Link relays to be Configurable on Configurable on

written at local 32 points for 16 points basis 32 points for 16 points basis
station(L) each station for each station each station for each station
I/O module
settings
Link registers to be 32 points for Configurable Configurable
written at local on 1 point basis on 1 point basis
each station for each station 32 points for for each station
station(W) each station
TA040302.EPS

A4-22
A4.4 Special Relays (M)

Special relays have specific functions, such as indicating the internal state of a CPU or
detecting errors.
In programs, these relays are used mainly for contacts a and b.
A4.4.1 Block Start Status

Block start status relays indicate which block is running when the selected blocks are being
executed.
These relays are numbered in ascending order as M001, M002, . . ., to correlate with block
1, block 2, ...
Table A4.5 Block Start Status
Item Description
CPU Module Relay Number Name Function Remarks
Block n start ON : Run Indicate whether block n

F3SP21, F3SP25 and F3SP35 (Note) M0001 to M0032 OFF : Stop is in progress or at a stop
status relay
when blocks are selected
and executed.
Note: The start status relays assigned to blocks 1 to 32 are M0001 to M0032 and M2001 to M2032, where the
values of M0001 to M0032 are the same as those of M2001 to M2032. Similarly, start status relays M2033 to
M3024 are assigned to blocks 33 to 1024.
TA040401.EPS
CAUTION
Do not write to a special relay, including those not listed in the table above (e.g., M067 to
M128), unless otherwise stated. This is because they are used by the CPU module for the
system. If you inadvertently write to these relays, a failure, such as a system shutdown,
may result. (It is also prohibited to use a forced set/reset instruction in debug mode.)

A4-23
A4.4.2 Utility Relays

Utility relays are used to provide timing in a program or give instructions to the CPU.
Table A4.6 Utility Relays
Item Utility Relays
No. Name Function Description
Always ON ON
M033
OFF Used for an initialization process or as a
dummy contact in a program.
Always OFF ON
M034
OFF
On-for-one-scan- Turns on for one scan only after the start

M035 1 scan of a program.
at-start-of-operation
Generates a clock pulse with a 0.01-sec

M036 0.01-sec clock 0.005s 0.005s
period.
0.02-sec clock Generates a clock pulse with a 0.02-sec

M037 0.01s 0.01s
period.
0.1-sec clock 0.05s 0.05s Generates a clock pulse with a 0.1-sec

M038
period.

M039 0.1s 0.1s
period.
Generates a clock pulse with a 1-sec

M040 1-sec clock 0.5s 0.5s
period.

M041 2-sec clock 1s 1s period.
30s 30s Generates a clock pulse with a 1-min

M042 1-min clock period.
Normal subunit ON: Normal transmission line or no fiber-optic FA-bus installed

M066 transmission line OFF: Unspecified or abnormal transmission line
TA040402.EPS
CAUTION
The special relay M066 (Normal Subunit Transmission Line) is only available with the Rev.8
SEE ALSO
Fiber-optic FA-bus Module and Fiber-optic FA-bus Type 2 Module (IM34M6H45-01E), for
more information on the M066 utility relay (Normal Subunit Transmission Line).

A4-24
A4.4.3 Sequence Operation and Mode Status Relays

Sequence operation and mode status relays indicate the status of sequence operation or
each mode.
Table A4.7 Sequence Operation and Mode Status Relays
Item Utility Relays
Run mode flag ON: Run mode Indicates the status of CPU operation.
M129
OFF: Other modes
ON: Debug mode

M130 Debug mode flag Indicates the status of CPU operation.
OFF: Other modes
Stop mode flag ON: Stop mode Indicates the status of CPU operation.
M131
OFF: Other modes
Pause flag ON: Pause Indicates the status of program execution

M132
OFF: Program execution during debug mode operation.
ON: Specified blocks Indicates whether specified blocks or all

M133 Execution flag
OFF: All blocks blocks are executed.
M134 Remote/local ON: Remote The Local option prohibits access through
(write-enabled) mode flag OFF: Local FA links.
RAM/ROM-based ON: ROM-based operation Indicates whether operation is based on

M135 operation flag OFF: RAM-based operation the ROM or RAM.
M136 Power-on ON: Power-on operation Indicates whether the system has been
(Note) OFF: Other modes of put in run mode at power-on or by
operation flag
operation resetting.
M172 Time setting ON: Time being set
(write-enabled) Requests to set clock data
(Note) OFF:
ON: Offline Indicates that input refreshing has

M173 Input-off line flag stopped.
OFF: Online
ON: Offline Indicates that output refreshing has

M174 Output-off line flag
OFF: Online stopped.
Shared-I/O ON: Offline Indicates that shared refreshing has

M175 off line flag stopped.
OFF: Online
M176 Link-I/O off line flag ON: Offline

Indicates that link refreshing has stopped.
OFF: Online
Devices reserved
M177 to M187 for extended functions
ON: Carry-enabled A carry flag used for shift or rotation

M188 Carry flag
OFF: Carry-disabled operation.
Devices reserved
Note: Available with the F3SP21, F3SP25 and F3SP35 only

TA040403.EPS
SEE ALSO
Specifications of Z49 to Z54 special registers for clock data for more information on time
setting.

A4-25
A4.4.4 Self-diagnosis Status Relays

Self-diagnosis status relays retain the results of self-diagnosis by the sequence CPU.
Table A4.8 Self-diagnosis Status Relays
Item Utility Relays
Error information is stored in special
M193 Self-diagnosis error ON: An error is found. registers Z17 to Z19 for updating the
OFF: No error is found results of self-diagnosis.
ON: Abnormal.
M194 Battery failure Indicates a failure in backup batteries.
OFF: Normal.
ON: A momentary power

Momentary failure is found. Indicates that a momentary failure has
M195 occurred.
power failure OFF: No momentary power
failure is found.
CPU-to-CPU ON: Abnormal. Indicates that a communication failure

M196
communication failure OFF: Normal. has occurred in shared relays/registers.
ON: Exists. Indicates whether or not a CPU exists in

M197 Existence of CPU1 OFF: Does not exist. slot 1.

M198 Existence of CPU2
OFF: Does not exist. slot 2.


Information on an error that may occur
Instruction ON: An error is found. during instruction processing is stored in
M201
processing error OFF: No error is found special registers Z22 to Z24.
Indicates that the state of module
M202 I/O collation error ON: Abnormal. installation is not consistent with the
OFF: Normal. program.
ON: Abnormal. Indicates that no access is possible to I/O

OFF: Normal. modules. The slot number of the module
M203 I/O module failure
in question is stored in special registers
Z33 to Z40.
ON: Abnormal. Indicates that the scan has exceeded the

M204 Scan time-out
OFF: Normal. scan time monitoring time.
ON: Abnormal
Failure in subunit transmission line.
M210
transmission line OFF: Unspecified or normal The slot number of the fiber-optic FA-bus
transmission line module in question is stored in special
registers Z89 to Z96 if a failure occurs in
ON: Abnormal
the module.
Switchover in subunit transmission line.
M211
transmission line OFF: Unspecified or normal
transmission line
M225 CPU-1 sequence ON: Executes the program. Indicates whether a sequence program
(Note) program execution OFF: Stops the program. for a CPU in slot 1 is running or at a stop.
Note: Available with the F3SP21, F3SP25 and F3SP35 only

TA040404.EPS

A4-26
CAUTION
The self-diagnosis relays M210 (Failure in Subunit Transmission Line) and M211
(Switchover in Subunit Transmission Line) are only available with the Rev.8 or later version
of the F3SP21, F3SP25 and F3SP35.
SEE ALSO
more information on the M210 (Failure in Subunit Transmission Line) and M211
(Changeover in Subunit Transmission Line) self-diagnosis relays.
A4.4.5 FA Link Module Status Relays

FA Link module status relays indicate the status of FA link.
SEE ALSO
Special relays/registers sections of instruction manual (IM34M5H43-01E), FA Link H

Module F3LP02-0N Fiber-optic FA Link H Module F3LP12-0N for more information on
these FA link module status relays.
Table A4.9 FA Link Module Status Relays

Item FA Link Module Status Relays
F3SP21 M257 to M480
ON: Abnormal. Indicate the status of FA
M257 to M480 FA link failure link.
F3SP25,F3SP35 OFF: Normal.
M8321 to M8992
TA040405.EPS

A4-27
A4.5 Timers (T)

There are four types of timer: 1-ms, 10-ms and 100-ms timers and a 100-ms continuous
timer. For each type, you can assign the number of timers using the configuration function.
However, you are not allowed to assign more than 16 points of 1-ms timers.
A4.5.1 1-ms, 10-ms, and 100-ms Timers

1-ms, 10-ms, and 100-ms timers are synchronized-scan, decremental timers which update
their current values and turn on/off their time-out relays using an END process.
Setpoints: 1-ms timer 0.001 to 32.767 s
10-ms timer 0.01 to 327.67 s
100-ms timer 0.1 to 3276.7 s
Each timer starts counting at the rising edge of the timer input, and expires when the
current value reaches 0. When the timer expires, its time-out relay turns on. The time-out
relay is used for a contact a or b. The timer is reset at the falling edge of the timer input and
the current value returns to the timer’s setpoint.
Timer input
X00502
TIM T001 1s
X00501 I0001 Y00601
X00301 T001 Y00603
I0002
ON
Timer input
X00502 OFF
Setpoint
Current value
T001 0
ON 1s
Time-out relay
T001 OFF
F040501.EPS
Figure A4.17 Timer

A4-28
A4.5.2 100-ms Continuous Timer

A 100-ms continuous timer is a synchronized-scan, decremental timer which updates its
current value and turns on/off its time-out relay using an END process.
Setpoint: 0.1 to 3276.7 s
The 100-ms continuous timer retains its current value and the state of its time-out relay
even when the timer input is set to OFF. When the timer input is set to ON again, the timer
starts counting from the value it retains. When the timer input is set to OFF after the con-
tinuous timer expires, the timer is reset, the current value returns to the setpoint, and the
time-out relay is set to OFF.
If you want to reset the continuous timer before it expires, write “0” to the time using a MOV
instruction (MOV 0 Tnnn) when the timer input is in an OFF state.
Timer input
X00502
TIM T241 10s
X00501 I0001 Y00601
X00301 T241 Y00603
I0002
ON
Timer input
X00502 OFF
Setpoint
Current value
T241
0
ON
Time-out relay
T241 OFF
(1) (2)
(1) + (2) =10 s
F040502.EPS
Figure A4.18 100-ms Continuous Timers
With the configuration function, you can configure a range of timers to determine whether
or not they retain their current values when the power is turned off. By default, all timers are
set so as not to retain their current values. If you set the timers to this option, their current
values are reset to their setpoints when you:
If you set the timers so as to retain their current values, the latest results are retained after
power-off. In this case, the timers are reset to their setpoints when you send a device

A4-29
A4.5.3 Selecting Timers

Select the range of 1-ms, 10-ms, and 100-ms timers and 100-ms continuous timers to be
used.
To select the range, specify the number of timers you will use for each type.
The following relationship exists between magnitudes of starting numbers assigned to
these timers, as classified by timer type.
1-ms timer < 10-ms timer < 100-ms timer < 100-ms continuous timer
Allocate 1-ms, 10-ms and 100-ms timers and 100-ms continuous timers to the sequence
CPU, in that order.
Table A4.10 Configuration of Timers

Range Range Range
1-ms timer – – –
Configurable on 1 Configurable on 1 Configurable on 1
10-ms timer T001 to T128 point basis; T0001 to T0512 point basis; T0001 to T1024 point basis;
16 max. for 1-ms T0513 to T0960 16 max. for 1-ms T1025 to T1920 16 max. for 1-ms
100-ms timer T129 to T240
timers; timers; timers;
100-ms Timer numbers Timer numbers Timer numbers
continuous T241 to T256 are continuous. T0961 to T1024 are continuous. T1921 to T2048 are continuous.
timer
TA040501.EPS

A4-30
A4.6 Counters (C)

The counters are decremental counters and have two types of input: count input and reset
input.
A counter detects the rising edge of a count input and updates the current value when a
counter instruction is executed. The counter terminates when its current value reaches 0.
When the counter terminates, its end-of-count relay turns on. The count-up relay is used
for a contact a or b.
The counter is reset at the rising edge of the reset input and the current value returns to the
counter’s setpoint. Count input is not accepted when the reset input is on.
Setpoint: 1 to 32767
Count input
X00502
CNT C001 100
X00501
Reset input
C001 X00504 Y00602
ON
Reset input
X00502 OFF
ON
Count input
X00502 OFF
100
99
98
Current value
C001
0 1
ON
Count-up relay
C001 OFF
F040601.EPS
Figure A4.19 Counter
With the configuration function, you can configure a range of counters to determine
whether or not they retain their current values when the power is turned off. By default, all
counters are set so as to retain their current values. If you set the counters otherwise, their
current values are reset to their setpoints when you:
If you set the counters so as to retain their current values, the latest results are retained
after power-off. In this case, the counters are reset to their setpoints when you send a
device clearance command from the programming tool.

A4-31
A4.6.1 Selecting Counters

Select the range of counters to be used.
Table A4.11 Configuration of Counters

Range Range Range
Sum of timers Sum of timers and Sum of timers and

Timer (T) T001 to T256 and counters: 512 T0001 to T1024 counters: 2048 T0001 to T2048 counters: 3072
points max., on 1 points max., on 1 points max., on 1
Device point basis point basis point basis
size Timer numbers: Timer numbers: Timer numbers:
T001 to T512 T0001 to T2048 T0001 to T3072
Counter (C) C001 to C256 Counter numbers: C0001 to C1024 Counter numbers: C0001 to T1024 Counter numbers:
C001 to C512 C0001 to C2048 C0001 to C3072
TA040601.EPS

A4-32
A4.7 Data Registers (D), Shared Registers (R), and

Extended Shared Registers (R)
A4.7.1 Data Registers (D)
Data registers serve as memory for storing the results of program-based computation.
Each data register has 16 bits. In programs, you can read from or write to data registers in
16-bit or 32-bit increments using advanced instructions.
When you use link registers on a 32-bit basis, the lower-order 16 bits are stored in the data
in the data register with that number incremented by 1.
X00502
MOV $100 D0001
X00501 X00502 Y00601
$1234
X00503 X00504
MOV $5678 D0002
X00501 T001 Y00602
X00503
D0001 $100
D0002 $5678
D0003 $1234
F040701.EPS
Figure A4.20 Data Registers
With the configuration function, you can configure a range of data registers to determine
data registers are set so as to retain the results. If you set the registers otherwise, they are
set to OFF (0) when you:
If you set the registers so as to retain the computation results, the latest results are retained
after power-off. In this case, the registers are set to OFF (0) when you send a device

A4-33
A4.7.2 Shared Registers (R) and Extended Shared Registers (R)

Shared and extended shared registers are used to exchange data between CPUs in multi-
CPU system configuration.
The shared registers can be used regardless of how CPUs are combined. The extended
shared registers can be used only when one of the F3SP25, F3SP28, F3SP35, F3SP38,
F3SP53 and F3SP58 sequence CPUs is combined with one or more units of the F3SP25
or F3SP35 sequence CPUs installed as add-on sequence CPUs.
In programs, you can read from or write to data registers in 16-bit or 32-bit increments
using advanced instructions.
When you use registers on a 32-bit basis, the lower-order 16 bits are stored in the data
in the data register with that number incremented by 1.
Data can be exchanged between the local CPU and a remote CPU by writing the data to
shared registers in the local CPU and reading it from the remote CPU.
If you write data to a device area other than that of the local CPU, information held by
shared registers of the remote CPU is overwritten. This results in a failure for these shared
registers to reflect the correct results of computation.
By default, no shared registers are assigned as devices. When using add-on CPUs, set the
range of shared registers to be used. Assign the same range for all of the CPUs. Other-
wise, the shared registers are not correctly refreshed.
Note that advanced instructions that contain any extended shared register are excluded
from high-speed processing.
SEE ALSO
Section 1.6, “High-speed Processing of Advanced Instructions,” inSequence CPU

Instruction Manual (IM34M6P12-03E) - Instructions, for details on the high-speed process-
ing of advanced instructions.
SEE ALSO
Shared and extended shared registers are used to exchange data (data sharing) between
CPUs in multi-CPU system configuration where sequence CPU and BASIC CPU modules
are installed. For more information on the functions of BASIC CPU modules, refer to:
• BASIC CPU Modules and YM-BASIC/FA Programming Language Instruction Manual
(IM34M6Q22-01E).

A4-34
Figure A4.21 shows an example of how specific shared registers are shared if you allocate
shared registers R0001 to R0256 for CPU 1 and shared registers R0257 to R0512 for CPU
2.
CPU 1
X00502
MOV $100 R0001
X00501 X00502 Y00601
CPU 2
X00503 X00504
MOV R0001 D0001
X00501 T001 Y00702
X00503
F040702.EPS
Figure A4.21 Shared Register
With the configuration function, you can configure a range of shared registers to determine
shared registers are set so as not to retain the results. If you set the registers otherwise,
they are cleared when you:
If you set the registers so as to retain the computation results, the latest results are retained
after power-off. In this case, the registers are cleared when you send a device clearance
command from the programming tool.

A4-35
CAUTION
When using shared or extended shared registers, follow the precautions given below.
(1) Index modification of shared or extended shared registers

When applying index modification to shared or extended shared registers of the local CPU,
be careful that any register number, which is directly specified in an instruction and to which
the content of an index register has been added, does not exceed the range specified by
configuration for the local CPU. Otherwise, information held by shared or extended shared
registers of remote CPUs is overwritten. This results in a failure for these shared registers
to reflect the correct results of computation.
V1
X00501
MOV R0001 B0001
X00501 T001 Y00602
I0003
Make sure the register number
does not exceed the range set
for the local CPU.
F040703.EPS
Figure A4.22 Precautions when Using Shared or Extended Shared Registers (1 of 2)

When using shared or extended shared registers in an instruction for transferring or com-
puting data held by multiple devices, be careful that the range of registers, which is defined
by the register number directly specified in the instruction and the number of registers
included in the transfer and computation, does not exceed the range specified by configura-
tion for the local CPU. Otherwise, information held by shared or extended shared registers
of remote CPUs is overwritten. This results in a failure for these shared registers to reflect
the correct results of computation.
X00501 X00504
BMOV R0001 D0001 D0100
X00501 X00504
BMOV R0001 D0001 10
Make sure the range does not

exceed the range set for the
local CPU. F040704.EPS
Figure A4.23 Precautions when Using Shared or Extended Shared Registers (2 of 2)
(3) Simultaneity of data

anteed.

A4-36
A4.7.3 Configuring Data Registers (D), Shared Registers (R) and

Extended Shared Registers (R)
Set the range of data registers, shared registers and extended shared registers to be used.
This configuration is necessary when an add-on CPU or CPUs are installed. Ranges are
assigned to these devices in the order of data registers and then shared registers and in
increments of 2 devices.
Table A4.12 Configuration of Data Registers and Shared Registers (for F3SP21 and F3SP25)
Item
Default Configuration Range Default Configuration Range Default Configuration Range
5120 points max. on 2 8192 points max. on 2 8192 points max. on 2
D0001 to points basis for all data D0001 to points basis for all data D0001 to points basis for all data
Data register (D) D5120 registers and shared D8192 registers and shared D8192 registers and shared
registers combined registers combined registers combined
Data register numbers: Data register numbers: Data register numbers:
Device D0001 to D5120 D0001 to D8192 D0001 to D8192
size Shared register – Shared register – Shared register
Shared relay (R) – numbers: R0001 to numbers: R0001 to numbers: R0001 to
R1024 R1024 R1024
Configurable on 2 Configurable ion 2

Extended points basis for register points basis for register
shared relay (R) – – – numbers from R1025
– numbers from R1025
to R3072 to R3072
TA040701.EPS
■ Configuring Shared and Extended Shared (R) Registers for Multiple

CPUs
Set the range of shared and extended shared registers to be used by each CPU in multi-
CPU system configuration where add-on CPU modules are installed. You can allocate a
desired number of registers to each CPU in 2 unit increments. These registers are avail-
able with the F3SP25 and F3SP35 sequence CPUs only.
CAUTION
Apply the same allocation of shared/extended shared registers to all CPUs. If the allocation
differs from CPU to CPU, shared refreshing is not performed correctly. This results in a
failure for these registers to reflect the correct results of computation.

A4-37
Shared registers
CPU 1 CPU 2 CPU 4
R0001
128 points 128 points 128 points CPU-1 shared
registers
R0129
512 points 512 points 512 units
CPU-2 shared
registers
R0641
registers
R0897
registers
Extended shared registers

CPU 1 CPU 2 CPU 4
R1025
1536 points 1536 points 1536 points
CPU-1 extended
shared registers
R2561
384 points 384 points 384 points CPU-2 extended
shared registers
R2945
shared registers
R3713
shared registers
F040705.EPS
Figure A4.24 Example of Allocating Shared/Extended Shared Registers when Four Sequence
CPUs Are Installed
CAUTION
Even if the specified range includes less than 1024 shared registers, the extended shared
registers always begin with the number R1025.

A4-38
A4.7.4 Setting Initial Data

Using the configuration function, set the initial values of data registers (D) to be used at the
start of program execution.
The data items to be configured are the data registers’ starting number and their quantity
and initial data values. After this configuration, the preset initial data values are stored in
the specified data registers when the program starts. This configuration is useful when a
large volume of initial data needs to be set by a program or when the initial data needs to
be saved. You can set initial data in a maximum of 1024 data registers.
The initial data is transferred D0001

at the start of program
execution.
Starting number =1
Quantity = 1024
D1024
D4096
F040706.EPS
Figure A4.25 Setting Initial Data

A4-39
A4.8 Special Registers (Z)

Special registers have specific functions, such as indicating the internal state of a program-
mable controller or detecting errors.
A4.8.1 Sequence Operation Status Registers

Sequence operation status registers indicate the status of sequence operation.
Table A4.13 Sequence Operation Status Registers
Type Sequence Operation Status Registers
No. Name Stored Data Description
Scan time Latest scan time Stores the latest scan time in 100-µs
Z001 (Run mode) increments.
Minimum scan time Allows the latest scan time to be read in

Z002 (Run mode) Minimum scan time 100-µs increments if it is shorter than the
minimum scan time.
Maximum scan time Allows the latest scan time to be read in
Z003 (Run mode) Maximum scan time 100-µs increments if it is longer than the
maximum scan time.
Scan time Stores the latest scan time in 100-µs
Z004 (Debug mode) Latest scan time
increments.

Z005 (Debug mode) Minimum scan time 100-µs increments if it is shorter than the
minimum scan time.
Z006 (Debug mode) Maximum scan time 100-µs increments if it is longer than the
maximum scan time.
Peripheral-process Stores the latest scan time in 100-µs
Z007 Latest scan time increments.(Tolerance: Scan time of one
scan time
control process)
Allows the latest scan time to be read in
Minimum peripheral- 100-µs increments if it is shorter than the
Z008 process scan time Minimum scan time minimum scan time.(Tolerance: Scan time
of one control process)
Maximum peripheral- 100-µs increments if it is longer than the
Z009 Maximum scan time
process scan time maximum scan time.(Tolerance: Scan
time of one control process)
TA040801.EPS
CAUTION
Do not write to a special register, including those not listed in the table above (e.g., Z010 to
Z016), unless otherwise stated. This is because they are used by the CPU module for the
system. If you inadvertently write to these registers, a failure, such as a system shutdown,
may result.

A4-40
A4.8.2 Self-diagnosis Status Registers

Self-diagnosis status registers retain the results of self-diagnosis by the sequence CPU.
Table A4.14 Self-diagnosis Status Registers
Self-diagnosis
Z017 Store the results of self-diagnosis.*
error number
Self-diagnosis error
Z018 Self-diagnosis error block number
Z019 instruction number
Instruction processing Store errors occurring during instruction

Z022 error number processing.*
Instruction Instruction processing

Z023 processing error error block number
Instruction processing
Z024 error instruction number
I/O collation error number Store detailed information on I/O collation

Z027 errors.*
I/O collation error I/O collation error

Z028 block number
I/O collation error

Store, as a bit pattern, the slot number for

which an I/O failure has occurred.
Z033: Main unit
I/O failure Z034: Subunit 1
Z033 to Z040 I/O failure 16 2 1 Z035: Subunit 2
Z036: Subunit 3
0 … 1 0 Z037: Subunit 4
Z038: Subunit 5
Z039: Subunit 6
Z040: Subunit 7
Z041 Main unit

Z042 Subunit 1
Slot number
Z043 Subunit 2
16 2 1
Z044 Subunit 3 0 … 1 0
Module recognition
Z045 Subunit 4 0: No modules are recognized.
Z046 Subunit 5 Unable to read/write.
1: Modules are recognized.
Z047 Subunit 6
Z048 Subunit 7
Z089 Main unit Slot number
Z090 Subunit 1 16 2 1
Z091 Subunit 2 0 … 1 0
Abnormal slot
Z092 insubunit Subunit 3 Fiber-optic FA-bus module
transmission line 0: Normal transmission line;
Z093 Subunit 4 Unspecified transmission line;
Z094 Subunit 5 or Loaded with the wrong module
1: Abnormal transmission line
Z095 Subunit 6 (Failure or changeover in
Z096 Subunit 7 transmission line)
* For information on error numbers (codes) to be saved in these special registers, see Table A8.2,"Details of Self-
diagnosis."
TA040802.EPS

A4-41
CAUTION
• The special registers Z041 to Z048 (Module Recognition) are only available with the
Rev.8 or later version of the F3SP21, F3SP25 and F3SP35.
• The special registers Z089 to Z096 (Abnormal Slot in Subunit Transmission Line) are
only available with the Rev.8 or later version of the F3SP21, F3SP25 and F3SP35.
SEE ALSO
more information on the Z089 to Z096 special registers (Abnormal Slot in Subunit
Transmission Line).

A4-42
A4.8.3 Utility Registers

Table A4.15 Utility Registers
Stores "year" as a BCD-coded value.
Z049 Lower-order two digits Example: 1999 as $0099
(write-enabled) of calendar year 2000 as $0000
Z050 Stores "month" as a BCD-coded value.

Month
(write-enabled) Example: January as $0001
Stores "day of month" as a BCD-coded
Z051 Day of month value.
(write-enabled) Example: 28th as $0028
Z052 Hour Stores "hour" as a BCD-coded value.

(write-enabled) Example: 10 o'clock as $0010
Clock data
Z053 Minute Stores "minute" as a BCD-coded value.
(write-enabled) Example: 15 minutes as $0015
Z054 Stores "second" as a BCD-coded value.

Second Example: 30 seconds as $0030
(write-enabled)
Stores "day of week" as a BCD-coded
Z055 Day of week
value.
($0 to $6)
Example: Wednesday as $0003
Z056 Constant scan time 0.1 ms increments

Value of constant scan time
(Note) Example: 10 ms as 100
Z057 1 ms increments
Constant scan time Value of constant scan time Example: 10 ms as 10
Z058 Scan time Value of scan time 1 ms increments

monitoring time monitoring time Example: 200 ms as 200
Note: Available with the F3SP21, F3SP25 and F3SP35 only.

TA0480803.EPS
● Follow the procedure given below to set clock data.

(1) Write the clock data to special registers Z049 to Z054. (Use a MOV P instruction. If
you use a BMOV or BSET instruction, an instruction error will be encountered.)
(2) Set special relay M172 to ON within the same scan as that in step 1 (use a DIFU
instruction, for example).
(3) Set special relay M172 to OFF in the scan subsequent to that in step 2.
Also stop writing the clock data to special registers Z049 to Z054 in that scan.
Note that no change is made to the clock data and the data reverts to its original values if
the values being set are incorrect.
● The accuracy of clock data is as follows.

Maximum monthly error: ±8 s (±2 s, when actually measured)
The clock accuracy is reset to the maximum daily error of -1.2 s/?2 s, however, when the
power is turned off and on again. In addition, it is possible to input a corrective value from
the programming tool. If you input a precise corrective value, the clock data is corrected
during the power-off-and-on sequence, thus offsetting the cumulative amount of error.

A4-43
A4.8.4 FA Link Module Status Registers

FA Link module status registers indicate the status of FA link.
SEE ALSO
Special relays/registers sections in FA Link Module F3LP02-0N Fiber-optic FA Link Module

F3LP12-0N (IM34M5H43-01E) for more information on the FA link module status registers.
Table A4.16 FA Link Module Status Registers

0: Under initialization
Z065 Local station status 1: Offline FA link 1
2: Online
Cyclictransmission FA link 1
Z066 time 1 ms increments
2: Online
Z257 (Note) Local station status 1: Offline FA link 3
2: Online
Z258 (Note) time 1 ms increments
2: Online
2: Online
2: Online
2: Online
2: Online
Note: Available with the F3SP25 and F3SP35 only.

TA040804.EPS

A4-44
A4.8.5 CPU Module Status Registers

CPU module status registers indicate the status of a CPU.
Table A4.17 CPU Module Status Registers

See Section A6.14, "User Log
Z105 Number of stored Management Function," for information on
user logs user logs.
TA040805.EPS

A4-45
A4.9 Index Registers (V)

Index registers are used to apply index modification to devices.
You can use these registers for both basic instructions and advanced instructions to make
index modifications.
Use these registers when specifying a device number by adding the content of an index
register to a device whose number is directly specified in an instruction.
SEE ALSO
Section 1.7, “Index Modification,” in the instruction manual (IM34M6P12-03E), Sequence

CPU - Instructions, for more information on the index registers.
X00502
MOV 100 V01
I0001 X00502 Y00601
V01
X00503 X00504 V01 V02
MOV D0001 D0100
X00501 T001 Y00602
X00503
I(0001+100)=I0101 D(0001+100)=D0101
F040901.EPS
Figure A4.26 Index Registers
CAUTION
Examination of whether or not the device number specified using an index register exceeds
the given configuration range, is not performed on the system side of the sequence CPU
module. The configuration range may be exceeded depending on the content of the index
register used, resulting in the selection of the wrong device. Be careful when specifying the
device number.

A4-46
A4.10 File Registers (B) F3SP25

F3SP35
File registers are used as extensions of data registers. Each file register has 16 bits.
Like data registers, you can read from or write to file registers in 16-bit or 32-bit increments
in programs using advanced instructions. Note that advanced instructions that contain any
file register are excluded from high-speed processing.
TIP
It is recommended that the values of file registers be transferred to data registers first and
then advanced instructions containing these data registers be executed, rather than directly
executing advanced instructions containing the file registers. This is because this strategy
makes the instruction execution time shorter.
X00502
MOV B00001 D0001
MOV 1 B00002
X00501 X00502 Y00601
X00503 X00504
MOV B00003 D0003
B00002 = B00002 + 1
F041001.EPS
Figure A4.27 File Registers
Unlike data registers, all file registers retain computation results when the power is turned
off. The file registers are cleared to OFF (0) when you write the data value OFF (0) to the
file registers from the programming tool. Unlike data registers, the file registers are not
cleared to OFF (0) even if you:
• send a device clearance command from the programming tool; or
• send a memory clearance command from the programming tool.

A5-1
A5. Programs
This chapter describes languages used for programming, program types, and program
memory.
A5.1 Programming Language

Two types of programming language are available: structured ladder language and
mnemonic language. In either case, the written program is read sequentially by the
sequence CPU to perform computations according to the program’s process details.
A5.1.1 Structured Ladder Language

The structured ladder language is based on relay symbol representation and allows the
programmer to do structured programming by breaking a program into functional parts.
The programmer can perform programming on

a function-by-function basis. Function 1
➤
➤
X00501
I0001 T001
I0001
TIM T010 10ms
I0001 T001 I0002
Function n
➤
➤
X00502
CNT C001 100
X00501 I0016
C001 X00504 Y00602
X00501 T001 Y00601
X00503
F050101.EPS
Figure A5.1 Structured Ladder Language

A5-2
A5.1.2 Mnemonic Language

The mnemonic language is designed to describe a program by breaking its process details
into instruction, source and destination sections. Like the structured ladder language, the
mnemonic language allows the programmer to perform programming on a function-by-
function basis.
Instruction section
LD I0001
OUT Y00602
LD X00501
AND X00502
MOV D0001 , D0002
Instruction section Source section Destination section

F050102.EPS
Figure A5.2 Mnemonic Language

A5-3
A5.2 Program Types and Configuration

Two types of programs are available: blocks and executable programs.
A5.2.1 Blocks and Executable Programs
■ Blocks
A block refers to a set of circuits entered through the programming tool.
Parts of each program written on a function-by-function basis using the structured ladder
language or mnemonic language are managed as blocks. Since the program can be
maintained or reused block by block, program development becomes extremely easy. A
single block can contain steps up to 10 K.
CAUTION
It is not possible for the CPU to execute a separate block.
Block 1 Circuit
X00503 X00504 Y00602
X00501 X00502 Y00601
X00503
Block n
I0001 Y00602
X00501 X00502 I0003
F050201.EPS
Figure A5.3 Blocks

A5-4
■ Executable Programs
An executable program refers to a program with a format which can be executed by the
CPU. The executable program is composed of a combination of multiple blocks created
with a programming tool. Each type of sequence CPU has its own maximum number of
blocks, as noted below.
F3SP21: 32
F3SP25: 128
F3SP35: 1024
Since you can execute only specific blocks of an executable program, it becomes easy for
you to control and manage your programs.
Block 1 Circuit
X00503 X00504 Y00602
Executable
X00501 X00502 Y00601 program
X00503 Block 1
Block 2
Block 16
I0001 Y00602
X00501 X00502 I0003

Block 16
F050202.EPS
Figure A5.4 Example of an Executable Program

A5-5
A5.2.2 Programs Composing an Executable Program

Programs that compose an executable program are classified into main routine programs,
subroutine programs and interrupt programs, according to their functions.
Main routine program
Block 1
Subroutine program

Block 2
Subroutine program
Executable
program
Block n
Subroutine program
Interrupt program
F050203.EPS
Figure A5.5 Programs Composing an Executable Program

A5-6
■ Main Routine Programs
A main routine program is always executed in each scan. Since the main routine program
is written in the structured ladder language, it is composed of multiple blocks.
You can execute a main routine program by either executing all blocks of the program or
executing only specific blocks.
Program
execution
Block 1
SUB This subroutine
program is
excluded from
the execution.
RET
Block n-1
Block n
F050204.EPS
Figure A5.6 The Way a Main Routine Program Is Executed

A5-7
■ Subroutine Programs
A subroutine program is executed when a CALL instruction is given by a main routine
program. Use this program when you want to run a specific process two or more times
within one scan. A subroutine program can be placed in any location in a block.
In a case where the operation mode in which only specific blocks are executed is selected,
a subroutine program is executed even if it is located in a yet-to-be-executed block and
called from a block being executed.
Subroutine programs can be nested to a maximum depth of eight layers (nesting means to
call a subroutine from within another subroutine).
Program Program
execution execution
CALL
Block 1
Block n-1
SUB
Block n
RET
Subroutine program
F050205.EPS
Figure A5.7 The Way a Subroutine Program Is Executed

A5-8
■ Interrupt Programs
An interrupt program is executed when any cause of interrupt occurs. A maximum of four
interrupt programs can be included in a block.
The relationship between a cause of interrupt and an interrupt program is described as a
parameter of an INTP instruction.
INTP X00301
F050206.EPS
Figure A5.8 INTP Instruction
Program Program
execution execution
Interrupt
Block 1 processing
Block n-1
INTP
Block n
IRET
Interrupt program
F050207.EPS
Figure A5.8 The Way an Interrupt Program Is Executed

A5-9
A5.3 Program Memory

Program memory contains programs as well as information required for their operation and
management. This section describes the configuration of the program memory and its
initial condition when there are no programs in it.
Table A5.1 Configuration of Program Memory and Its Initial Condition
Memory Component Description Initial Condition

An area for storing information required to Stays in the default state of program manage-
manage the entire range of programs, such ment, where the program name is "PROGRAM,"
Program management table as program names, the number of steps, and block name is "PROGRAM," and the number of
information on block management. steps is "0."
Program An area for storing programs. Contains a NOP instruction.
An area for storing configuration information, Contains the defaults discussed in subsection
Configuration table*
such as device sizes and operation methods. A1.2.3, "Configuration."
An area for storing configuration information Contains the defaults discussed in subsection
I/O configuration table* such as output settings, in case the se- A1.2.3, "Configuration."
quence stops and for I/O module settings.
An area for storing the information required

Contains "0," indicating there are no such program
to control the execution of program instruc-
Program control instructions table control instructions as a JMP instruction or a sub-
tions, such as a JMP instruction and a sub-
routine instruction.
routine instruction.
An area for storing timer and counter set- Contains "0," indicating there are neither timers
Timer/counter settings table points. nor counters.
An area for storing such information as circuit

Utility comments and sub-comments. Contains "0."
* See subsection A1.2.3, "Configuration," for more information.

TA050301.EPS
CAUTION
No programs can be executed when the program memory is in its initial condition.

A5-10
Configuration of program memory
Program management table
Programs
F3SP21: 10 K (10240) steps
Program F3SP25: 20 K (20480) steps
F3SP35: 100 K (102400) steps
Range of devices
Configuration table Error-mode operation
Range of devices latched at power failure
RAM
Setting as to whether or not data is retained
I/O configuration table Setting of sampling interval
Setting of data codes
Jump Interrupt definition
Program control instructions table Subroutine
Label
Timer/counter settings table
Circuit comments, sub-comments,

Utility registration tables, etc.
FA050301.EPS
Figure A5.9 Configuration of Program Memory

A6-1
A6. Functions
This chapter describes functions which can be executed by the CPU module, such
as the execution of specified blocks and debugging operation.
A6.1 Function List

The following tables summarize the functions provided by the sequence CPU.
Table A6.1 Functions Provided by the Sequence CPU
Sequence CPU Function Function Overview Page
Operation setup function Specifies the operation mode of the CPU and its actions. A6-3
Constant scan Executes a sequence program at certain time intervals. A6-5
Specifies how an executable program is processed.Specified A6-6
Execution of all blocks/specified blocks blocks are executed using ACT and INACT instructions.
Debugging function Supports debugging operations, such as forced set/reset. A6-13
Protects programs by means of password.This function has two
Program protection function A6-17
modes: executable program protection and block protection.
Makes on-line modifications or changes to a program in the

Online edit function A6-19
program memory of the CPU.
Acquires and displays states of multiple devices for up to 1024
Sampling trace function (*1) A6-27
scans.
Performs the same level of communication as that of a personal
Personal computer link function (*2) computer link module, when a personal computer or a monitor is A6-31
connected to the programming tool port.
Macro instruction function (*1) Allows the user to create and register new, customized A6-48
instructions.
*1 Available with the F3SP25 and F3SP35 only.

*2 Available with the F3SP21, F3SP25 and F3SP35 only.
TA060101.EPS
Table A6.2 ROM Management (Writer) Function

ROM Management (Writer) Function Function Overview Page
File-to-ROM transfer function Writes programs or data to the ROM. A6-25
CPU-to-ROM transfer Writes a program or data to the ROM. A6-25
(ROM copy) function
Cross-checks the ROM data with the details of programs in the
File/ROM cross-check function A6-25
programming tool*.
ROM clearing function Erases the ROM data. A6-25
* Refers to either the FA-M3 Programming Tool WideField or Ladder Diagram Support Program M3.
TA060102.EPS

A6-2
Table A6.3 Device Management Functions (F3SP21, F3SP25 and F3SP35 only)
ROM Management (Writer) Function Function Overview Page
Reads device information from the CPU module and saves it to a
Device upload function A6-47
file in the programming tool*.
Reads device information from a file in the programming tool*
Device download function A6-47
and writes it to the CPU module.
Device edit function Edits device information saved in a file in the programming tool*. A6-47
Cross-checks device information saved in the CPU module with

Device cross-check function that saved in a file in the programming tool*. A6-47
* Refers to either the FA-M3 Programming Tool WideField or Ladder Diagram Support Program M3.
TA060103.EPS

A6-3
A6.2 Operation Setup Function

The operation setup function sets up the CPU operation mode and initializes programs and
devices. This function can be used by entering a command from the programming tool,
personal computer link module, or an add-on CPU.
■ Run Mode
The CPU begins running a program from its first instruction, similar to when the power is
turned on. When the power is turned on or the mode is changed from “stop” to “run,” the
CPU sets all devices to 0, except for latching-type devices, before executing the program.
When the CPU enters the Run mode, functions available only in the Debug or Stop mode
are disabled.
■ Debug Mode
The CPU begins running a program from its first instruction, similar to when the power is
turned on. When the power is turned on or the mode is changed from “Stop” to “Debug,” the
CPU sets all devices to 0, except for latching-type devices, before executing the program.
Be sure to disable the Debug mode and enter the Run mode when you have completed
your debugging and tuning tasks.
■ Stop Mode
The CPU stops running the program. External output data is retained (ON) or not retained
(OFF), depending on the settings of the configuration item “external output to be retained in
case of sequence stop.” This mode does not work when the CPU has already stopped
running the program.
■ Clearing Memory Stop
This function deletes a program or programs and sets all devices to 0. Stop running the
program before using this function.
■ Clearing Devices Stop
This function sets all latching-type devices, excluding file registers for the F3SP25 and
F3SP35, to 0. Stop running the program before using this function. To clear file registers,
use the device edit function of the device management function to set all the file register
data to 0 and write the data to the CPU module using the device write function.
See Also
For details on the device management function, see Section A6.12, “Device Management
Function.”

A6-4
CAUTION
The following are precautions you should follow when using the functions described in this
chapter:
• Some functions are not available in all the operation modes.
Note that the following marks are used when explaining each function, in order to
indicate that the function in question is available in the cited mode or modes.
Run , Debug and Stop
Unless otherwise specified, the function can be used in any operation mode.
• The scan time may become longer for some functions.
When you finish using such a function, be sure to disable it before running the system.
Be especially careful when using any function that works in Debug mode. When your
debugging and tuning tasks are complete, always disable the function and enter Run
mode.
• Be sure to use the ROM writer functions when you operate the ROM pack.
Note that the following mark is used when explaining each ROM writer function to
indicate that the function is available in ROM Writer mode.
ROM writer

A6-5
A6.3 Constant Scan Run Debug
The constant scan function executes a program repeatedly at specified time intervals. You
can set the constant scan time, i.e., constant-scan time interval, to a value from 1 ms to 190
ms in 0.1 ms increments. To do this, use the configuration function.
0 step END 0 step END 0 step END

instruction instruction instruction
3ms 5ms 2ms
10ms 10ms 10ms
FA060201.EPS
Figure A6.1 Operation Based on 10-ms Constant Scan
If the scan time of a sequence program is longer than the preset constant scan time, any
constant scan is ignored and the program is executed with its own scan time.
END
END instruction END
0 step instruction 0 step 0 step instruction 0 step
1ms 3ms 1ms
2ms 3ms 2ms

Scan time for a program
FA060202.EPS
Figure A6.2 Operation Based on 2-ms Constant Scan
A6.3.1 Setting the Constant Scan Time

Set the constant scan time using the configuration item “operation control” of the WideField
or Ladder Diagram Support Program M3. You can set the constant scan time to a value
from 1 ms and 190 ms in 0.1-ms increments (only available with the F3SP21, F3SP25 or
F3SP35). If you will not use the constant scan time, set the constant scan function to the
option “0” (default).
CAUTION
• The constant scan time must be shorter than the scan time monitoring time.
• If the constant scan time is longer than the scan time monitoring time, a scan timeout
error occurs.

A6-6
A6.4 Executing All Blocks/Specified Blocks Run Debug
Select the method of executing a program — executing either all blocks or specified blocks,
using the configuration item “operation control.”
A6.4.1 Executing All Blocks

This method always executes all blocks of an executable program sequentially from block 1.
The program execution method defaults to the option “all blocks are executed.”
All blocks are executed.

Executable program
Block 1
I0001 Y00602
X00501 X00502 I0003
Block n
X00503 I0002 Y00603
X00501 X00502 I0004
I0003
FA060301.EPS
Figure A6.3 Execution of All Blocks

A6-7
A6.4.2 Executing Specified Blocks

This method uses ACT/INACT instructions to control blocks of an executable program so
that only the specified blocks are executed.
This allows you to control blocks which are programmed for each function. Thus, you can
easily know how the blocks are controlled.
Enabled blocks are referred to as “blocks in an ACTIVE state,” while disabled blocks are
called “blocks in an INACTIVE state.” Use an ACT instruction to set a block in an ACTIVE
state and an INACT instruction to set the block in an INACTIVE state. Whether a block is in
an ACTIVE or INACTIVE state is indicated by a special relay, according to the following
relationship between special relay numbers and block numbers.
• M0001 to M0032: Blocks 1 to 32 (for F3SP21)
(Note that special relays M0001 to M0032 contain the same values as special relays
M2001 to M2032.)
A special relay is set to “1” when the corresponding block is in an “ACTIVE” state, and “0”
when the block is in an “INACTIVE” state. This means the two states can be handled in a
program.
ACTIVE-state blocks are executed in ascending order of their block numbers. By default,
only block 1 is in an ACTIVE state. To determine whether all blocks or specified blocks are
executed, use the configuration function.
Executable program Block 1

ACTIVE state
Block 1 I0001 Y00602
Function 1 Special relay
M001=1
X00501 X00502 I0003
Block 2
Function 2 INACTIVE state
Special relay
M002=0
Block m
ACTIVE state X00503 Y00603
Block m
Function m Special relay
M00m=1
X00501 X00502 I0004
Block n
Function n INACTIVE state I0003
Special relay
M00n=0
FA60302.EPS
Figure A6.4 Execution of Specified Blocks-Executing block 1 and block m only

A6-8
A6.4.3 Operation when Specified Blocks Are Enabled

Blocks that have been enabled with an ACT instruction are initialized at the end of the
scan in which they were enabled. It is from the next scan that the blocks enabled with an
ACT instruction actually start.
nth scan
Executable program Block 1 Special relay

Function 1 M2001=1
Block 1 ACT
Function 1
ACT Block 2
Block 2 Next scan

Function 2
(n + 1)-th scan
Block m
Function m
Block 1 Special relay
Function 1 M2001=1
Block n
Function n Next scan

Function 2 M2002=1
Executable program
ACT Block m
Block 1
Function 1 Next scan
(n + 2)-th scan
Block 2 ACT
Function 2
Block m Function 1 M2001=1
Function m
Block n
Function n Block 2 Special relay
Function 2 M2002=1
Block m Special relay

Function m M200m=1
FA060303.EPS
Figure A6.5 Operation when Specified Blocks Are Enabled

A6-9
Devices that are specified in the blocks enabled with an ACT instruction are placed in the
following conditions by block initialization.
Table A6.4 Conditions when Blocks Are Enabled
Device Condition when Blocks Are Enabled
Timer Resets.
Continuous timer Retains the value it held before the blocks are enabled.
Counter Retains the value it held before the blocks are enabled.
Destination of OUT instruction Goes into an OFF state.
All other devices Retain the states they held before the blocks are enabled.
TA060301.EPS
Use a SET instruction for devices whose output values need to be retained when blocks
are enabled.
This device is set to OFF.
X00503 I0002 Y00603
X00501 X00502 I0004
I0003
X00301 I0005
SET Y00601
I0004
Use a SET instruction to retain the output value of this device.

FA060304.EPS
Figure A6.6 Example of Devices Initialized When Blocks Are Enabled

A6-10
A6.4.4 Operation when Specified Blocks Are Disabled

Blocks that have been disabled with an INACT instruction are initialized at the end of the
scan in which they were disabled. It is in the next scan that the blocks disabled with an
INACT instruction actually stop.
nth scan
Executable program Block 1 Special relay

Function 1 M2001=1
Block 1 INACT
Function 1
INACT: Block 2
Block 2 Block 2 Special relay

Function 2 Function 2 M2002=1
Block m
Function m
Function m M200m=1
Block n
Function n

Function 2 M2002=0
Executable program
Block 1 INACT
Function 1 Next scan
(n+1)th scan
Block 2
Function 2
Block m Function 1 M2001=1
Function m
INACT: Block m
Block n
Function n Block n Special relay
Function n M200m=1

Function m M200m=0
Next scan
(n+2)th scan

Function 1 M2001=1
F060403.EPS
Figure A6.7 Operation When Specified Blocks Are Disabled

A6-11
Devices that are specified in the blocks disabled with an INACT instruction are placed in the
following conditions by block initialization.
Table A6.5 Conditions when Blocks Are Disabled
Device Condition when Blocks Are Enabled
Timer Resets.
Continuous timer Retains the value it held before the blocks are enabled.
Counter Retains the value it held before the blocks are enabled.
Destination of OUT instruction Goes into an OFF state.
All other devices Retain the states they held before the blocks are enabled.
TA060302.EPS
Use a SET instruction for devices whose output values need to be retained when blocks
are disabled.
This device is set to OFF.
X00503 I0002 Y00603
X00501 X00502 I0004
I0003
X00301 I0005
SET Y00601
I0004
Use a SET instruction to retain the output value of this device.

FA060306.EPS
Figure A6.8 Example of Devices Initialized When Blocks Are Disabled
A6.4.5 Operation When Specified Blocks Are Executed

● Example Where Each Block Controls the Block to Be Enabled Next Time
Block 1
Condition
ACT BLOCK 2
INACT BLOCK 1
Block 1
Block 2
Condition Condition
ACT BLOCK m
Block 2
INACT BLOCK 2
Condition
Block m
Block m
Condition
ACT BLOCK 1
INACT BLOCK m
FA060307.EPS
Figure A6.9 Example Where Each Block Controls the Block to Be Enabled Next Time

A6-12
● Example Where Blocks to Be Enabled Are Controlled by Creating Sched-
uler
Block 1
Condition
ACT BLOCK 2
INACT BLOCK n
Condition
Block 1
ACT BLOCK 3
INACT BLOCK 2
Condition
ACT BLOCK 1
ACT BLOCK m
INACT BLOCK 3
Condition
ACT BLOCK n
Condition
INACT BLOCK 1
INACT BLOCK m
Block 2
Condition
Block 3
Condition
Block 1 Block m
Condition Condition
Block n
Condition
F060408.EPS
Figure A6.10 Example Where Blocks to Be Enabled Are Controlled by Creating Scheduler
Create a scheduler for block 1 which is initially in an ACTIVE state.

A6-13
A6.5 Debugging Functions
A6.5.1 Step Operation Debug
Step operation executes only one instruction at a time as dictated by a specified instruction
number. After completing the instruction, the CPU goes into a Pause state and stops
program execution. Use the programming tool to specify the instruction number.
I0001 Y00602
X00501 X00502 I0003
X00503 I0002 Y00603
One instruction is executed. FA060401.EPS
Figure A6.11 Step Operation
CAUTION
The clock data of both timers and special relays are updated only when the CPU is execut-
ing a program during step operation. That is, the CPU does not update the data when in a
Pause state.
Step operation is ignored if such a control instruction as JMP or CALL is executed. The
CPU resumes normal instruction execution from the instruction to which control has been
passed.
An instruction which I0001 Y00602

is to be suspended
next X00501
JMP LBL 1
X00503 I0002 Y00603
X00501 X00502 I0004

LBL 1
The instruction execution I0003 An instruction is
control moves here. executed normally.
FA060402.EPS
Figure A6.12 Step Operation when a JMP (or CALL) Instruction Is Executed
If the CPU is paused due to a control instruction, you can re-input the jump destination of
the control instruction as the start-of-step-operation instruction number, in order to continue
step operation.

A6-14
I0001 Y00602
X00501
JMP LBL 1
Suspended state
X00503 I0002 Y00603
Enter the instruction

number again.
X00501 X00502 I0004
LBL 1
I0003
FA060403.EPS
Figure A6.13 Continuation of Step Operation from where the CPU is Paused Due to Control
Instruction
A6.5.2 Scan Operation Debug

Scan operation causes the CPU to stop at the first instruction part of an executable pro-
gram when the specified condition, which is shown below, becomes true. The CPU goes
into a Pause state and stops program execution.
● Specified Condition
Off-to-on transition of specified bit
On-to-off transition of specified bit
For this condition, use one of the bit devices with the codes X, Y, I, E, L, T, C and M.
Program execution Specified condition is met?

YES
stops
(Suspended state)
NO
I0001 Y00602
X00501 X00502 I0003
X00503 I0002 Y00603
X00501 X00502 I0004
I0003
FA060405.EPS
Figure A6.14 Scan Operation
CAUTION
The clock data of both timers and special relays are updated only when the CPU is execut-
ing a program during scan operation. That is, the CPU does not update the data when in a
Pause state.

A6-15
CAUTION
Scan operation is only possible with Ladder Diagram Support Program M3, and is not
possible with WideField.
A6.5.3 Partial Operation Debug

Partial operation executes only a specific range of instructions defined by the starting and
ending instruction numbers. Use a programming tool to specify the starting and ending
numbers. This mode of operation is used when only part of program performance needs to
be verified.
Start instruction number

I0001 Y00602
X00501 X00502 I0003
X00503 I0002 Y00603
X00501 X00502 I0004
I0003
End instruction number
Only this part of a
program is executed. FA060406.EPS
Figure A6.15 Partial Operation
CAUTION
Partial operation is only possible with Ladder Diagram Support Program M3, and is not
possible with WideField.
A6.5.4 Forced SET/RESET Debug Stop
A forced SET/RESET instruction forcibly sets a specified bit device to ON/OFF, regardless
of program execution. You can use the instruction for a maximum of 32 bit devices of all
types combined. Only bit devices are supported, i.e., X, Y, I, E, L, T and C devices.
If a forced SET instruction is applied to a timer (T) or a counter (C), the timer expires or the
counter terminates.
A forced SET/RESET instruction remains valid until you:
• disable the instruction,
• change the operation mode to RUN, or
• turn off the power.

A6-16
A6.5.5 Changing Setpoints, Current Values and Data Values

Debug Stop
• Changing Setpoints
You can change the setpoints of timers and counters.
• Changing Current Values

You can change the current values of timers and counters.
If you set a current value of “0,” a timer expires and a counter terminates.
• Changing Word or Long-word Data Values

You can change the data values of word devices other than timers and counters, such as
data registers. If you select bit devices such as internal relays instead, data values included
in the change are those of 16 or 32 bits’ worth of devices, beginning with the first device
address.
A6.5.6 Stopping Refreshing Debug

You can prevent X/Y relays for external devices, link relays/registers for FA links, and
shared relays/registers for add-on CPUs, from being refreshed by the results of program
execution. This allows you to visually check I/O data on the monitor.
In the case of X/Y relays for external devices, you can stop refreshing X input relays and Y
output relays separately.
X00502 Y00602
X00501 X00502 Y00601
X00503 X00504 Y00603
X00501 X00502 Y00604
X00503
Computation
results
Data memory in the CPU
Output relay (Y) area External output device
Output refresh is disabled.

FA060407.EPS
Figure A6.16 Stop of Output Refreshing

A6-17
A6.6 Protecting Programs

For security reasons, you can protect your programs from being referenced. There are two
modes of protection: executable program protection and block protection. Protection is
achieved by entering a password with the setup tool. A password must consist of eight
alphanumeric characters, beginning with a letter. The protection information is saved in an
executable program or block by the setup tool.
CAUTION
Program protection is designed to prevent unauthorized references only. It is not effective
against deleting programs or changing CPU operations due to erroneous operations or
writing.
A6.6.1 Executable Program Protection

Executable program protection protects the entire executable program. When this protec-
tion mode is selected, all functions that act upon an executable program (e.g., downloading,
uploading, monitoring and online editing) are disabled.
X00503 X00504 Y00602

Personal
computer X00501 X00502 Y00601
X00503
Monitoring, debugging operation, printout

Upload Download
FA060501.EPS
Figure A6.17 Executable Program Protection
When executable program protection is selected, the following functions are disabled:
Downloading, uploading, monitoring (circuit diagram monitoring, debugging
operation, changing timer/counter setpoints, online editing), ROM writer functions,
and printing.

A6-18
A6.6.2 Block Protection

Block protection protects programs on a block-by-block basis. This protection mode is
designed to prevent unauthorized references only. In addition, only specified blocks are
included in the protection. When block protection is selected for a block, its circuit diagrams
and instructions are not displayed on the programming tool.
Block n
X00503 X00504 Y00602

Personal
computer
Block m
X00501 X00502 Y00601
X00503
The protection has the effect

only on specified blocks
FA060502.EPS
Figure A6.18 Block Protection
When block protection is selected, the following functions are disabled:

Monitoring (circuit diagram monitoring, debugging operation, changing timer/
counter setpoints, online edit) and printing

A6-19
A6.7 Online Editing Debug Stop
Online editing allows you to make modifications or additions to your program when the
program is being executed. This function is useful when you make minor changes to the
program during a debugging or tuning task. Modifications/changes made to the program
are reflected in the CPU program memory at the end of a given scan.
Addition I0001 Y00602
X00501 X00502 I0003
X00503 I0002 Y00603
X00501 X00502 I0004
I0003
CPU program memory
The addition is reflected

at the end of a given scan.
FA060801.EPS
Figure A6.19 Online Editing
WARNING
Do not perform online editing when the machinery under control is being operated.
CAUTION
• You are not allowed to modify the following instructions and circuits:
• SUB and RET instructions and circuits that contain any of these instructions.
• INTP and IRET instructions and circuits that contain any of these instructions.
• Be careful about CPU operation when your modifications/additions span
multiple circuits.
Modifications/additions are reflected in a program for only one circuit at a time during
each scan. This means you will need as many scans as the number of circuits being
updated to include the modifications/additions. Be careful with CPU operation until all
these scans are completed.
• Online editing affects the scan time.
Modifications/additions are reflected in a program in synchronization with program
execution. This means online editing lengthens the scan time.
The message “CPU being optimized” appears at the end of online editing performed
using the programming tool. The time interval during which the message is on display
is equivalent to one scan and is far longer than a normal scan time. For this reason it
is not possible to refresh data for exchange with external devices or communicate with
them.

A6-20
A6.8 Making Programs Resident Using ROM Writer

Functions
A6.8.1 Making Programs Resident in ROM
Programs that have been debugged and tuned can be made resident in ROM. To make a
program resident in ROM, transfer the program to the ROM pack using the ROM writer
functions of the CPU.
The items to be made resident in ROM are programs themselves, as well as program
management information, configuration information, control tables, timer/counter setpoint
tables, and comment management information. At power-on, all pieces of information
necessary for the CPU to start program execution are allowed to become resident in ROM.
Available ROM packs are limited by the number of program steps, the number of circuits/
sub-comment lines, and/or the number of timers/counters, as shown below.
Table A6.6 Limitations on Selection of ROM pack
ROM pack Model RK10-ON RK30-ON,RK33-ON RK50-ON,RK53-ON
When F3SP21 is used 5K steps*1 10 K steps 10 K steps
When F3SP25 is used Unusable. 20 K steps 20 K steps
When F3SP35 is used Unusable. 20 K steps*2*3 100 K steps*4
*1 Can support a maximum of 400 lines of circuit comments and sub-comments combined.
*2 Can store a maximum of 2048 units of timers and counters combined.
*3 Can store a maximum of 128 program blocks.
*4 Can store a maximum of 80 K steps for each program when there are 33 or more program blocks
TA060901.EPS

A6-21
With the configuration function, you can make the following two types of data resident in
ROM. These types of data are used to set initial values to be used by a program.
• Setpoints of 1,024 data registers’ worth of default data
• Either 32768 data registers’ or file registers’ worth of current values within CPU
module-see subsection A6.8.2, “Setting Devices’ Current Values to Be Made Resident
in ROM.”
At power-on, data read from the ROM pack is stored in data registers or file registers
specified with the configuration function. Data registers and file registers included in the
data retention in case of power failure revert to their respective default values. If you edit
both of the configuration items mentioned above for the same data register, only the
setpoint of the second configuration item “Setting Devices’ Current Values” is effective.
TIP
Data retention in case of power failure is effective for devices not included in the configura-
tion discussed above.
Making the initial setpoints of data registers resident in ROM is only possible when Model
RK30-0N, RK33-0N, RK50-0N or RK53-0N is selected as the ROM pack. Similarly, making
the current values of data registers or file registers resident in ROM is only possible when
Model RK50-0N or RK53-0N is selected as the ROM pack.
If you perform both types of configuration mentioned above for the same data register, only
the current value set by the latter type of configuration is effective.
TIP
Data retention in case of power failure is effective for devices not included in the configura-
tion discussed above.
Program RAM configuration Program ROM configuration

Program management table Program management table
Program program Program

The program size is limited.
Configuration table Device range Configuration table

Operation methods in case of an error
Data lock-up ranges at a power failure
I/O configuration table Lock-up/Not-lock-up type settings I/O configuration table

RAM Sampling cycles ROM
Data code type block
Program control instruction Jump Interrupt definitions Program control instruction

table Subroutines table
Labels
Timer/counter set value Timers and counters Timer/counter set value

table table
Utility Circuit comments, sub-comments or Utility

other information
The data sizes are limited.
FA060901.EPS
Figure A6.20 Contents of Program to Be Made Resident in ROM

A6-22
CAUTION
Be sure to debug and tune programs before making them resident in ROM. You cannot edit
or carry out partial modification of a program or data that has already been made resident
in ROM. Programs made resident in ROM can only be executed on a CPU module whose
“model name” has been transferred to the ROM pack.

A6-23
A6.8.2 Setting Devices’ Current Values to Be Made Resident in

ROM F3SP21
F3SP25
F3SP35
Define initial values to be made resident in data registers (D) or file registers (B) when
program execution begins. This definition is effective only when Model RK50-0N or RK53-
0N is selected as the ROM pack.
The data items to be defined are the type of device, starting number, and quantity of de-
vices. This configuration enables the current values of the specified devices to be stored in
the ROM pack when the “file-to-ROM transfer” or “CPU-to-ROM transfer (ROM copy)”
function of the ROM writer functions is executed. You can determine whether or not to
update the device data to be made resident in ROM with the current values when executing
the “file-to-ROM transfer” or “CPU-to-ROM transfer” function. When program execution
begins, the device data in the ROM pack is read and stored in the specified devices. This
configuration is useful when you want to set a large volume of initial data or save initial data
for a program. You can set initial values in a maximum of 5120 data registers for the
F3SP21 sequence CPU or a maximum of 32768 file registers for the F3SP25/F3SP35
sequence CPUs.

A6-24
A6.8.3 ROM Writer Functions and ROM Writer Mode ROM writer
The sequence CPU or an add-on sequence CPU can be operated by reading a program
stored in the ROM pack. In the FA-M3, you can achieve the same functions as those of a
commercially available ROM writer, such as writing a program to the ROM pack, by using
the sequence CPU or add-on sequence CPU. These functions are called the ROM writer
functions and include file-to-ROM transfer, CPU-to-ROM transfer, and file/ROM cross-
check. The ROM writer functions work in a dedicated mode different from the normal
operation mode of the sequence CPU. This dedicated mode is called the ROM Writer
mode. The ROM Writer mode is maintained even when you turn on or off the power. At
power-on, no programs are read from the ROM pack.
If you want to write any single program to multiple ROM packs, simply transfer the program
to the program memory only once. Then, change the ROM packs one by one.
CAUTION
In ROM Writer mode, a program in the program memory of the sequence CPU is retained.
It is also possible to write a debugged and/or tuned program directly to the ROM pack
without retaining it in the program memory.
Sequence CPU
Personal
computer Program memory
ROM pack
Transfer
Write
Read
ROM Writer mode

FA060902.EPS
Figure A6.22 ROM Writer Functions and ROM Writer Mode

A6-25
Using the ROM writer functions, you can save a debugged and/or tuned program to the
ROM pack. To transfer the program to the ROM pack, use the ROM management function
of the programming tool. The following details the ROM writer functions.
■ File-to-ROM Transfer Function

This function writes a program or data to ROM.
It first transfers a program to the CPU’s program memory, and then writes the program to
ROM. At this point, you can determine whether or not to make the current values of de-
vices resident in ROM (for the F3SP21, F3SP25 and F3SP35 only).
■ CPU-to-ROM Transfer (ROM Copy) Function

This function writes a program or data in the CPU directly to the ROM without transferring it
using the ROM management function of the programming tool. At this point, you can
determine whether or not to make the current values of devices resident in ROM.
A debugged and/or tuned program or data in the CPU is not initialized when the CPU is
changed to the ROM Writer mode. It is therefore possible to write the program or data
directly to ROM. This function is also used to write the same program to multiple ROM
packs. You can write the program to all of the ROM packs by simply changing the ROM
packs one after another. There is no need to transfer the program repeatedly.
■ File/ROM Cross-check Function

This function cross checks the content of ROM with that of a program in WideField or
Ladder Diagram Support Program M3.
■ ROM Clearance Function

This function erases the content of a ROM.
CAUTION
• Change the CPU to ROM Writer mode before using the ROM writer functions. You
cannot use the ROM writer functions in other modes.
• Be sure to disable ROM Writer mode when you finish using the ROM writer functions.
The CPU does not execute any sequencing functions if ROM Writer mode remains
active.

A6-26
A6.9 Exclusive Access Right

An exclusive access right is used to prevent a program, operation mode, or device data
from being changed or prohibit the program or device data from being downloaded by other
users when the program is being executed or debugged. Once you acquire the exclusive
access right, all alteration- and control-related commands entered from other tools, CPU
modules or personal computer links are rejected until you release the right.
If you withhold the exclusive access right, all alteration- and control-related commands from
other users remain disabled. Release the access right as soon as you have completed the
required process.
If another user has already acquired the exclusive access right, it is not available to you.
The exclusive access right is handled in the following three modes:
● Acquisition
This mode acquires the exclusive access right.
● Release
This mode releases the exclusive access right.
● Forced Release
This mode permits you to forcibly release the exclusive access right from the CPU holding
the right through access from a tool or module having no access right.
Personal
computer
Obtains the exclusive access right. Has no access.

Personal computer link
Sequence CPU module

FA061001.eps
Figure A6.22 Exclusive Access Right
Once the exclusive access right is acquired, the system prohibits the following acts from
being performed by a tool or module having no access right:
CPU operation, CPU stop, debugging, downloading, debugging operation, use of
debugging functions, writing to devices, and change in timer/counter setpoints.

A6-27
A6.10 Sampling Trace Function F3SP25

F3SP35
The sampling trace function sequentially stores the states and contents of devices selected
for sampling, in the sampling trace memory of the sequence CPU.
The sampling trace function has three sampling modes:
• TRC-instruction sampling
• End-of-scan sampling
• Fixed-interval sampling
As the condition for triggering sampling, you can define the rising or falling edge of a
selected relay signal or a match with the data of a selected word device. The CPU watches
the trigger condition when processing the END instruction of a program. If the trigger
condition becomes true, the CPU is allowed to perform 1024 rounds of sampling from a
point of time as much as the number of delays before (negative delay) or after (positive
delay) the condition becomes true.
Configure the sampling trace function using the programming tool. The results of sampling
trace operation can be viewed on the programming tool in timing-chart format, as shown on
the next page.
You can perform the sampling trace function in either the Run or Debug mode. The sam-
pling trace function, if performed once again, deletes previous data. If you define sampling
trace function settings using the configuration function, the CPU begins sampling at the
moment of power-on. If you define sampling trace function settings using the configuration
function and then permanently store them in ROM, the CPU reverts to the ROM data
during a power-on-and-off sequence even if you redefine the settings later using the pro-
gramming tool.

A6-28
Sampling trace Program name USR 1

Trigger occurrence time 97/09/07 15:23:07
Trigger condition: Data matching D0100 Sampling: Each scan Delay: 0
Cursor [ 0 ] ms
0 100 200 300 400 500
Relay device
1 X00401 0
2 Y00301 1
3 I0001 0
4 I0002 0
5 I0011 0
6 I0012 1
7 I0021 1
8 I0022 0
Word device -3 -2 -1 0 1 2 3 4
1 D1000 1024 2048 4696 8192 16384
2 D1001 245 245 245 250 250
3 D1002 27 27 28 28 29
4 D1003 0 0 0 0 0
KEYIN:
Enlarge Time-series
Reduce chart Address Menu
FA061101.EPS
Start of sampling trace operation : Instructed from the programming tool
Trigger condition : Set from the programming tool
¥ Rising/falling edge of signal at selected relay
¥ Match between data values
Sampling mode :TRC-instruction sampling
End-of-scan sampling (every 1 to 1000 scans)
Fixed-interval sampling (10 to 2000 ms)
Sampling frequency : 1024 cycles
Number of delays : Selection of a positive or negative number from -1023 to +1023
Devices to be sampled :16 units of X, Y, I, E, L, T, C or M relays
4 or 16 units of D, B, R, W, V, Z, T or C word devices or X, Y, I, E, L, T, C
or M relays, beginning with the one with the specified first address
Figure A6.23 View of Results of Sampling Trace Operation
See Also
Ladder Diagram Support Program M3 Instruction Manual (IM34M6Q13-01E), or FA-M3
Programming Tool WideField Instruction Manual (IM34M6Q14-01E) for details on how to
define sampling trace function settings.
Sampling is carried out as explained below.
● TRC-instruction Sampling
By using a TRC instruction in a program, you can sample the states and data of specified
contacts at any point of a scan.
The CPU collects data when the input-condition relay of the TRC instruction is set to ON.
The CPU stores results of up to four cycles of sampling if it has executed multiple TRC
instructions during the same scan. The subsequent TRC instructions are ignored. It is at
the end of a given scan when the CPU actually stores the results.
END TRC END TRC TRC END TRC END
Sampling Sampling Sampling Sampling

FA061102.EPS
Figure A6.24 TRC-instruction Sampling

A6-29
● End-of-scan Sampling
The CPU samples the states and data of specified contacts at the end of a scan. It collects
and stores the data each time the specified number of scans are completed.
END END END END
Sampling Sampling Sampling Sampling

FA061103.EPS
Figure A6.25 End-of-scan Sampling at Two-scan Intervals
● Fixed-interval Sampling
The CPU samples the states and data of specified contacts at fixed time intervals. It
collects and stores the data when the specified period expires and before the next scan
begins.
Specified period of time

END END END END
Sampling Sampling
FA061104.EPS
Figure A6.26 Fixed-interval Sampling
CAUTION
The sampling trace function monitors the trigger condition when an END instruction in a
program is being processed. The function therefore cannot judge the condition to be true if
it becomes true once during program execution but becomes false again by the time the
processing of the END instruction begins.
● Sampling when Negative Delay Is Defined

Number of delays (—)
Trigger condition is met End of a trace
Start of a trace
1,024 traces are stored in the sampling trace buffer.

FA061105.EPS
Figure A6.27 Sampling when Negative Delay Is Defined

A6-30
● Sampling when Positive Delay Is Defined
Number of delays (+) End of a trace

Trigger condition is met
Start of a trace
1,024 traces are stored in

the sampling trace buffer.
FA061106.EPS
Figure A6.28 Sampling when Positive Delay Is Defined

A6-31
A6.11 Personal Computer Link Function F3SP21

F3SP25
F3SP35
The programming tool connector on the front of the CPU module functions in the same way
as the RS-232-C communication port on the F3LC11-1N personal computer link module.
This means you can connect a host computer, such as a personal computer or FA com-
puter, or a monitor to the CPU module to perform one-to-one communication as with the
personal computer link module. This feature is called the personal computer link function.
You can monitor and configure devices and start, stop, load and save programs by entering
commands from the host computer.
Personal computer
on which "Ladder
Personal computer Diagram Support
or monitor with a Program M3" runs
PC interface
Personal X00503 X00504 Y00602

computer
X00501 X00502 Y00601
X00503
Personal computer Programming tool

link function connection function
Sequence CPU module FA061201.EPS
*Refers to either WideField or Loadder Diagram Support Program M3

Figure A6.29 Personal Computer Link Function

A6-32
A6.11.1 System Configuration

Figure A6.30 shows examples of system configuration using the personal computer link
function.
External equipment, such as a personal computer or monitor, is connected to the CPU
module of the FA-M3 by using the programming tool connector on the front of the FA-M3
and a dedicated programming tool cable.
Personal
computer
Monitor
Personal computer link cable

Personal computer link cable
Sequence CPU module Sequence CPU module

FA061202.EPS
Figure A6.30 Examples of Connection between CPU Module and External Equipment
For conformance to CE Marking, fit a ferrite core to the cable for the programming tools for
equipment using the personal computer link functions.
Kitagawa Industries Co., Ltd. RFC series

Examples of ferrite core TDK Corporation ZCAT series
Tokin Corporation ESD-SR series

A6-33
A6.11.2 Differences from Personal Computer Link Module

This subsection describes the differences between the F3LC11-1N personal computer link
module and the personal computer link function of the CPU.
■ Function Differences
The transmission rate and data format of the CPU’s personal computer link function differ
from those of the personal computer link module. For more information, see subsection
A6.11.4, “Setting Up the Personal Computer Link Function.”
Table A6.7 Transmission Rate and Data Format of CPU’s Personal Computer Link Function
Transmission Rate (bps) Data Length Parity No. of Stop Bits
9600 8 bits Even 1 bit
9600 8 bits None 1 bit
19200 8 bits Even 1 bit
TA061201.EPS
The dedicated programming tool cable is required to connect a personal computer or

monitor to the CPU module. To set the transmission rate, data format, checksum, terminal
character, and protection function, use the configuration item “communication setting,” or
switches in the case of the personal computer link module. The event transfer function is
not supported.
An MDR module reset command resets only the communication port. The maximum
number of personal computer link modules that can be installed remains the same even if
the CPU’s personal computer link function is used.
■ Protocol Differences
This paragraph briefly describes the communication protocol of the personal computer link
function.
Sending station Receiving station

Communication STX
protocol of personal
computer link function Station No.
CPU No.
Response wait time
Command
Parameters
Checksum
ETX
CR
STX
Station No.
CPU No.
OK
Command response
Checksum
ETX
CR
FA061203.EPS
Figure A6.31 Communication Protocol of Personal Computer Link Function
In personal computer link communication, the maximum size of text that can be transferred
at the same time is 512 bytes.

A6-34
A6.11.3 Specification of Personal Computer Link Function

Table A6.8 summarizes the specifications of the CPU’s personal computer link function.
Table A6.8 Specifications of Personal Computer Link Function
Item Description Setup*1

Supported CPUs F3SP21-0N , F3SP25-2N , F3SP35-5N
Interface Compliant with EIA RS-232C
Transmission mode Half-duplex
Synchronization Start-stop
Transmission rate(bps) 9600/19200 ✓
Start bit : 1
Data length: Fixed at 8 bits
Data format
Parity bit : None/Even ✓
Stop bit : Fixed at 1 bit
Parity check
Error checking
Checksum : Yes/No ✓
RS-232-C control line Not used.
Xon/Xoff Not used.
Configurable item Transmission rate, data format, checksum, terminal ✓

character, and protection function
Protocol Dedicated protocol
Terminating character Yes/No ✓
Protection function*2 Yes/No ✓
Range of access Access to all control data, uploading/downloading ladder

programs, CPU operation (Run mode)/stop (Stop mode),
operations and reading error logs
Transmission distance 8 m max.
External connection Dedicated cable
*1 The check mark ✓ indicates that the user can configure the item by using the configuration
function. However, there are restrictions on the way the transmission rate and parity check are
combined. See subsection A6.11.4, "Setting Up the Personal Computer Link Function," for more
information.
*2 You can set the protection function to the Yes option to prevent inadvertent writing to the FA-M3.
TA061202.EPS

A6-35
A6.11.4 Setting Up the Personal Computer Link Function

This subsection describes the items you should define when using the personal computer
link function.
■ Transmission Rate and Data Format

You cannot set up the transmission rate and data format separately because they are
shared by the programming tool and personal computer link function.
To define these items, use the ladder programming tool or the program configuration
function. You can only define the transmission rate and data format by selecting one of the
combinations listed in Table A6.9.
Table A6.9 Combinations of Transmission Rate and Data Format
Transmission Rate and Data Format
Mode Use of Hand-held
Transmission Data No. of
Parity Programming Tool
Rate (bps) Length Stop Bits
Communication mode 0 (*) 9600 8 bits Even 1 bit Yes
Communication mode 1 9600 8 bits None 1 bit No
Communication mode 2 (*) 19200 8 bits Even 1 bit No
* See "CAUTION" below.
TA061203.EPS
Communication mode 0: Default. In this mode, you can use the hand-held programming
console.
Communication mode 1: Select this mode when using a modem. In this mode, you
cannot use the hand-held programming console.
Communication mode 2: Only select this mode when you are using a personal computer
that supports the transmission rate of 19200 bps. In this mode,
you cannot use the hand-held programming console.
Under normal conditions, use the personal computer link function in communication mode
0. When the CPU starts up, the function is placed in the communication mode you have set
using the configuration function. The personal computer link function is set to “communica-
tion mode 0” when the sequence CPU module is shipped from the factory. You can use the
ladder programming tool for all of the communication modes. Refer to the following
cautionary notes before using the tool, however.
CAUTION
• If you select communication mode 2 and use a personal computer that does not
support 19200 bps, you can no longer switch back to the original communication
mode. In that case, connect a personal computer that supports 19200 bps and then
change the communication mode.
• If you have selected communication mode 0, set the personal computer link function
of the CPU to the option “Used” when editing the configuration item “personal
computer link function.” Otherwise, the CPU will automatically performs
communication during its startup, in order to read the RUN/STOP switches of the
programming console.

A6-36
CAUTION
• Be careful when setting the transmission rate.
The WideField supports all of the communication modes listed on the previous page.
However, first refer to the instruction manual of the personal computer that runs the
WideField to check available transmission rates and data formats. Then, temporarily
change the transmission rate of the personal computer link function using the
programming tool to make sure the CPU module can communicate with the personal
computer in the communication mode you want to use. Finally, configure the personal
computer link function according to that communication mode. Note that the personal
computer link function automatically reverts to the previous transmission rate if
communication is not established after a temporary change in the transmission rate.
If you select a communication mode in which the personal computer cannot
communicate, it is impossible to communicate with the CPU module through the
computer. If this happens, first install the sequence CPU module in the fifth or higher
numbered slot of the main unit. Next, turn on the power and make sure the RDY
indicator has come on. Then, turn off the power to clear the CPU memory completely
and allow the CPU module to revert to its factory-set defaults.
CAUTION
• To use the personal computer link function, set the configuration item “personal
computer link function” to the option “Used.” If you do not select this option, the CPU
performs communication at power-on in order to recognize the hand-held
programming console. Consequently, you may fail to successfully communicate with
higher-order equipment.
• If you set the configuration item “personal computer link function” to the option “Used,”
the settings of the RUN/STOP switches of the hand-held programming console are not
put into effect.
■ Checksum, Terminal Character and Write Protection Function

Define these items using the program configuration item “communication setting.” By
default, all these items are set to the option “Not used.”
SEE ALSO
FA-M3 Programming Tool WideField Instruction Manual (IM34M6Q14-01E), or Ladder

Diagram Support Program M3 Instruction Manual (IM34M6Q13-01E), for details on how to
use the configuration function.

A6-37
A6.11.5 Communication Procedure

To be able to perform communication, the transmission specifications, e.g., the transmis-
sion rate and data format, must be consistent between the CPU module and a personal
computer, FA computer or monitor.
Use the program configuration function to set up the transmission specifications of the
sequence CPU module. To set the transmission specifications of a personal computer or
FA computer, use a communication software program. In the case of the transmission
specifications of a monitor, use the configuration function of the monitor itself.
■ Communication Procedure
The following outlines the procedure of communication using a BASIC program on a
personal computer. For details on the statements and functions used in the program, refer
to the BASIC reference manual that came with your personal computer.
1. Open the RS-232-C communication file.

Enter a command in the following format:
OPEN “COM: xxxxx” AS#y
xxxxx: Enter communication parameters, such as the parity, data length, and the
number of stop bits.
y: File number. This number is used for subsequent inputs to and outputs from
the file.
2. Send a command to the FA-M3 in the following format.
PRINT#y, String variable name (or string)
3. Enter a command in the following format to receive a response from the FA-M3.
LINE INPUT#y, String variable name
INPUT#y, String variable name

A6-38
■ Overview of Communication
Communication control performed by the CPU module is based on the processing of
commands and responses using a dedicated protocol.
At first, the host computer (or monitor) has the transmission right. When the computer
sends out a command, the transmission right transfers to the CPU module. The CPU
module then sends a response to the host computer.
If the configuration item “personal computer link function” is set to the option “Used,” the
CPU module does not send a command to the host computer.
Personal computer
(when using BASIC)
PROGRAM
Command xxxxxx (ASCII string)

PRINT#
LINE INPUT#
or Response xxxxxx (ASCII string)
INPUT$
FA-M3
Power
supply CPU
FA061204.EPS
Figure A6.32 Interaction between Command and Response
Upper-level computer
Command STX code
Station number
CPU number
Response-wait time
Command To the FA-M3
Parameter
Checksum
(FA-M3)
ETX code Response STX code
Terminating character
Station number
CPU number
Response-wait time
To an upper-level computer Command response
(or monitor)
Checksum
ETX code
Terminating character
FA061205.EPS
Figure A6.33 Brief Description of Command and Response Formats

A6-39
A6.11.6 Commands and Responses

SEE ALSO
Personal Computer Link Command Instruction Manual (IM34M6P41-01E), for details on

commands and responses.
(1)Command Format and Elements

Figure A6.34 shows the format of a command to be sent from the host computer or monitor
to the FA-M3.
Number of bites Element

1 STX code
2 Station number (SA)
2 CPU number (nn)
1 Response-wait time (WT)
3 Command
Variable length Parameter
2 Checksum (SUM) Required only when "Checksum" of the

configuration facility is set to "Used."
1 ETX code
1 CR code Required only when "Terminating
character" of the configuration facility is
set to "Used."
Figure A6.34 Command Format and Elements
For commands and responses, use the upper-case alphabetic letters of A to Z, which are
the ASCII codes of $41 to $5A (hexadecimal numbers).
The individual elements are detailed below.
● STX (Start of Text) Code

A control code indicating the start of text. The corresponding character code is $2.
● Station Number
The station number is fixed at 01 when the CPU’s personal computer link function is used.
● CPU Number
Use a number from 01 to 04 to define which of the CPU modules to communicate with.
01: Main CPU module
02: Add-on CPU module 1

A6-40
● Response Wait Time
You can set a wait time, i.e., delay, which is an interval from when a command is sent to
when a response is received. The wait time can be as long as 600 ms. Set a relatively long
wait time if the communication software running on the host computer is such a program as
a BASIC interpreter. To set a wait time, use characters “0” to “F,” as shown below.
Table A6.10 Setpoints of Response Wait Time
Character Response Wait Time (ms) Character Response Wait Time (ms)
0 0 (Note) 8 80
1 10 9 90
2 20 A 100
3 30 B 200
4 40 C 300
5 50 D 400
6 60 E 500
7 70 F 600
TA061204.EPS
Note: Even if the response wait time is set at 0, there is a delay of as much as the internal processing time*.
Host computer
Command Response wait time
or monitor
Internal processing time*
CPU module
Pre- Post- Response
processing processing
Processing
One scan Pause between scans One scan

FA061207.EPS
Figure A6.35 CPU Operation during Response Wait Time
● Command
Using three letters, specify the type of access, such as reading or writing, from the host
computer or monitor to the CPU.
● Parameters
Set such data items as a device name, the number of devices and their data values.
Available parameter types vary depending on the command you use. A parameter is not
required for some commands.

A6-41
● Checksum
A checksum can be added to the transmission text to check data. Using the program
configuration function, you can determine whether or not to add a checksum. If you set the
item “Checksum” to “Yes,” you must add a checksum to a command which is sent from the
host computer or monitor to the FA-M3. In this case, a checksum is automatically added to
each response. If the item “Checksum” is set to “No,” this code is unnecessary. A
checksum is calculated as explained below.
The ASCII codes of characters from the one following the STX code to the one immediately
preceding the checksum code in the text are added together on a byte-by-byte basis.
The lower-order one byte of the result of performing addition is taken and represented as a
hexadecimal number. The 2-character, 2-byte string thus obtained is used as the
checksum.
Text to be sent (string) Checksum

Code to be calculated for a checksum
STX 0 1 0 1 A B R D X 0 0 2 0 1 , 1 6 B 9 ETX CR
02 30 31 30 31 41 42 52 44 58 30 30 32 30 31 2C 31 36 42 39 03 0D
ASCII code (hexadecimal)

30+31+30+31+41+42+52+44+58+30+30+32+30+31+2C+31+36=3B9 (hexadecimal)
Lower 1 byte of the result (3B9, hexadecimal) is represented as a string "B9." This string is a
checksum.
FA061208.EPS
Figure A6.36 Method of Check-sum Calculation
● EXT (End of Text) Code

A control code indicating the end of text. The corresponding character code is $3.
● CR (Carriage Return) Code

A control code indicating the termination of text. The corresponding character code is $0D,
which is the ASCII-code decimal numeral of 13. This code is required only if the configura-
tion item “Terminal character” is set to “Yes.”

A6-42
(2)Response Format and Elements
The following shows the format of a response to be sent from the FA-M3 to the host com-
puter or monitor. For details on the individual elements and characters used, see para-
graph (1), “Command Format and Elements.”
● When Communication is Normal

1 STX code
2 CPU number (nn)
2 OK
Variable length Command response

These values are also
2 Checksum (SUM) added to a response
1 ETX code only when they are
1 CR code specified with the
configuration facility.
FA061209.EPS
Figure A6.37 Response Format when Communication Is Normal
When communication ends successfully, the string “OK” is returned along with a command
response.
● When Communication is Abnormal

1 STX code
2 CPU number (nn)
2 ER
2 EC 1
2 EC 2
2 Command
These values are also
2 Checksum (SUM) added to a response
1 ETX code only when they are
1 CR code specified with the
configuration facility.
FA061210.EPS
Figure A6.38 Response Format when Communication Is Abnormal
When communication results in an abnormal end, the string “ER” is returned along with the
codes EC1 and EC2, where:
EC1 : Error code
EC2 : Detailed error code
If the communication failure is due to an error in the CPU number, the received 2-byte CPU
number is returned. If the failure is due to an error in the station number, no response is
returned.
If an ETX code in a command is not received, no response may be returned. If this hap-
pens, be sure to perform a timeout process on the host computer or monitor.

A6-43
(3)Error Code in a Response
A communication failure may occur when the sequence CPU module receives a command.
In that case, the module returns the string “ER” and an error code as a response to the
command.
The following error codes are reserved.
Table A6.11 Error Codes
Error Code (EC1) Meaning Probable Cause
01 CPU number error - The CPU number is outside the range of 1 to 4.
02 Command error - The command does not exist.
- The command is not executable.
- The device name does not exist.*
03 Device specification error - Incorrectly specified the bit devices in an attempt to read/write
them in units of words.
- Attempted to use characters other than 0 and 1 when setting bits.*
- Attempted to use values other than 0000 to FFFF when setting
04 Value outside the range words.
- The starting point in the command, such as Load or Save, is
outside the range of addresses.
05 Number of data items - The number of bits or words is outside the specified range.*
outside the range - The specified number of data items does not match the number
of parameters including device names.
- Attempted to execute monitoring without having specified a
06 Monitor error monitor command (BRS or WRS).
08 Parameter error - The parameter is incorrect for a reason other than noted above.*
41 Communication error - An error has occurred during communication.*
42 Checksum error - The check sum is wrong due to missing bits, garbled character,etc.
43 Internal buffer overflow - The amount of data received is larger than the specified.
Timeout - No end-of-process response is returned from the CPU for

51 reasons such as a CPU power failure.
52 CPU processing failure - The CPU has detected an error when processing the command.
- A Cancel command (PLC) has been issued while neither a Load
F1 Internal error command (PLD) nor a Save command (PSV) is in process.
- An internal error is found.
TA0601205.EPS
* See Table 6.12, "Detailed Error Codes," for more information.

A6-44
If a parameter error occurs, the detailed error code field indicates the number of the faulty
parameter. If a communication error occurs, the detailed error code field indicates details
on the error.
Table A6.12 Detailed Error Codes
Error Code (EC1) Meaning Detailed Error Code (EC2) *
03 Device specification error The EC2 field provides a hexadecimal representation of the
04 number assigned to the faulty parameter.
Value outside the range (The number is one, among the ordinal parameter numbers, at
Number of data items which an error has occurred first.)
05
outside the range (Example:) 1 2 3 4 5 6 Parameter
S numbers
T 0101ABRW 03 Y00501, 1, I0002, 0, A1234567
X
Erroneous device number
08 Parameter error In this example, the respective error codes take the values shown
below.
• EC1 = 08
• EC2 = 06
b7 b6 b5 b4 b3 b2 b1 b0
MSB LSB
Each bit has the following meaning.

b7: Reserved
41 Communication error b6: Reserved
b5: Framing error
b4: Overrun error
b3: Parity error
b2: Reserved
b1: Reserved
b0: Reserved
1 : Self-diagnostic error
2 : Program error (including parameter error)
4 : CPU-to-CPU communication error
8 : Device access error
52 CPU processing failure 9 : Protocol error
A : Parameter error
B : Operation mode error, or state of protection or exclusive access
C : Device/block specification error
F : System's internal error
* The EC2 error code has no meaning for any value of EC1 other than those listed above.
TA061206.EPS

A6-45
(4)Specifiable Devices
Table A6.13 lists devices that you can select by typing their names.
Use commas (,) or spaces to separate parameters. A device name should be represented
in six or seven characters (or bytes). Their abbreviations can also be used. For example,
X00201 can be abbreviated as X201 and V00002 as V02 or V2.
The following example shows the case of reading the data of CPU1’s five input relays,
beginning with input relay X00201. The response wait time is assumed to be 100 ms.
S
T 0 1 0 1 A B R D X 0 0 2 0 1 , 0 0 5
X
FA061211.EPS
Command Parameters
Response wait time
CPU number
Station number, which is fixed at 01.
Table A6.13 Specifiable Devices
Device Name Read Write

Length Bit Word Bit Word
Bit Xnnnnn Input relay 6 bytes Yes Yes No No
device Ynnnnn Output relay 6 bytes Yes Yes Yes Yes
Innnnn Internal relay 6 bytes Yes Yes Yes Yes
Ennnnn Shared/extended 6 bytes Yes Yes Yes Yes
shared relay
Lnnnnn Link relay 6 bytes Yes Yes Yes Yes
Mnnnnn Special relay 6 bytes Yes Yes Yes Yes
Tnnnnn Timer 6 bytes Yes *1 Yes *2 No Yes *2
Cnnnnn Counter 6 bytes Yes *1 Yes *2 No Yes *2
Word Dnnnnn Data register 6 bytes No Yes No Yes
device Rnnnnn Shared register 6 bytes No Yes No Yes
Vnnnnn Index register 6 bytes No Yes No Yes
Bnnnnnn File register 7 bytes No Yes No Yes
Wnnnnn Link register 6 bytes No Yes No Yes
Znnnnn Special register 6 bytes No Yes No Yes
*1 Specify:
a time-out relay as TUnnnn, and
an end-of-count relay as CUnnnn,
*2 Specify:
the current value of a countdown timer as TPnnnn,
the current value of a countdown counter as CPnnnn,
the current value of a count-up timer*3 as TInnnn,
the current value of a count-up counter*3 as CInnnn,
the setpoint of a timer*4 as TSnnnn, and
the setpoint of a counter*4 as CSnnnn.
*3 The countdown type of timers and counters has been made available with the FA-M3 controller for such
reasons as viewing on a host computer.
Current value of count-up type timer/counter ? Setpoint ( Current value of countdown type timer/counter
*4 The timer setpoint TSnnnn and counter setpoint CSnnnn are not available for a word writing command.
TA061207.EPS

A6-46
(5)Cautionary Notes on Communication Process
• No response may be returned if, for exanple, you specify a wrong station number in a
command. In such a case, perform a time - out process on the host computer.
• When downloading a program using the personal computer link function, you are not
allowed to download the program at the same time using a personal computer link
module or Ethernet interface module. If you do, normal operation is not guaranteed.
• If you write a value to a shared device that is being used by another CPU, the written
value may soon be updated.
• If you are using a monitoring-purpose command, you must renew it in the event of a
power failure.
• In personal computer link communication, the maximum size of text that can be sent
or received by the CPU module at one time is 512 bytes. The maximum size that can
be received by the host computer may be limited to 256 bytes if there is such a
limitation on the computer. If this is the case, pay special regard to the length of
response text. Take such corrective measures as reducing the number of devices to
be read, so that the text length will not exceed 256 bytes.

A6-47
A6.12 Device Management Function

The device management function enables you to upload/download device information/data
of the CPU module to/from the programming tool*, edit the data, and cross-check it against
the CPU module and the programming tool. You can specify the range of devices whose
data are uploaded or downloaded. You can also use this function to set defaults in devices
when, for example, replacing the CPU module.
* WideField or Ladder Diagram Support Program M3.
The devices that you can configure using the device management function are:
internal relays (I), shared relays (E), time-out relays for timers’ current values (T), count-up
relays for counters’ current values (C), data registers (D), shared registers (R), link regis-
ters (W), index registers (V) and file registers (B)
You cannot configure the following devices:
I/O relays (X/Y), timers and counters, special relays (M), and special registers (Z).
The device management function serves the following four purposes:
■ Device Data Uploading

The device management function allows you to read device information/data from the CPU
module and saves it to a file of the programming tool. You can specify the range of devices
to be saved.
■ Device Data Downloading

The device management function allows you to read device information/data from a file of
the programming tool and writes it to the CPU module. You can either download all the
device data from the file or download part of the data by specifying the range of devices.
■ Device Data Editing

The device management function allows you to edit device information/data in a file of the
programming tool. You can view and change the current value of each device.
■ Device Data Cross-checking

The device management function allows you to cross-check device information/data in the
CPU module against that in a file of the programming tool. You can make a cross-check on
all device data in the file or part of the data by specifying the range of devices. If there is
any mismatch, the function shows the name of the device having the mismatch as well as
the mismatch itself.

A6-48
A6.13 Macro Instructions F3SP25

F3SP35
The F3SP25 and F3SP35 sequence CPU modules support user-created macro instruc-
tions.
A6.13.1 What Are Macro Instructions?
■ Overview
A macro instruction enables you to perform a process requiring multiple instructions/steps
as a single-instruction/step process.
Figure 6.39 presents an overview of the macro instructions.
Macro instructions described in ladder-diagram editing

X00502
MOV 1 D0001
M Macro
ABC D0001 D0002 0 instruction call
(Nemonic: MCALL ABC D0001 D0002 0) (calling side)
M V01
EFG123 D0002 W0001 Y00301
(Nemonic: MCALL EFG123 D0002 W0001 Y00301)
FA061401.EPS
Macro instruction ABC described in ladder-macro editing

"ABC" macro instruction entity (called side)
M033
MOV 1 A0001
MOV 2 U01
U01
P02 = P01 + A000
MRET
FA061402.EPS
Figure A6.39 Examples of Macro Instructions
In Figure A6.39, the “ABC” and “EFG123” instructions are macro instructions. When the
CPU encounters the “ABC” instruction, it executes a called-side “ABC” macro instruction
like a subroutine, using operands “D0001” and “D0002” as its parameters. Macro instruc-
tions are created by ladder-macro editing separately from regular instructions created in
ladder-diagram editing. The MRET instruction in Figure 6.34 represents the end of the
macro instruction.
For details on operands P01, P02, and U01 in the figure, see subsection A6.13.3, “Devices
Dedicated to Macro Instructions.”
SEE ALSO
Subsection 3.13.6, “Macro Instructions, Parameter Instructions, Macro Instruction Returns”

in the 2nd or later edition of, Sequence CPU Instruction Manual - Instructions
(IM34M6P12-03E), for details on the MRET instruction.

A6-49
■ Purpose
Using macro instructions offers the following two advantages.
● Enhancing Programming Efficiency

Like subroutines, macro instructions allow you to group processes of the same type into
one. Macro instructions differ from subroutines, however, in the following two ways.
• Parameters can be passed to macro instructions.
Subroutines require that an instruction for passing parameters, such as MOV, must
precede a CALL instruction.
• Macros can be handled as instructions.
You need not be aware of internal processing at all except for inputting/outputting
parameters.
Note: 1. Copy a block containing subroutines under a different name.

2. Delete components other than subroutines from a circuit diagram.
3. In ladder-diagram editing, read the copying-destination block.
Using existing Using macro

subroutine instruction
Use existing No No
Macro instruction
subroutine? exists?
Yes Yes
Find Refer to Create new macro
subroutine Create new subroutine
specifications instruction
Find Enter macro

inputs/outputs instruction
List devices used End

in subroutine
Copy subroutine
(Note)
Match inputs/outputs
with devices used in Note: 1. Copy a block containing subroutines under a different name.
subroutine 2. Delete components other than subroutines from a circuit diagram.
3. In ladder-diagram editing, read the copying-destination block.
End FA061403.EPS
Figure A6.40 Difference between Subroutines and Macro Instructions
● Accumulating Expertise
You can use your control expertise to create macro instructions to customize your FA-M3
controller.

A6-50
A6.13.2 Specification of Macro Instructions
■ Supported CPU Modules

Macro instructions are only supported for the F3SP25 and F3SP35 sequence CPU mod-
ules.
■ Number of Macro Instructions

Called-side macro instructions are downloaded, along with user ladder diagrams, from a
personal computer to the CPU module using the programming tool*. You can include a
maximum of 64 called-side macro instructions in one executable program during download-
ing. In addition, you can use each calling-side macro instruction in your user ladder
program any number of times.
* WideField or Ladder Diagram Support Program M3
■ Size of Macro-instruction Program

The size of a program of called-side macro instructions is limited by the total size of that
program and user programs combined.
■ Macro Instruction Execution Time

Table A6.14 Macro Instruction Execution Time
F3SP25 F3SP35
FUNC Instruction Mnemonic
When When not When When not
No. executed executed executed
executed
(esec) (esec) (esec) (esec)
996 Macro instruction call MCALL 22.0 0.6 16.5 0.45

995 Parameter instruction PARA 8.0 0.36 6.0 0.27
998 Macro instruction return MRET 10.0 — 7.5 —
TA061401.EPS
■ Online Macro Instruction Editing

You can use the online edit function of the programming tool for user-created ladder dia-
grams containing calling-side macro instructions. In that case however, you can only use
macro instructions that have already been downloaded. You cannot create a new macro
instruction. You can also edit online called-side macro instructions which have already
been downloaded. It is not possible, however, to edit online any circuit diagram that follows
an MRET macro return instruction.
■ Making Macro Instructions Resident in ROM

Like programs, you can make macro instructions resident in a ROM pack. This is automati-
cally done when you transfer a program to the ROM pack using the ROM writer function of
the CPU module.

A6-51
A6.13.3 Devices Dedicated to Macro Instructions

Table A6.15 lists devices dedicated to macro instructions.
Table A6.15 Devices Dedicated to Macro Instructions
F3SP25, F3SP35
Device Code
Range Quantity
Pointer register P P01 to P16 16
Macro relay H H0001 to H0512 512
Macro register A A0001 to A0512 512
Macro index register U U01 to U16 16
TA061402.EPS
■ Pointer (P) Registers

Pointer registers are dedicated to macro instructions and used to pass parameters to
macro instructions. You can use these registers for called-side macro instructions. Table
A6.16 shows the relationship between pointer registers and macro instruction operands.
M
EFG123 D0001 I0001 Y00301
Operand3
Operand2
Operand1
FA061404.EPS
Table A6.16 Relationship between Pointer Registers and Macro Instruction Operands
Operand No. Pointer Register No.
1 P01
Parameters that can be directly passed using a macro
2 P02 instruction call
3 P03
4 P04
Parameters that can be passed using a parameter
instruction
16 P16
T061303.EPS
Using a basic or advanced instruction, you can read from and write to pointer registers in a
macro instruction just like devices passed as parameters. You can also apply a word/long
word process, index modification process, and automatic BIN-to-BCD or BCD-to-BIN
conversion process to these pointer registers. High speed processing of advanced instruc-
tions is not performed, however. More specifically, high speed processing does not apply to
a MOV, CAL, CMP, or logical operation instruction that uses pointer registers in a macro
instruction as its operands.
TIP
When executing two or more instructions that use pointer registers, it is recommended that
you first transfer the values of the pointer registers to macro relays/registers. Then, execute
two or more instructions that use these macro relays/registers. This strategy reduces the
instruction execution time.

A6-52
X00502
MOV 1 V01
V01
PARA 4 R0001 P04=R0002
M
P01=D0001
EFG123 D0001 I0001 Y00301
P02=I0001
(Nemonic: MCALL EFG123 D0001 I0001 Y00301) P03=Y00301
Real "EFG123" macro instruction (called side)
M033
MOV 1 A0001
MOV 2 U01
U01
P04 = P01 + A0001
Pointer register specified in a macro instruction (called side)
(Note)
U01
R0002 = D0001 + A0001
MRET
(Note) Pointer registers can be used for real macro instructions (called side).
FA061406.EPS
Figure A6.41 Example of Using Pointer Registers
CAUTION
• If you pass a device accompanied by an index modification device to a macro instruc-
tion as a parameter, the instruction receives an already index-modified device. In the
example of Figure A6.41, the parameter R0001;V01 equals the device R0002 be-
cause V01 = 1.
• Any index modification in a pointer register applies to a parameter that is passed. In
the example of Figure A6.41, the parameter P01;U01 equals the device D0003
because P01 = D0001 and U01 = 2.
■ Macro Relays (H), Macro Registers (A) and Macro Index Registers (U)
These devices are dedicated to macro instructions. Using a basic or advanced instruction,
you can read from and write to a macro relay, macro register and macro index register in a
called-side macro instruction just like an internal relay (I), data register (D) and index
register (V). These devices can be used for called-side macro instructions.
You can use these devices in your macro instruction without having to be aware which
devices are used in the instruction when applying the instruction. Needless to say, the
values of these devices are retained.

A6-53
A6.13.4 Nesting Macro Instructions

Nesting macro instructions enables you to call another macro instruction when executing
the current execution. If you nest macro instruction calls to a depth of more than eight
levels, an instruction processing error will result. The depth of nesting is stored in special
register Z106. The value “0” is stored in the special register Z106 if you execute any non-
nested macro instruction.
CAUTION
Parameters 1 to 3 to be passed to macro instructions are saved when the macro instruc-
tions are nested. However, parameters 4 to 16 passed by parameter instructions are not
saved. If a parameter instruction is executed in a called macro instruction, the relevant
parameters are overwritten.
SEE ALSO
Subsection 3.13.6, “Macro Instructions, Parameter Instructions, Macro Instruction Returns”

in the 2nd or later edition of, Sequence CPU Instruction Manual - Instructions (IM34M6P12-
03E), for details on parameter instructions.

A6-54
When nesting macro instructions, you may mistakenly overwrite macro devices, such as
relays, registers and index registers, in a called macro instruction and thereby destroy their
data. To avoid this problem, check the depth of macro instruction nesting stored in special
register Z106 and use macro devices separately for each level of nesting depth (see the
example below).
X00501 M
NEST1 D0001 D0002
Real NEST 1 macro instruction
X00502
U01 = Z106 * 64
0 0
A01 = P1 + 1
A01 (A001 to A064 can be used.)

M U01
NEST2 A01 P2
U01 = Z106 * 64
The NEST 2 instruction damages U01.
MRET
Real NEST 2 macro instruction

X00503
U01 = Z106 * 64
64 0
U01
A01 = P1 + 1
A01 (A001 to A064 can be used.)

U01
NEST3 A01 P2
U01 = Z106 * 64
The NEST 3 instruction damages U01.
MRET
FA061407.EPS
Figure A6.42 Example of Using Macro Devices Separately when Nesting Macro Instructions

A6-55
A6.13.5 Handling Macro Instruction Errors

An error occurs when creating a program using a macro instruction tool if:
• there are two or more macro instructions of the same name,
• a macro instruction specified in an MCALL macro instruction call is not found, or
• any single macro instruction contains two or more MRET macro return instructions.
An error also occurs and the special relay M201 for instruction processing errors is set to
ON if:
• an MRET ladder macro instruction return is executed before an MCALL macro
instruction call (special register Z022 contains the error code $2501), or
• the depth of macro instruction call nesting exceeds eight levels (special register Z022
contains the error code $2502).
An error encountered in a called-side macro instruction is viewed by the user as an error in
a calling-side macro instruction. Thus, the user can know which parameters were passed
to the macro instruction.
CAUTION
An error, except a check-sum memory error, found by self-diagnosis in a called-side macro
instruction is also viewed by the user as an error that has occurred as the result of execut-
ing a calling-side macro instruction.
It is not possible to determine in which downloaded-type macro instruction a check-sum

memory error is found. Therefore, the error is recognized when it is detected, rather than
when the macro instruction is executed.
Table A6.17 Error Codes for Macro Instructions
Error Type Error Name Error Code Description
$2501 There is no return destination.
Instruction processing Macro instruction error The upper limit of nesting depth, i.e.,
$2502 eight levels, has been exceeded.
TA061403.EPS

A6-56
A6.13.6 Protecting Macro Instructions

You can protect macro instructions from being referenced by someone else to ensure the
security of called-side macro instructions. This protection is achieved for each macro
instruction by entering a password with the WideField or Ladder Diagram Support Program
M3. A password must consist of eight alphanumeric characters, beginning with a letter.
The protection information is saved in the management information area of a macro in-
struction file. You are not allowed to perform macro instruction editing, printing and monitor-
ing for macro instructions under protection unless your password matches.
CAUTION
Executable program protection and block protection are effective for user-created ladder
programs that contain macro instructions. If, for example, executable program protection is
enabled, any act of working with executable programs, such as downloading, uploading,
monitoring or online-editing, becomes impracticable.
A6.13.7 Debugging Operation
■ Forced-Set/Reset
You can also turn on and off bit devices forcibly in calling-side and called-side macro
instructions.
■ Step and Partial Operations

Partial operation is not possible with calling-side and called-side macro instructions.

A6-57
A6.14 User Log Management Function F3SP21

F3SP25
F3SP35
User log management is a function that logs, or keeps record of, errors in a user system,
information on the way they occurred, and the condition of system operation, by executing a
user log instruction. This function is useful for analyzing faults and understanding the
operating conditions of machinery. You can read saved user logs using instructions or the
programming tool.
■ Handling User Logs

For each CPU, you can save a maximum of 64 user logs as 32-character messages
classified by their main codes, by executing a user log instruction in a program. As user log
information, four data items-the date, time, one-word main code and one-word subcode-are
recorded. The user log information storage area is used cyclically. If the maximum
recordable number of logs is exceeded, the extra logs are ouÚ≤written in chronological
order. Use the programming tool or a user log reading instruction to read stored user log
information. You can refer to the special register Z105 to find out the number of user logs
stored.
Ladder diagram
Stored when an instruction is executed
ULOG D0001 D1000
User log information storage area
97/09/26 14:10:52 12-05 Stored

97/09/26 14:21:12 17-04 (or overwritten)
in order of
occurrences
Rotary
buffer
system
FA061501.EPS
Figure A6.43 Handling User Logs
CAUTION
In some cases, the programming tool may show two identical logs. This happens when you
execute a user log instruction to store a new user log while reading a stored use log using
the programming tool. To prevent this from occurring, view user logs when you are not
executing a user log instruction.
SEE ALSO
Subsection 3.13.5, “Storing, Reading and Clearing User Logs,” in the 2nd or later edition of
Sequence CPU Instruction Manual -Instructions (IM34M6P12-03E) for details on
instructions related to user logs.

Blank Page
A7-1
A7. I/O Response Time Based on Scan Time

This chapter discusses examples of calculating the scan time and I/O response time.
It also explains such parameters as instruction execution time.
A7.1 Scan Time

As discussed earlier in Chapter A3, the sequence CPU module is designed so that two
systems of processes, i.e., a system of control-related processes and a system of
peripheral processes, run concurrently and independently. For this reason, the system of
control-related processes whose main purpose is to execute programs and control-related
processes is not affected by the system of peripheral processes whose purpose is to
support communication and programming tools. Thus, the system of control-related
processes can run at extremely high speeds. Under normal conditions, the scan time of the
sequence CPU module is equivalent to the time taken by the system of control-related
processes. The following paragraphs explain the processing tasks and time of each of
these systems.
● System of Control-related Processes

The latest, maximum and minimum scan times taken by the system of control-related
processes are stored in special registers Z001 to Z003 in that order.
Table A7.1 Scan Time of System of Control-related Processes
Item Processing Task Processing Time

Common processing Self-diagnosis Fixed at 0.5 ms.
Program execution Executes ladder programs. The scan The scan time is the sum of the execution
time is calculated using the program times of basic and advanced instructions. It
execution time or output refreshing varies depending on the type of CPU module
time, whichever is greater. and the execution time of each instruction
word. See Section A7.5, "Instruction
Execution Time," for more information.
Output refreshing Writes the contents of Y output relays 12 µs 3 number of modules calculated on a
to an output module. 16-device basis*
Input refreshing Reads the contents of 3 input relays to 6 µs 3 number of modules calculated on a
write them to the output module. 16-device basis*
Synchronization processing Ensures synchronization and the simul- • When output relays are used:
taneity of data for operation- and con- 8 µs3number of modules calculated on a
trol-related processes between the sys- 16-device basis*
tem of control-related processes and • When FA link modules are used:
the system of peripheral processes. 0.003 3 (number of relays used in FA link for
refreshing/16 ( number of registers used in
FA link for refreshing) +0.05 ms.
• When an add-on CPU is installed:
0.002 3 (number of relays set in local
CPU/32 • number of registers set in local
CPU/2)+0.05 ms.
TA070101.EPS

A7-2
* Relationship between Types of I/O Module and Number of Modules Calculated on a
16-device Basis
Type of I/O Module Number of Modules Calculated on a 16-device Basis
4-point I/O relay 1
8-point I/O relay 1
14-point I/O relay 1
TA070102.EPS
● System of Peripheral Processes

The latest, maximum and minimum scan times taken by the system of peripheral
processes are stored in special registers Z007 to Z009 in that order.
Table A7.2 Scan Time of System of Peripheral Processes
Item Processing Task Processing Time
Link refreshing Updates the contents of link relays and When an FA link module is installed:
registers when an FA link module is 0.015 T (number of relays used in FA link for
installed. refreshing/16 + number of registers used in FA
link for refreshing) + 0.06 ms
Not performed if no FA link module is When no FA link module is installed: 0.00 ms
installed.
Shared refreshing Updates the contents of When an add-on CPU is installed:
shared/extended shared relays and 0.014 T (number of relays set in CPU for
shared/extended shared registers refreshing/32 + number of registers set in CPU
when an add-on CPU is installed. for refreshing/2) + 0.10 ms
In a single refreshing cycle, this task
updates the contents of
shared/extended shared relays or
shared/extended shared registers
included in the configuration setting, for
each CPU.
Not performed if no add-on CPU is When no add-on CPU is installed:
installed. 0.00 ms
Tool service Processes commands input from a Varies with the type command.
programming tool connected to the
CPU. Executes one command per
service.
Link service Processes commands input from a Varies with the type command.
personal computer link module.
Executes one command per service.
CPU service Processes commands input from a Varies with the type command.
remote CPU module. Executes one
command per service.
T070103.EPS
A7.2 Setting Scan Time Monitoring Time

This configuration item sets the scan time monitoring time. You can set the time within the
range of 10 ms to 200 ms, in 10 ms increments. By default, the time is set at 200 ms.

A7-3
A7.3 Examples of Calculating the Scan Time

● When the CPU is F3SP21
Module configuration :Four 32-point input modules
:Four 32-point output modules
User program :3K steps consisting of LD and OUT instructions only, where the
average execution time of these instructions is assumed to be 0.3 µ s
F
3 F
P 3
U S
2 P
2
0 8
32-point input 32-point output

module module
F070301.EPS
Figure A7.1 Module Configuration of F3SP21 Sequence CPU
Table A7.3 Scan Time of F3SP21 Sequence CPU

Item Calculation Processing Time
Common processing Fixed at 0.5 ms. 0.5ms
Program execution 0.3µs 3 3072 = 922µs 0.9ms
Number of modules calculated on a 16-device basis
Output refreshing 234=8 12µs 3 8 = 96µs 0.1ms*

Input refreshing 234=8 6µs 3 8 = 48µs 0.05ms

Synchronization 0.06ms
234=8 8µs 3 8 = 64µs
processing
Scan time, which is the sum of all time spans listed above 1.5ms
* The output refreshing time and the minimum peripheral processing time are excluded from scan time
calculation because the sum of these time spans is smaller than the program execution time.
TA070301.EPS

A7-4
● When the CPU Is F3SP35
Module configuration: Four 32-point input modules
:Four 32-point output modules
User program :5K steps consisting of LD and OUT instructions only, where the
average execution time of these instructions is assumed to be 0.15 µ s
F
3 F
P 3
U S
2 P
5
0 8
32-point input 32-point output

module module
F070302.EPS
Figure A7.2 Module Configuration of F3SP35 Sequence CPU
Table A7.4 Scan Time of F3SP35 Sequence CPU

Item Calculation Processing Time
Common processing Fixed at 0.5 ms. 0.5ms
Program execution 0.15µs T 3072 = 717µs 0.5ms
Output refreshing Number of modules calculated on a 16-
points basis 0.1ms*
12µs T 8 = 96µs
Input refreshing Number of modules calculated on a 16-
points basis 0.05ms
2 T 4 = 8 6µs T 8 = 48µs
Synchronization Number of modules calculated on a 16-
processing points basis 0.06ms
2 T 4 = 8 6µs T 8 = 48µs
Scan time, which is the sum of all time spans listed above 0.1ms
* The output refreshing time and the minimum peripheral processing time are excluded from scan time
calculation because the sum of these time spans is smaller than the program execution time. calculation
because the sum of these time spans is smaller than the program execution time.
T070302.EPS

A7-5
A7.4 Examples of Calculating the I/O Response Time

● Calculation of the minimum I/O response time
Input response time :16 ms
Output response time :1 ms
Scan time :2 ms
Minimum I/O response time = Input response time + Scan time + Output response time
= 16 ms + 2 ms + 1 ms = 19 ms
X00502 Y00602
Input refreshing
Output refreshing
Input X00502 One scan
Output Y00602
F070401.EPS
Figure A7.3 Minimum I/O Response Time
● Calculation of the maximum I/O response time

Input response time :16 ms
Output response time :1 ms
Scan time :2 ms
Maximum I/O response time = Input response time + (Scan time T 2) + Output responce time
= 16 ms + (2 T 2) ms + 1 ms = 21 ms
X00502 Y00602
Input refreshing
Output refreshing
One scan One scan

Input
X00502
Output Y00602
F070402.EPS
Figure A7.4 Maximum I/O Response Time

A7-6
A7.5 Instruction Execution Time

The execution time of each instruction is found in “Table of Instruction Words” in Appendix
of Sequence CPU Instruction Manual - Instructions (IM34M6P12-03E).
The instruction execution time varies slightly depending on the contents of source-of-
transfer or destination-of-transfer devices or the number of devices included in data
transfer. The execution time lengths listed in the “Table of Instruction Words” are typical.
Use these values of instruction execution time for reference purposes only when calculating
the scan time. The instruction execution time decreases or increases in length, as shown in
Table A7.5 below, depending on the conditions under which an instruction is executed. Use
values of T in the Table of Instruction Words to figure out guidelines of the scan time
according to the formulas given in Table A7.5.
Table A7.5 Calculation of Instruction Execution Time
Instruction Execution Time (µs)
Execution Conditions
When executed T+0.36 T+0.24 T+0.18
Differential type instruction
When not executed
16 bits T+5.03N1 T+3.33N1 T+2.53N1
Relay (BIN format)
32 bits T+7.03N1 T+4.73N1 T+3.53N1
X and Y I/O relays defined 16 bits T+7.03N2 T+4.73N2 T+3.53N2
in BCD format 32 bits T+9.03N2 T+6.03N2 T+4.53N2
Basic instruction T+2.03N3 T+1.33N3 T+1.03N3
Index modification
Application instruction T+4.03N4 T+2.63N4 T+2.03N4
Link registers with numbers
W20001 and greater Register — T+5.13N4 T+3.83N4
File registers
For these relays, further
Extended shared relays add the execution time of
Special relays with numbers Relay — "relays (BIN format)" to
M1025 and greater each execution time
indicated above.
T: Instruction execution time in "Table of Instruction Words"
N1: Number of relay devices
N2: Number of relay devices defined in BCD format
N3: Number of index-modified relay devices
N4: Number of link registars with numbers W20001 and greater and file resisters TA070501.EPS
See Also
Table of instruction words in Appendix of Sequence CPU Instruction Manual - Instructions
(IM34M6P12-03E), for details on the execution time of each instruction.
■ Examples of Calculation
The following paragraphs give examples of calculating the instruction execution time. For
information on the execution time of an MOV instruction, see “Application Ladder-sequence
Instructions” in Appendix 2 of Sequence CPU Instruction Manual - Instructions
(IM34M6P12-03E).
● Differential Type Instructions
MOV D0001 D0002
0.36 + 0.36 = 0.72 s (for F3SP21 sequence CPU)


A7-7
● Relays (BIN Format)
Use any execution time in parentheses ( ), from the “Table of Instruction Words.”
MOV I0002 D0001 Number of relay devices:

N1 = 1
6.4 + 5.0 31= 11.4 µs (for F3SP21 sequence CPU)
● X and Y I/O Relays Defined in BCD Format

MOV I0002 D0001 Number of relay devices

defined in BCD format: N2 = 1
● Index Modification
(1) Basic Instructions
I0001
Number of index-modified
relay devices: N3 = 1
0.18 + 2.031 = 2.18 µs (for F3SP21 sequence CPU)
(2) Advanced Instructions

V01 V02
MOV D0001 D0002 Number of index-modified
relay devices: N3 = 2
6.4 + 4.0 3 2 = 14.4 µs (for F3SP21 sequence CPU)

A7-8
● Extended Shared Relays/Registers, Special Relays with Numbers M1025
and Greater, Link Registers with Numbers W20001 and Greater, and File
Registers
(1) Extended Shared Registers, Link Registers and File Registers
MOV B0001 D0001 Number of file registers N4=1

(2) Extended Shared Relays and Link Relays with Numbers M1025 and Greater
The execution time of “relays (BIN format)” is further added to the execution time of
devices discussed in item 1 above.
MOV E3098 D0001 Number of extended shared

relays N4=1
4.3 + (5.1 + 3.3) 31= 12.7 µs (for F3SP25 sequence CPU)
3.2 + (3.8 + 2.5) 31= 9.5 µs (for F3SP35 sequence CPU)

A8-1
A8. RAS Features

This chapter describes the RAS features of the sequence CPU module, such as the self-
diagnosis and error logging functions that work if the module fails.
A8.1 Self-diagnosis
The sequence CPU performs self-diagnosis on its device memory, instruction codes, and
so on when the power is turned on or a program is being executed. The results of self-
diagnosis are reflected in predetermined special relays and registers. If any failure is found
during self-diagnosis, the CPU updates the statuses of LED indicators and stops executing
programs depending on the failure mode.
Table A8.1 shows how the severity of failure is classified by type and mode.
Table A8.1 Severity of Failure and Statuses of LED Indicators
FAIL Signal Action of Output
Contact Output Module
Between Between Output Output
FAIL1 FAIL2 modules modules
Severity of LED Indicator Failure
Failure and COM and COM with 32 or with 64
Status Condition Failure Mode less output output
points points points *2
Major The green RDY The key • CPU failure Shorted Open Default: Nullified
failure lamp goes out. hardware is • Memory crash RESET setpoint
disabled. • Power-off Can be set The status
in 16 point is always
increments. HOLD.
Moderate The red ERR The user • Program error Shorted Open Default: Default:
failure lamp comes on. program • I/O collation failure*1 RESET RESET
cannot be • I/O module failure*1 Can be set Can be set
• Memory failure
started or run in a group in a group
• CPU failure
any further. on a on a module
• Instruction error*1 module basis.
• Scan time-out*1 basis.
• Startup failure
• Detection of invalid
instruction
• Excess number of
I/O points
• ROM pack failure
• Subroutine error*1
• Interrupt error*1
• Failure in subunit
transmission line*1
• Sensor control scan
time-out error*1
Minor failure The yellow ALM The program is • Momentary power Open Shorted Continued Continued
lamp comes on. abnormal, failure operation operation
though it can • CPU-to-CPU
still be run. communication
* 1: Either the minor or moderate failure can be selected as the failure level for this item using the configuration function
* 2: Include the F3WD64 module and advanced modules that contain output relays. TA080101.EPS
For some of the failure modes, you can select the Stop or Continue option to determine
whether to stop or continue program execution if any of these failures occur. This
selection can be made using the configuration function. This configuration item defaults to
the Stop option for a moderate failure and to the Continue option for a minor failure.
Moderate failure modes set to the Continue option are treated as minor failure modes,
while minor failure modes set to the Stop option are treated as moderate failure modes.
IM 34M6P12-02E 2nd Edition : Oct 1, 2001-00

A8-2
CAUTION
• If you want the contacts of an output module to be reset in case of a major or
moderate failure in the sequence CPU module, use an output module with 32 or less
output points and set the “Output in case of CPU stop” option of the configuration
function to RESET.
• If you want the contacts of an output module to be held in case of a major or moderate
failure in the sequence CPU module, set the “Output in case of CPU stop” option of
the configuration function to HOLD. Note that there is no difference in the module
action due to a difference in the type of output module.

A8-3
Table A8.2 Details on Self-diagnosis (1 of 6)
Special Special Stored
Relay Registers Error
Failure Mode that that Store Code Failure Description Corrective Actions
Turns Error
on Codes, Etc.
Major CPU The CPU Hardware 1.Check the installation environment
failure failure - - - malfunctions due to failure for possible problems, such as
noise or for other noise sources. If the failure recurs,
reasons. replace the module.
Hardware failure
Moderate Startup M193 Z017 to $10nn A failure has 1.It is likely that restrictions on
failure failure Z019 occurred during module installation have been
CPU initialization. violated. Check the modules
according to Section 1.2,
"Restrictions on Installing
Modules," in the instruction manual
Sequence CPUs Hardware.
2.Check the installation environment
for possible problems, such as
noise sources. If the failure recurs,
replace the module.
SPU $11nn The CPU for 1.Check the installation environment
failure sequence for possible problems, such as
computing has noise sources. If the failure recurs,
failed. replace the module.
Memory $1201 A program Transient memory 1.It is likely that the error is due to a
failure checksum error has failure or hardware transient memory failure caused by
occurred. failure (See effects of noise. Check the
CAUTION at the end installation environment. Clear the
of tables for memory by referring to CAUTION at
information on how the end of tables and download the
to discriminate program once again. If the failure
between these recurs, replace the module.
failures).
$1202 Inadvertent writing Application 1.Check if there is any error in the

has been done to values of index registers or in the
the M129 to M131 parameters defining the number of
special relays for devices in an instruction for globally
handling Run, rewriting multiple devices, such as
Debug and Stop a BMOV block transfer instruction.
mode flags.
A device memory Hardware 1.It is likely that the error is due to a
read/write check failure transient memory failure caused by
error has occurred. effects of noise. Check the
$1203 A system memory installation environment. Clear the
read/write check memory by referring to CAUTION at
error has occurred. the end of tables and download the
program once again. If the failure
Detection $1701 An invalid recurs, replace the module.
of invalid instruction has been
instruction encountered.
$1702 There is no END
instruction in the
program.
TA080201.EPS

A8-4
Turns Error
on Codes, Etc.
Moderate Program M193 Z017 to $2001 The JMP, SUB and Wrong input to 1.Verify compatibility among the
failure error Z019 RET instructions programmable JMP, SUB and RET instructions.
are not compatible controller 2.It is likely that the error is due to a
with one another. Hardware failure transient memory failure caused by
effects of noise. Check the
installation environment. Clear the
memory as instructed in CAUTION
at the end of section and download
the program again. If the failure
recurs, replace the module.
Excess $2002 The number of I/O 1.It is likely that restrictions on
number points has been module installation have been
violated. Check the modules
of I/O exceeded.
according to Section 1.2,
points "Restrictions on Installing Modules,"
in the instruction manual Sequence
CPUs-Hardware.
ROM $8203 The ROM pack is Mismatch between 1.A ROM pack whose data has been
pack incompatible with ROM pack and erased is in no way defective. Use
failure the CPU. CPU it as is.
Hardware failure 2.It is likely that data has been
written to the ROM pack under a
wrong CPU name. Rewrite to the
ROM pack and try using it again.
The ROM pack or CPU module
may be defective if the same failure
recurs. Replace the ROM pack or
CPU module.
$8204 It is not possible to Hardware failure 1.Rewrite to the ROM pack and try
read from or write to using it again. The ROM pack or
the ROM pack. CPU module may be defective if
the same failure recurs. Replace
the ROM pack or CPU module.
Battery M194 - $1801 The backup 1.The power supply module may be
failure batteries have defective if the same failure recurs.
failed. Replace the module.
Sub- M201 Z022 to $2201 The RET instruction Application error 1.Check if there is such an error as a
routine Z024 has not been jump out of or into the subroutine
error executed because 2.Check if a scan timeout has been
(Note) there is no return detected within the subroutine.
destination.
$2202 The maximum 1.Check the depth of nesting when
nesting depth of calling another subroutine in a
eight levels has given subroutine.
been exceeded.
TA080202.EPS
Note: For this failure mode, you can determine whether to stop or continue program execution.

A8-5
Turns Error
on Codes, Etc.
Moderate Interrupt M201 Z022 to $2301 The IRET instruction 1.Check if there is such an error as a
failure error Z024 has not been jump out of the interrupt program or
(Note) executed because a jump into the program from
there is no return outside it.
destination. 2.Check if a scan timeout has been
detected within the subroutine.
$2302 There are more than 1.There are more than eight
eight interrupts interrupts waiting for execution.
waiting for Check the detailed process of each
execution. interrupt, the number of interrupts,
their frequency, etc. When the
power is turned on and before the
program is executed, check if there
is a possibility that more than eight
interrupts will occur.
Instruction $2101 The parameters are 1.Check if any abnormal value is set
error erroneous. for the instruction parameter in
(Note) question.
$2102 The data is 1.Check if any abnormal value, such
erroneous. as one based on division by 0, is
set in the instruction parameter.
$2103 There is an error in 1.It is likely that an illegal value
BIN-to-BCD or has been set in BIN-to-BCD or
BCD-to-BIN BCD-to-BIN conversion. Check the
conversion. parameter where the error has
occurred.
$2104 There is an error in 1.Check if more data values have
the pointers of the been written to the FIFO table than
FIFO table. can be accepted by the table.
2.Check if an attempt has been
made to read data values from the
FIFO table when there is none.
3.Check if the default settings of the
FIFO table are correct. Also check
if the table has been destroyed in
any other part of the program.
$2105 The value defining a 1.Check if there is any error in the
boundary between values of index registers or in the
devices has been parameters defining the number of
exceeded. devices in an instruction for globally
rewriting multiple devices, such as a
BMOV block transfer instruction.
TA080203.EPS

A8-6
Turns Error
on Codes, Etc.
Moderate Instruction M201 Z022 to $2106 The FOR-NEXT loop 1.Check if there is such an error as a
failure error Z024 is not consistent. jump out of or into the FOR-NEXT
(Note1) loop.
2.Check if a scan timeout has been
detected within the FOR-NEXT
loop.
I/O M202 Z027 to $2401 ¥ The condition of Application failure 1.It is likely that there is a mismatch
collation Z029 module installation between the X and Y I/O relay
failure is not consistent devices specified in the program
(Note) with the program. and those contained in the installed
¥ The number of I/O module. Check if the instruction
HRD/HWR parameter in question is consistent
instructions has with the installed I/O module.
exceeded the limit 2.Check if the number of each of the
(error code:$2401). HRD and HWR instructions has
exceeded 64.
$2402 $2402 1.It is likely that there is a mismatch
(READ/ (READ/WRITE) between the slot number in
WRITE) HRD/HWR instructions used in the
program and that of the installed I/O
module. Check if the instruction
parameter in question is consistent
with the installed I/O module.
$2403 $2403 1.It is likely that there is a mismatch
(READ/ (READ/WRITE) between the slot number in
WRITE) READ/WRITE instructions used in
the program and that of the
installed I/O module. Check if the
instruction parameter in question is
consistent with the installed I/O
module.
I/O M203 Z033 to - ¥ It is not possible to 1.Check if the subunit is turned off.
failure Z040 read from or write 2.Check if there is any problem with
(Note) to the I/O module. the cable of the fiber-optic FA-bus
¥ There is a module.
communication 3.Do not reset the CPUs individually.
failure in the fiber- Reset them all at once from the
optic FA-bus main CPU.
module. 4.The I/O module may be defective.
¥ An attempt has Replace it.
been made to reset
a remote CPU in a
multi-CPU system.
TA080204.EPS

A8-7
Turns Error
on Codes, Etc.
Moderate Scan M204 - - The scan time Application failure 1.Check if the repetition-counter
failure timeout monitoring time has values of the FOR-NEXT loop are
(Note) been exceeded. correct.
2.Check if the FOR-NEXT loop has
been mistakenly turned into an
endless loop by JMP instructions.
3.Adjust the scan time monitoring
time according to the execution
time of the application program.
Failure in M210 Z089 to - It is not possible to Open-circuited 1.Check if the subunit is turned off.
subunit Z096 read from or write to cable 2.Check if there is any problem with
transmission the subunit. Loss of power to the cable of the fiber-optic FA-bus
line subunit module.
(Note) Hardware failure 3.The fiber-optic FA-bus module may
be defective. Replace it.
Minor Moment M195 - - The CPU indicates 1.If this failure mode occurs too
failure ary that a momentary frequently, check the power supply
power power failure has for possible problems. If a UPS is
failure occurred. in use, check that it has captured
peak values of its supply voltage
waveform. If the failure still occurs
frequently while there is no problem
with the waveform, it is likely that
the power supply module and/or
CPU module is defective. Replace
it.
Note: For this failure mode, you can determine whether to stop or continue program execution. TA080205.EPS

A8-8
Turns Error
on Codes, Etc.
Minor CPU-to-CPU M196 - - There is a Hardware failure 1.It is likely that there is a failure in
failure communication communication remote CPUs in a multi-CPU
failure failure in the shared system. Do not reset the CPUs
devices. individually. Reset them all at once
from the main CPU. If this failure
mode recurs, replace the CPU
modules.
Switchover in M211 Z089 to - There is a problem Open-circuited 1.Check if there is any problem with
subunit Z096 with the twisted-pair cable the cable of the fiber-optic FA-bus
transmission cables attached to module.
line 2.The fiber-optic FA-bus module may
be defective. Replace it.
TA080206.EPS
CAUTION
The failure mode “switchover in subunit transmission line” is effective for the Rev.8 or later
You can clear the CPU memory and revert it back to its factory settings by installing the
sequence CPU module in the 5th or later slot of the main unit and turning it on. If the failure
is a transient memory failure due to effects of noise, download the application program
again to allow memory reuse. If the failure recurs, there may be a hardware failure.
Replace the sequence CPU module.
See Also
Fiber-optic FA-bus Module and Fiber-optic FA-bus Type 2 Module Instruction Manual
(IM34M6H45-01E), for more information on the failure modes “failure in subunit
transmission line” and “switchover in subunit transmission line.”

A8-9
A8.1.1 Setting Operation Mode in Case of Failure and External

Output Mode in Case of Sequence Stop
■ Setting Operation Mode in Case of Failure

Using the configuration function, determine whether to stop (for moderate failures) or
continue (for minor failures) executing sequence programs in case of such a fault as an
instruction processing failure. The table below summarizes the configuration items and
their defaults. If a failure for which you have selected the Continue option actually occurs,
the CPU fails to correctly perform such tasks as accessing the I/O module that caused the
failure or processing instructions.
Configuration Item Default

I/O module failure
I/O collation failure
Instruction processing error
Stop (for moderate failures)
Scan time-out
Subroutine error
Interrupt error
Failure in subunit transmission line Continue (for minor failures)
TA080104.EPS
CAUTION
Use the R1.08 or later version of Ladder Diagram Support Program M3 to edit the
configuration item “Failure in Subunit Transmission Line.” This item is effective for the Rev.8
or later version of the F3SP21, F3SP25 and F3SP35 sequence CPU modules.
See Also
Fiber-optic FA-bus Module and Fiber-optic FA-bus Type 2 Module Instruction Manual
(IM34M6H45-01E), for more information on the failure modes “failure in subunit
transmission line” and “switchover in subunit transmission line.”

A8-10
A8.2 Recovering Normal Operation after Correcting

Moderate/Minor Failures
After eliminating the cause of a moderate or minor failure, initialize the states of special
relays, special registers and LED indicators as instructed below.
■ Recovery after Correcting Moderate Failures

After correcting any moderate failure, reset the special relays and special registers and turn
off the ERR indicator lamp by:
• turning on the power again, and
• setting the sequence CPU in the Run or Debug mode using the programming tool.
■ Recovery after Correcting Minor Failures

After correcting any minor failure, reset the special relays and special registers and turn off
the ALM indicator lamp by:
• turning on the power again,
• setting the sequence CPU in the Run or Debug mode using the programming tool,
and
• performing an “alarm acknowledgement.”

Toc-B1

PART B for CPU module designed for the
FA-M3 Value system (F3SP05-0P)
CONTENTS
B1. Specification and Basic Configuration ................................................ B1-1
B1.1 Overview ........................................................................................................ B1-1
B1.2 Specification ................................................................................................. B1-3
B1.2.1 Performance Data ........................................................................... B1-3
B1.2.2 Device List ...................................................................................... B1-5
B1.2.3 Configuration .................................................................................. B1-6
B1.2.4 Components and Their Functions ................................................... B1-8
B1.2.5 External Dimensions ....................................................................... B1-9
B1.3 Basic Configuration .................................................................................... B1-10
B1.3.1 Units ............................................................................................. B1-10
B1.3.2 Slot Number ................................................................................. B1-11
B1.3.3 I/O Relay Number ......................................................................... B1-11
B2. System Configuration .......................................................................... B2-1
B2.1 Basic System Configuration ........................................................................ B2-1
B2.2 Extended System Configuration .................................................................. B2-2
B2.2.1 Remote I/O System ........................................................................ B2-2
B2.2.2 Personal Computer Link System ..................................................... B2-3
B2.2.3 FA Link System ............................................................................... B2-3
B2.3 Programming Tools ....................................................................................... B2-4
B2.3.1 WideField ....................................................................................... B2-4
B2.3.2 Ladder Diagram Support Program M3 ............................................ B2-6

Blank Page
B1-1
B1. Specification and Basic Configuration

This chapter explains the specification of the F3SP05-0P sequence CPU module
designed for the FA-M3 Value system (Model F3SC21-1N Controller) and the
system’s basic configuration.
B1.1 Overview
■ Overview
Model F3SP05-0P is a sequence CPU module with a built-in power supply and memory
and is used to configure the FA-M3 Value system. The built-in power supply is functionally
equivalent to the F3PU10-0N power supply module. The sequence CPU is also
functionally equivalent to the F3SP21-0N except for the CPU’s 5K-step program size. This
chapter focuses on the CPU of the F3SP05-0P module. For details on the power supply
block of the module, refer to the part “FA-M3 Value (Model F3SC21-1N)” of Hardware
Manual (IM34M6C11-01E).
For further details on instructions available with the F3SP05-0P module, refer to the
F3SP21’s Sequence CPU Instruction Manual - Instructions (IM34M6P12-03E), as such
specifications as device sizes and instructions available with the F3SP05-0P are the same
as those of the F3SP21 sequence CPU module.
CAUTION
The R2.02 or a later version of Ladder Diagram Support Program M3 is required to use the
F3SP05-0P sequence CPU module.
■ Features
• Support for high-speed processes and responses of the module’s maximum
instruction processing speed.
maintenance.
• Provides various functions, e.g., a forced SET/RESET function and scan operation
independent of program computation results, for easy program debugging and
maintenance.
link function.

B1-2
store programs.
■ Major Functions
latched in case of power failure, and external output to be retained in case of
sequence stop)
• Debugging (forced SET/RESET instructions, online editing, scan operation, etc.)
* See Section B1.2, “Specification,” for more information.

B1-3
B1.2 Specification
B1.2.1 Performance Data
Table B1.1 Performance Data (1 of 2)
Item Specifications
Number of I/O points 2048 max.
Number of internal relays (I) 4096
Number of extended shared relays (E) 0
Number of link relays (L) 2048
Number of special relays (M) 2048
Number of timers (T) 256
Number of counters (C) 256
Number of data registers (D) 5120
Number of extended shared registers (R) 0
Number of file registers (B) 0
Number of link registers (W) 2048
Number of special registers (Z) 256
Number of labels 64
Number of interruption processing routines 4*

Decimal constant



TB010201.EPS
* The inputs of F3WD32-3F cannot be used as interrupt inputs.

B1-4
Table B1.1 Performance Data (2 of 2)
Item Specifications
Program size 10 K steps max., ROM-able
Number of program blocks 32 max.

instructions Application instruction 227
Instruction Basic instruction 0.18 to 0.36 µs/instruction

execution time Application instruction 0.36µs min./instruction
Sampling trace function Not available.
User logging function Available.

Available.
Number of personal computer link modules 2 max.
Macro instruction function Not available
Automatic

Self-diagnosis Detection of memory failure,CPU failure and I/O module failure,syntax checking,etc.
Link function FA link,personal computer link,and remote I/O link (fiber-optic FA-bus,
fiber-optic FA-bus Type 2)
• Online editing
Other functions be latched in case of power failure, and external outputs to be latched in case
of sequence stop)
TB010202.EPS

B1-5
B1.2.2 Device List

Table B1.2 Device List
Device Code Range Quantity Remarks
Input relay X00201 to X71664

X (discontinuous)
2048 The range to be used differs
Y00201 to Y71664 depending on the module type.
Output relay Y (discontinuous)
Internal relay I I00001 to I4096 4096

Shared relay E – 0 Not available.
Non- L0001 to L11024
Link relay latching L 2048
(discontinuous)
type
Special relay M M0001 to M2048 2048
1-ms timer – 0 Max. 16 points can be set.
Timer
10-ms timer T T001 to T128 128 Correlative with counters (C) in
100-ms timer T129 to T240 112 terms of configuration limitations.
Con-
tinuous 100-ms timer T241 to T256 16
timer
Latching Correlative with counters (T) in
Counter type C C001 to C256 256 terms of configuration limitations.
Latching
Data register type D D0001 to D5120 5120
File register B – 0 Not available.

Non-
Link register latching W00001 to W11024
W (discontinuous) 2048 Used for FA link communication.
type
Special register Z Z001 to Z512 512
Index register V V01 to V32 32
Shared register R – 0 Not available.
TB010203.EPS

B1-6
B1.2.3 Configuration
The sequence CPU contains the predefined defaults of device sizes and operation meth-
ods.
You can run programs with these defaults. In some applications, however, they may not suit
your specific purpose. In such a case, flexibility allows for defaults to be changed to meet
your needs. Changing the defaults is called "configuration" and can be performed through
a programming tool.
Table B1.3 Configuration Ranges (1 of 2)
Item Default Configuration Range
Internal relay (I) 4096 –
Shared relays (E) 0 –
Timer (T) 256 512 units in 1 point increments
Device for timers and counters com-
size Counter (C) 256
Data register (D) 5120
–
Shared registers (R) 0
1-ms timer 0
Timer 10-ms timer 128 Configurable in 1 point incre-
ments;
100-ms timer 112 16 units max. for 1-ms timers;
100-ms continuous timer 16
Link relay (L) 32 units for each station Configurable in16 points incre-
ments for each link
Range
of link Configurable in 1 point incre-
relays/ Link register (W) 32 units for each station ments for each link
registers
Link relays (L)/ Configurable in 16 points
Range of link data increments for each link module
registers (W)
(2 modules max.)
Configurable in 32 points
Internal relay (I) I0001 to I1024 increments; continuous from the
starting number
Link relay (L) Non-latching type increments; continuous from the
Range of starting number
devices Configurable in 1 point
to be Timer (T) Non-latching type increments; continuous from the
latched (except for continuous timers) starting number
in case Configurable in 1 point
of power All latched
Counter (C) (C001 to C256) increments; continuous from the
failure starting number
All latched
Data register (D) (D0001 to D5120) Configurable in 2 points
increments; continuous from the
starting number
Link register (W) Non-latching type
TB010204.EPS

B1-7
Table B1.3 Configuration Ranges (2 of 2)

Configurable for up to 1024 points
Initial data Data register (D) None continuously from the starting
number
Scan time monitoring time 200 ms Configurable from 10 to 200 ms

in 10 ms increments
Configurable from 1.0 to 190.0 ms
Constant scan time Normal scan in 0.1 ms increments
I/O module failure Stop
I/O collation failure Stop
Ope-
ration Instruction processing failure Stop
mode in Scan timeout Stop Selectable from Stop and
case of Continue options.
failure Subroutine error Stop
Interrupt error Stop
Subunit transmission line failure Continuation
Selectable from Retained/Not
Output mode in case of sequence stop OFF Retained options on a module
basis
BIN/BCD; configurable in 16
Data code type BIN points increments
I/O
module
16 ms 16 ms/1 ms; configurable in 16
Input sampling interval points increments
Devices'
current
values to Configurable for up to 5120 points
Data and file registers None continuously from the starting
be made
resident number
in ROM
Program execution mode All blocks All blocks/Specified blocks
Momentary power failure detection

mode Standard mode Standard mode
CPU
commu- Mode 0: 9600 bps, even parity
Mode 0: 9600 bps, Mode 1: 9600 bps, non parity
nication Mode even parity
port Mode 2: 19200 bps, even parity
Used/unused Unused Unused/Used

Personal
computer Check sum None Yes/No
link func- Terminal character selection
tion None Yes/No
Protection function None Yes/No
Relationship between FA link Related/Not related
numbers and slot numbers None Between each FA link number
and slots 1 to 16
Note: For more information on configuration when FA link H and/or fiber-optic FA link H modules are used,
see Section A4.3, "Link Relays and Link Registers," of Chapter A4, "Devices," in the main part of this
instruction manual and FA Link H Module F3LP02-0N Fiber-optic FA Link H Modules F3LP12-0N
(IM34M6H43-01E). TB010205.EPS

B1-8
B1.2.4 Components and Their Functions

This subsection describes the LED indicators, their states, and the programming tool
connector on the front side of the sequence CPU module.
Table B1.4 summarizes combinations of the LED indicators as classified by the severity of failure.

SP0-0N CPU RDY (= READY, green) --------------------On = Normal
Off = Major failure
Off = Normal
Off = Normal


function is in use.
FB010201.EPS
Table B1.4 LED Indicator Combinations Based on the Severity of Failure

Normal
RDY On Off On On
RUN On Off Off On
ERR Off On On Off
TB010207.EPS

B1-9
B1.2.5 External Dimensions

F3SP05-0P Unit:mm
83.2 58
2
100
FB010202.EPS

B1-10
B1.3 Basic Configuration

B1.3.1 Units
■ Main Unit
In the case of the FA-M3 Value system, the F3SC21-1N controller is called a main unit and
consists of the following modules.
• F3BU04-0N base module
• F3SP05-0P sequence CPU module with power supply and memory
• F3WD64-3N I/O module
Install the F3SP05-0P sequence CPU module in the leftmost slot of the F3BU04-0N base
module and the F3WD64-3N I/O module in slot 2. In the remaining third and fourth slots,
install other necessary I/O modules or special modules.
■ Subunit
A unit that contains no CPU modules and is connected to the main unit through a fiber-optic
FA-bus or fiber-optic FA-bus type 2 is called a subunit. The subunit consists of the modules
listed in Table B1.5. A maximum of seven subunits can be connected to the main unit and
are identified by their unit numbers.
Table B1.5 Subunit Components
Name Description
At least one CPU module is required. Several types are available depending
CPU module on the functionality.
TB010301.EPS

B1-11
B1.3.2 Slot Number

Slot number

Unit number
Main unit = 0
Subunit = 1 to 7
FB010301.EPS
Figure B1.1 Slot Numbers
B1.3.3 I/O Relay Number

Each input relay (X) and output relay (Y) number is defined as a slot number followed by a
terminal number. The terminal number is a number corresponding to each terminal of an I/
O module.
Y004 06
Terminal number
Slot number
001 002 003 004 Slot numbers
Y 08- OUT
Output relay number

Y00406
F3YC08-0N
FB010302.EPS
Figure B1.2 I/O Relay Number
The input and output terminal numbers of a mixed-I/O module or multifunctional module
with 32 input and output points each are assigned as 1 to 32 and as 33 to 64, respectively.

Blank Page
B2-1
B2. System Configuration

This chapter describes the configuration of a small-scale control system and pro-
gramming tools.
B2.1 Basic System Configuration

The basic system configuration only refers to a system consisting of a main unit. For more
information on the main unit, see subsection B1.3.1, "Units."
FB020101.EPS
Figure B2.1 Example of Basic System Configuration

B2-2
B2.2 Extended System Configuration

B2.2.1 Remote I/O System


Main unit
Subunit
Fiber-optic cable
FB020202.EPS
Figure B2.2 Example of System Using Fiber-optic FA-bus Type 2 Modules

B2-3
B2.2.2 Personal Computer Link System

sequence CPU module can be connected directly to a personal computer or a monitor
through the module's programming port.

with PC interface
Main unit

FB020203.EPS
Figure B2.3 Example of Personal Computer Link System
B2.2.3 FA Link System

The combinations of the types of communication and associated modules covered by an
FA link system are:
FA link H communication and FA link H module
Fiber-optic FA link H communication and fiber-optic FA link H module
communication. For more information on the FA link, see FA Link H Module F3LP02-0N
Fiber-optic FA Link H Module F3LP12-0N (IM34M6H43-01E).
FA link

FB020204.EPS
Figure B2.4 Example of FA Link System

B2-4
B2.3 Programming Tools

The FA-M3 Programming Tool WideField and Ladder Diagram Support Program M3 are
available as programming tools for the F3SP05-0P sequence CPU module.
B2.3.1 WideField

F3SP05 F3SP38
F3SP21 F3SP53
FA-M3 Programming Tool WideField SF610-JCW F3SP25 F3SP58
F3SP28 F3FP36
F3SP35
TB020301.EPS
Personal computer
Sequence CPU module

FB020301.EPS
Figure B2.5 Overview of WideField
■ Object Ladder
WideField defines "blocks" and "macros" that compose a ladder program as "objects," a
term commonly used in the computing world. The object-oriented ladder language
assumes responsibility for a given function and features a high degree of independence.
Consequently, the language offers higher productivity and better maintainability than a
structured programming language. It is therefore effective for the reuse of ladder programs.
■ Features
Blocks can be reused as sheer components. Devices that are used only within a block are
defined separately. WideField eliminates the chance of using the same device twice and
makes it easy to recombine blocks.

B2-5
● Index View
part. This makes debugging more efficient

• •
I*****
+ •
CAL = •
•
I*****
• Material feed
Flux coating
Fixation heating
Cooling CAL = +
I***** I***** Y*****

Unloading I*****
MOVE
I***** I***** I***** •
+
CAL =
Flux coating
•
I***** Finish coat
MOVE
Cleaning
Fault-diagnosis
. I***** I***** I***** Y*****
Power-off sequence
Unloading
•
I***** I***** Y***** •
•
I***** I***** I***** Y*****
Fault-diagnosis
I***** Y*****
Power-off sequence
FB020302.EPS
● Group Signal Names

You can change the method of naming signals from an "individual basis" to a "group basis."
This enables you to define a set of data.

MCN1
MCN3
FB020303.EPS

You can pick data items, such as device names and comments, in a Microsoft Excel

B2-6
B2.3.2 Ladder Diagram Support Program M3

The table below presents an overview of Ladder Diagram Support Program M3.
Description Software Model
Windows 95
MS-DOS version
Windows NT 4.0 version
Ladder Diagram Support Program M3
SF510-E3W SF510-E3P
TB020302.EPS
Ladder Diagram Support Program M3, supports both ladder diagram input and mnemonic
input for higher programming efficiency. In addition, its wide choice of debugging functions
reduces the amount of time required for tuning work. Since this programming tool runs on a
personal computer, there is no need for any dedicated programming console.
X00503 X00504 Y00602
Personal X00501 X00502 Y00601

computer
X00503
Sequence CPU module

FB020304.EPS
Figure B2.7 Ladder Diagram Support Program M3
CAUTION
The R2.02 or a later version of Ladder Diagram Support Program M3 is required to use the

Toc-C1

PART C for CPU module designed for the
FA-M3 Value II system (F3SP08-0P)
CONTENTS
C1. Specification and Basic Configuration ................................................ C1-1
C1.1 Overview ........................................................................................................ C1-1
C1.2 Specification ................................................................................................. C1-3
C1.2.1 Performance Data ........................................................................... C1-3
C1.2.2 Device List ...................................................................................... C1-5
C1.2.3 Configuration .................................................................................. C1-6
C1.2.4 Components and Their Functions ................................................... C1-8
C1.2.5 External Dimensions ....................................................................... C1-9
C1.3 Basic Configuration .................................................................................... C1-10
C1.3.1 Units ............................................................................................. C1-10
C1.3.2 Slot Number ................................................................................. C1-11
C1.3.3 I/O Relay Number ......................................................................... C1-11
C2. System Configuration .......................................................................... C2-1
C2.1 Basic System Configuration ........................................................................ C2-1
C2.2 Extended System Configuration .................................................................. C2-2
C2.2.1 Remote I/O System ........................................................................ C2-2
C2.2.2 Personal Computer Link System ..................................................... C2-3
C2.2.3 FA Link System ............................................................................... C2-3
C2.3 Programming Tools ....................................................................................... C2-4
C2.3.1 WideField ....................................................................................... C2-4

Blank Page
C1-1
C1. Specification and Basic Configuration

This chapter explains the specification of the F3SP08-0P sequence CPU module
designed for the FA-M3 Value system (Model F3SC22- Controller) and the
system’s basic configuration.
C1.1 Overview
■ Overview
Model F3SP08-0P is a sequence CPU module with a built-in power supply and memory
and is used to configure the FA-M3 Value II system. The built-in power supply is function-
ally equivalent to the F3PU10-0N power supply module. The sequence CPU is also func-
tionally equivalent to the F3SP21-0N. This chapter focuses on the CPU of the F3SP08-0P
module. For details on the power supply block of the module, refer to the part “FA-M3 Value
II (Model F3SC22-)” of Hardware Manual (IM34M6C11-01E).
For further details on instructions available with the F3SP08-0P module, refer to the
F3SP21’s Sequence CPU Instruction Manual - Instructions (IM34M6P12-03E), as such
specifications as device sizes and instructions available with the F3SP08-0P are the same
as those of the F3SP21 sequence CPU module.
CAUTION
The R2.06 or a later version of FA-M3 Programming Tool WideField is required to use the
■ Features
• Support for high-speed processes and responses of the module’s maximum instruc-
tion processing speed.
maintenance.
• Provides various functions, e.g., a forced SET/RESET function independent of
program computation results, for easy program debugging and maintenance.
link function.

C1-2
store programs.
■ Major Functions
latched in case of power failure, and external output to be retained in case of se-
quence stop)
• Debugging (forced SET/RESET instructions, online editing, etc.)
* See Section C1.2, “Specification,” for more information.

C1-3
C1.2 Specification
C1.2.1 Performance Data
Table C1.1 Performance Data (1 of 2)
Item Specifications
Number of I/O points 2048 max.
Number of internal relays (I) 4096
Number of extended shared relays (E) 0
Number of link relays (L) 2048
Number of special relays (M) 2048
Number of timers (T) 256
Number of counters (C) 256
Number of data registers (D) 5120
Number of extended shared registers (R) 0
Number of file registers (B) 0
Number of link registers (W) 2048
Number of special registers (Z) 256
Number of labels 64
Number of interruption processing routines 4*

Decimal constant



TC010201.EPS
* The inputs of F3WD32-3F cannot be used as interrupt inputs.

C1-4
Table C1.1 Performance Data (2 of 2)
Item Specifications
Program size 10 K steps max., ROM-able
Number of program blocks 32 max.

instructions Application instruction 227
Instruction Basic instruction 0.18 to 0.36 µs/instruction

execution time Application instruction 0.36µs min./instruction
Sampling trace function Not available.
User logging function Available.

Available.
Number of personal computer link modules 2 max.
Macro instruction function Not available
Automatic

Self-diagnosis Detection of memory failure,CPU failure and I/O module failure,syntax checking,etc.
Link function FA link,personal computer link,and remote I/O link (fiber-optic FA-bus,
fiber-optic FA-bus Type 2)
• Online editing
Other functions be latched in case of power failure, and external outputs to be latched in case
of sequence stop)
TC010202.EPS

C1-5
C1.2.2 Device List

Table C1.2 Device List
Device Code Range Quantity Remarks
Input relay X00201 to X71664

X (discontinuous)
2048 The range to be used differs
Y00201 to Y71664 depending on the module type.
Output relay Y (discontinuous)
Internal relay I I00001 to I4096 4096

Shared relay E – 0 Not available.
Non- L0001 to L11024
Link relay latching L 2048
(discontinuous)
type
Special relay M M0001 to M2048 2048
1-ms timer – 0 Max. 16 points can be set.
Timer
10-ms timer T T001 to T128 128 Correlative with counters (C) in
100-ms timer T129 to T240 112 terms of configuration limitations.
Con-
tinuous 100-ms timer T241 to T256 16
timer
Latching Correlative with counters (T) in
Counter type C C001 to C256 256 terms of configuration limitations.
Latching
Data register type D D0001 to D5120 5120
File register B – 0 Not available.

Non-
Link register latching W00001 to W11024
W (discontinuous) 2048 Used for FA link communication.
type
Special register Z Z001 to Z512 512
Index register V V01 to V32 32
Shared register R – 0 Not available.
TC010203.EPS

C1-6
C1.2.3 Configuration
The sequence CPU contains the predefined defaults of device sizes and operation meth-
ods.
You can run programs with these defaults. In some applications, however, they may not suit
your specific purpose. In such a case, flexibility allows for defaults to be changed to meet
your needs. Changing the defaults is called "configuration" and can be performed through
a programming tool.
Table C1.3 Configuration Ranges (1 of 3)
Internal relay (I) 4096 –
Shared relays (E) 0 –
Timer (T) 256 512 units in 1 point increments
Device for timers and counters com-
size Counter (C) 256
Data register (D) 5120
–
Shared registers (R) 0
1-ms timer 0
Timer 10-ms timer 128 Configurable in 1 point incre-
ments;
100-ms timer 112 16 units max. for 1-ms timers;
100-ms continuous timer 16
Link relay (L) 32 units for each station Configurable in16 points incre-
ments for each link
Range
of link Configurable in 1 point incre-
relays Link register (W) 32 units for each station ments for each link
/registers
Link relays (L)/ Configurable in 16 points
Range of link data increments for each link module
registers (W)
(2 modules max.)
Internal relay (I) I0001 to I1024 increments; continuous from the
starting number
Link relay (L) Non-latching type increments; continuous from the
Range of starting number
devices Configurable in 1 point
to be Timer (T) Non-latching type increments; continuous from the
latched (except for continuous timers) starting number
in case Configurable in 1 point
of power All latched
Counter (C) (C001 to C256) increments; continuous from the
failure starting number
All latched
Data register (D) (D0001 to D5120) Configurable in 2 points
increments; continuous from the
starting number
Link register (W) Non-latching type
TC010204.EPS

C1-7
Table C1.3 Configuration Ranges (2 of 3)
Configurable for up to 1024 points
Initial data Data register (D) None continuously from the starting
number
Scan time monitoring time 200 ms Configurable from 10 to 200 ms

in 10 ms increments
Configurable from 1.0 to 190.0 ms
Constant scan time Normal scan in 0.1 ms increments
I/O module failure Stop
I/O collation failure Stop
Ope-
ration Instruction processing failure Stop
mode in Scan timeout Stop Selectable from Stop and
case of Continue options.
failure Subroutine error Stop
Interrupt error Stop
Subunit transmission line failure Continuation
Selectable from Retained/Not
Output mode in case of sequence stop OFF Retained options on a module
basis
BIN/BCD; configurable in 16
Data code type BIN points increments
I/O
module
16 ms 16 ms/1 ms; configurable in 16
Input sampling interval points increments
Devices’
current
values to Configurable for up to 5120 points
Data and file registers None continuously from the starting
be made
resident number
in ROM
Program execution mode All blocks All blocks/Specified blocks
Momentary power failure detection

mode Standard mode Standard mode
CPU
commu- Mode 0: 9600 bps, even parity
Mode 0: 9600 bps, Mode 1: 9600 bps, non parity
nication Mode even parity
port Mode 2: 19200 bps, even parity
Used/unused Unused Unused/Used

Personal
computer Check sum None Yes/No
link func- Terminal character selection
tion None Yes/No
Protection function None Yes/No
Relationship between FA link Related/Not related
numbers and slot numbers None Between each FA link number
and slots 1 to 16
Note: For more information on configuration when FA link H and/or fiber-optic FA link H modules are used,
see Section A4.3, "Link Relays and Link Registers," of Chapter A4, "Devices," in the main part of this
instruction manual and FA Link H Module F3LP02-0N Fiber-optic FA Link H Modules F3LP12-0N
(IM34M6H43-01E). TC010205.EPS

C1-8
C1.2.4 Components and Their Functions

This subsection describes the LED indicators, their states, and the programming tool
connector on the front side of the sequence CPU module.
Table C1.4 summarizes combinations of the LED indicators as classified by the severity of failure.

SP08-0P CPU RDY (= READY, green) --------------------On = Normal
Off = Major failure
Off = Normal
Off = Normal


function is in use.
FC010201.EPS
Table C1.4 LED Indicator Combinations Based on the Severity of Failure

Normal
RDY On Off On On
RUN On Off Off On
ERR Off On On Off
TC010207.EPS

C1-9
C1.2.5 External Dimensions

F3SP08-0P Unit:mm
83.2 58
2
100
FC010202.EPS

C1-10
C1.3 Basic Configuration

C1.3.1 Units
■ Main Unit
In the case of the FA-M3 Value II system, the F3SC22- controller is called a main unit
and consists of the following modules.
• F3BU04-0N base module
• F3SP08-0P sequence CPU module with power supply and memory
• F3WD32-3F I/O module
• F3WD64-3F I/O module
• F3XD16-3F input module
• F3YD14-5A output module
Install the F3SP08-0P sequence CPU module in the leftmost slot of the F3BU04-0N base
module and the other I/O modules in slot 2 (or slots 2 and 3). In the remaining third and
fourth slots (or only slot 4), install other necessary I/O modules or special modules.
001 002 003 004

I/O Module
I/O Module
Main Unit
F3WD32
F3SP08
F3SC22-1F
001 002 003 004

I/O Module
I/O Module
Main Unit
F3WD64
F3SP08
F3SC22-2F
001 002 003 004

I/O Module
Main Unit
F3XD16
F3YD14
F3SP08
F3SC22-1A
■ Subunit
A unit that contains no CPU modules and is connected to the main unit through a fiber-optic
FA-bus or fiber-optic FA-bus type 2 is called a subunit. The subunit consists of the modules
listed in Table C1.5. A maximum of seven subunits can be connected to the main unit and
are identified by their unit numbers.
Table C1.5 Subunit Components
Name Description
TC010301.EPS

C1-11
C1.3.2 Slot Number

Slot number

Unit number
Main unit = 0
Subunit = 1 to 7
FC010301.EPS
Figure C1.1 Slot Numbers
C1.3.3 I/O Relay Number

Each input relay (X) and output relay (Y) number is defined as a slot number followed by a
terminal number. The terminal number is a number corresponding to each terminal of an
I/O module.
Y004 06
Terminal number
Slot number
001 002 003 004 Slot numbers
Y 08- OUT
Output relay number

Y00406
F3YC08-0N
FC010302.EPS
Figure B1.2 I/O Relay Number
The input terminal numbers of F3WD64- are assigned as 1 to 32 and the output
terminal numbers assigned as 33 to 64;
The input terminal numbers of F3WD32- are assigned as 1 to 16 and the output
terminal numbers are assigned as 17 to 32.

Blank Page
C2-1
C2. System Configuration

This chapter describes the configuration of a small-scale control system and
programming tools.
C2.1 Basic System Configuration

The basic system configuration only refers to a system consisting of a main unit. For more
information on the main unit, see subsection C1.3.1, "Units."
FC020101.EPS
Figure C2.1 Example of Basic System Configuration

C2-2
C2.2 Extended System Configuration

C2.2.1 Remote I/O System


Main unit
Subunit
Fiber-optic cable
FC020202.EPS
Figure C2.2 Example of System Using Fiber-optic FA-bus Type 2 Modules

C2-3
C2.2.2 Personal Computer Link System

sequence CPU module can be connected directly to a personal computer or a monitor
through the module's programming port.

with PC interface
Main unit

FC020203.EPS
Figure C2.3 Example of Personal Computer Link System
C2.2.3 FA Link System

The combinations of the types of communication and associated modules covered by an
FA link system are:
FA link H communication and FA link H module
Fiber-optic FA link H communication and fiber-optic FA link H module
communication. For more information on the FA link, see FA Link H Module F3LP02-0N
Fiber-optic FA Link H Module F3LP12-0N (IM34M6H43-01E).
FA link

FC020204.EPS
Figure C2.4 Example of FA Link System

C2-4
C2.3 Programming Tools

The FA-M3 Programming Tool WideField and Ladder Diagram Support Program M3 are
available as programming tools for the F3SP05-0P sequence CPU module.
C2.3.1 WideField

F3SP05 F3SP35
F3SP08 F3SP38
FA-M3 Programming Tool WideField SF610-JCW F3SP21 F3SP53
F3SP25 F3SP58
F3SP28 F3FP36
TB020301.EPS
Personal computer
Sequence CPU module

FC020301.EPS
Figure C2.5 Overview of WideField
CAUTION
The R2.04 or a later version of FA-M3 Programming Tool WideFild is required to use the
■ Object Ladder
WideField defines "blocks" that compose a ladder program as "objects," a term commonly
used in the computing world. The object-oriented ladder language assumes responsibility
for a given function and features a high degree of independence. Consequently, the lan-
guage offers higher productivity and better maintainability than a structured programming
language. It is therefore effective for the reuse of ladder programs.
■ Features
Blocks can be reused as sheer components. Devices that are used only within a block are
defined separately. WideField eliminates the chance of using the same device twice and
makes it easy to recombine blocks.

C2-5
● Index View
part. This makes debugging more efficient

• •
I*****
+ •
CAL = •
•
I*****
• Material feed
Flux coating
Fixation heating
Cooling CAL = +
I***** I***** Y*****

Unloading I*****
MOVE
I***** I***** I***** •
+
CAL =
Flux coating
•
I***** Finish coat
MOVE
Cleaning
Fault-diagnosis
. I***** I***** I***** Y*****
Power-off sequence
Unloading
•
I***** I***** Y***** •
•
I***** I***** I***** Y*****
Fault-diagnosis
I***** Y*****
Power-off sequence
FC020302.EPS
● Group Signal Names

You can change the method of naming signals from an "individual basis" to a "group basis."
This enables you to define a set of data.

MCN1
MCN3
F040403.EPS

You can pick data items, such as device names and comments, in a Microsoft Excel

Blank Page
Toc-1

This appendix provides lists of special devices, as well as the formats of

documentation you will use when designing your system. These formatted
sheets can be conveniently copied for use as standard forms in your system
design. There are four forms, as shown in the table of contents below.
CONTENTS
Appendix 1. Special Relays (M) .................................................................App.1-1
Appendix 1.1 Block Start Status ........................................................................... App.1-1
Appendix 1.2 Utility Relays ................................................................................... App.1-2
Appendix 1.3 Sequence Operation and Mode Status Relays ............................. App.1-4
Appendix 1.4 Self-diagnosis Status Relays ......................................................... App.1-5
Appendix 1.5 FA Link Module Status Relays ....................................................... App.1-7
Appendix 2. Special Registers (Z) .............................................................App.2-1
Appendix 2.1 Sequence Operation Status Registers .......................................... App.2-1
Appendix 2.2 Self-diagnosis Status Registers .................................................... App.2-2
Appendix 2.3 Utility Registers .............................................................................. App.2-4
Appendix 2.4 FA Link Module Status Registers .................................................. App.2-5
Appendix 2.5 CPU Module Status Registers ....................................................... App.2-6
Appendix 3. Forms for System Design .....................................................App.3-1
■ Program Coding Sheet ..................................................................................... App.3-1
■ Relay Devices Assignment Table ..................................................................... App.3-2
■ Register Devices Assignment Table ................................................................ App.3-3
■ Timer/Counter Setpoints Table ......................................................................... App.3-4

Blank Page
App.1-1
Appendix 1. Special Relays (M)

Special relays have specific functions, such as indicating the internal state of a CPU or
detecting errors. In programs, these relays are used mainly for contacts a and b.
Appendix 1.1 Block Start Status

Block start status relays indicate which block is running when the selected blocks are being
executed.
These relays are numbered in ascending order as M001, M002, . . ., to correlate with block
1, block 2, ...
Table Appendix 1.1 Block Start Status
Item Description
F3SP28,F3SP38,F3SP53,F3SP58 M001 to M0016 Block n start ON : Run Indicate whether block n
M0001 to M0032 status relay OFF : Stop is in progress or at a stop
F3SP21, F3SP25, when blocks are selected
F3SP35 (Note) and executed.
M2001 to M3024
Note: The start status relays assigned to blocks 1 to 32 are M0001 to M0032 and M2001 to M2032, where the
values of M0001 to M0032 are the same as those of M2001 to M2032. Similarly, start status relays M2033 to
M3024 are assigned to blocks 33 to 1024.
AP040401.EPS
CAUTION
Do not write to a special relay, including those not listed in the table above (e.g., M067 to
M128), unless otherwise stated. This is because they are used by the CPU module for the
system. If you inadvertently write to these relays, a failure such as a system shutdown may
occur. (The use of a forced set/reset instruction in debug mode is also prohibited.)

App.1-2
Appendix 1.2 Utility Relays

Utility relays are used to provide timing in a program or give instructions to the CPU.
Table Appendix 1.2 Utility Relays
Item Utility Relays
Always ON ON
M033
OFF Used for an initialization process or as a
dummy contact in a program.
Always OFF ON
M034
OFF
On-for-one-scan- Turns on for one scan only after the start

M035 1 scan of a program.
at-start-of-operation
Generates a clock pulse with a 0.01-sec

M036 0.01-sec clock 0.005s 0.005s
period.

M037 0.01s 0.01s
period.
0.1-sec clock 0.05s 0.05s Generates a clock pulse with a 0.1-sec

M038
period.

M039 0.1s 0.1s
period.

M040 1-sec clock 0.5s 0.5s
period.

M041 2-sec clock 1s 1s period.
30s 30s Generates a clock pulse with a 1-min

M042 1-min clock period.
1-ms clock 0.5s 0.5s Generates a clock pulse with a 1-msec

M047 period.
(Note)
2-ms clock 1ms 1ms Generates a clock pulse with a 2-msec

M048 period.
(Note)
Normal subunit ON: Normal transmission line or no fiber-optic FA-bus installed
M066 transmission line OFF: Unspecified or abnormal transmission line
On for one scan at CB ON: When the block starts. Turns on for one scan when the
M097 startup sensor control block starts (at the first
(Note) OFF: In all other cases.
execution of the sensor control block).
Note: Only available with the F3SP28, F3SP38, F3SP53 and F3SP58. AP010101.EPS

App.1-3
CAUTION
The utility relay M066 “normal subunit transmission line” is only available with the Rev.8 or
later version of the F3SP21, F3SP25 and F3SP35.
See Also
more information on the M066 utility relay (Normal Subunit Transmission Line).

App.1-4
Appendix 1.3 Sequence Operation and Mode Status

Relays
Sequence operation and mode status relays indicate the status of sequence operation or
each mode.
Table Appendix 1.3 Sequence Operation and Mode Status Relays
Item Sequence Operation and Mode Status Relays
Run mode flag ON: Run mode Indicates the status of CPU operation.
M129
OFF: Other modes
ON: Debug mode

M130 Debug mode flag Indicates the status of CPU operation.
OFF: Other modes
Stop mode flag ON: Stop mode Indicates the status of CPU operation.
M131
OFF: Other modes
Pause flag ON: Pause Indicates the status of program execution

M132
OFF: Program execution during debug mode operation.
Execution flag
ON: Specified blocks Indicates whether specified blocks or all
M133 (All blocks/
OFF: All blocks blocks are executed.
Specified blocks)
RAM/ROM-based ON: ROM-based operation Indicates whether operation is based on
M135 operation flag OFF: RAM-based operation the ROM or RAM.
M136 Power-on ON: Power-on operation Indicates whether the system has been
OFF: Other modes of put in run mode at power-on or by
(Note1) operation flag
operation resetting.
M137 ON: Start Indicates the status of sensor control
(Note2) CB execution status
OFF: Stop block execution.
M172 Time setting ON: Time being set

(write-enabled) Requests to set clock data
OFF:
ON: Offline Indicates that input refreshing has

M173 Input-off-line flag stopped.
OFF: Online
ON: Offline Indicates that output refreshing has

M174 Output-off-line flag
OFF: Online stopped.
Shared-I/O- ON: Offline Indicates that shared refreshing has

M175 off-line flag stopped.
OFF: Online
M176 Link-I/O-off-line flag ON: Offline

Indicates that link refreshing has stopped.
OFF: Online
Devices reserved
ON: Carry-enabled A carry flag used for shift or rotation

M188 Carry flag
OFF: Carry-disabled operation.
Devices reserved
Note 1: Only available with the F3SP21, F3SP25, F3SP28, F3SP35, F3SP38, F3SP53 and F3SP58.
Note 2: Only available with the F3SP28, F3SP38, F3SP53 and F3SP58.
AP010301.EPS
See Also
Specifications of special registers for clock data, for more information on time setting.

App.1-5
Appendix 1.4 Self-diagnosis Status Relays

Self-diagnosis status relays indicate the results of self-diagnostics by the sequence CPU.
Table Appendix 1.4 Self-diagnosis Status Relays
Item Self-diagnosis Status Relays
Error information is stored in special
M193 Self-diagnosis error ON: An error is found. registers Z17 to Z19 for updating the
OFF: No error is found results of self-diagnosis.
ON: Abnormal.
M194 Battery failure Indicates a failure in backup batteries.
OFF: Normal.
ON: A momentary power

Momentary failure is found. Indicates that a momentary failure has
M195 occurred.
power failure OFF: No momentary power
failure is found.
CPU-to-CPU ON: Abnormal. Indicates that a communication failure

M196
communication failure OFF: Normal. has occurred in shared relays/registers.




Information on an error that may occur
Instruction ON: An error is found. during instruction processing is stored in
M201
processing error OFF: No error is found special registers Z22 to Z24.
Indicates that the state of module
M202 I/O collation error ON: Abnormal. installation is not consistent with the
OFF: Normal. program.
ON: Abnormal. Indicates that access to I/O modules is not

OFF: Normal. possible. The slot number of the module
M203 I/O module failure
in question is stored in special registers
Z33 to Z40.
ON: Abnormal. Indicates that the scan has exceeded the

M204 Scan time-out
OFF: Normal. scan time monitoring time.
ON: Abnormal
Subunit transmission transmission line.
M210
line fai lure OFF: Unspecified ornormal The slot number of the fiber-optic FA-bus
transmission line module in question is stored in special
registers Z89 to Z96 if a failure occurs in
ON: Abnormal
the module.
Switchover in subunit transmission line.
M211
transmission line OFF: Unspecified ornormal
transmission line
Indicates that it is not possible to sustain
M212 CB scan timeout ON: Abnormal. the execution interval of the sensor control
OFF: Normal. block.
M225 CPU-1 sequence ON: Executes the program. Indicates whether a sequence program for
(Note1) program execution OFF: Stops the program. a CPU in slot 1 is running or at a stop.
AP010401.EPS
Note 1: Only available with the F3SP21, F3SP25, F3SP28, F3SP35, F3SP38, F3SP53 and F3SP58.
Note 2: Only available with the F3SP28, F3SP38, F3SP53 and F3SP58.

App.1-6
CAUTION
The M210 (Subunit Transmission Line Failure) and M211 (Switchover in Subunit
Transmission Line) self-diagnosis relays are only available with the Rev.8 or a later version
of the F3SP21, F3SP25 and F3SP35.
See Also
more information on the M210 (Subunit Transmission Line Failure) and M211 (Switchover
in Subunit Transmission Line) self-diagnosis relays.

App.1-7
Appendix 1.5 FA Link Module Status Relays

FA Link module status relays indicate the status of FA link.
See Also
Special relays/registers sections of FA Link H Module F3LP02-0N Fiber-optic FA Link H

Module F3LP12-0N (IM34M5H43-01E), for more information on these FA link module
status relays.
Table Appendix 1.5 FA Link Module Status Relays

Item FA Link Module Status Relays
F3SP28, F3SP38 M257 to M480
ON: Abnormal. Indicate the status of FA
FA link failure link.
F3SP53, F3SP58 F3SP21,F3SP25 M257 to M480 OFF: Normal.
F3SP35 M8321 to M8992
AP010501.EPS

Blank Page
App.2-1
Appendix 2. Special Registers (Z)

Special registers have specific functions, such as indicating the internal state of a
programmable controller or detecting errors.
Appendix 2.1 Sequence Operation Status Registers

Sequence operation status registers indicate the status of sequence operation.
Table Appendix 2.1 Sequence Operation Status Registers
Scan time Latest scan time Stores the latest scan time in 100-µs
Z001 (Run mode) increments.

Z002 (Run mode) Minimum scan time 100-µs increments if it is shorter than the
minimum scan time.
Z003 (Run mode) Maximum scan time 100-µs increments if it is longer than the
maximum scan time.
Scan time Stores the latest scan time in 100-µs
Z004 (Debug mode) Latest scan time
increments.

Z005 (Debug mode) Minimum scan time 100-µs increments if it is shorter than the
minimum scan time.
Z006 (Debug mode) Maximum scan time 100-µs increments if it is longer than the
maximum scan time.
Peripheral-process Stores the latest scan time in 100-µs
Z007 Latest scan time increments.(Tolerance: Scan time of one
scan time
control process)
Minimum peripheral- 100-µs increments if it is shorter than the
Z008 process scan time Minimum scan time minimum scan time.(Tolerance: Scan time
of one control process)
Maximum peripheral- 100-µs increments if it is longer than the
Z009 Maximum scan time
process scan time maximum scan time.(Tolerance: Scan
time of one control process)
AP020101.EPS
CAUTION
Do not write to a special register, including those not listed in the table above (e.g., Z010 to
Z016), unless otherwise stated. This is because they are used by the CPU module for the
system. If you inadvertently write to these registers, a failure such as a system shutdown
may occur.

App.2-2
Appendix 2.2 Self-diagnosis Status Registers

Self-diagnosis status registers indicate the results of self-diagnostics by the sequence
CPU.
Table Appendix 2.2 Self-diagnosis Status Registers
Type Seelf-diagnosis Status Registers
Self-diagnosis
Z017 Store the results of self-diagnosis.*
error number
Z018 Self-diagnosis error block number
Instruction processing Store errors occurring during instruction

Z022 error number processing.*
Instruction Instruction processing

Z023 processing error error block number
Instruction processing
Z024 error instruction number
I/O collation error number Store detailed information on I/O collation

Z027 errors.*
I/O collation error I/O collation error

Z028 block number
I/O collation error

Store, as a bit pattern, the slot number for

which an I/O failure has occurred.
I/O failure Z033: Main unit
Z034: Subunit 1
Z033 to Z040 I/O failure 16 2 1 Z035: Subunit 2
0 … 1 0 Z036: Subunit 3
Z037: Subunit 4
Z038: Subunit 5
Z041 Main unit

Z042 Subunit 1
Z043 Subunit 2
Slot number
Z044 Subunit 3 16 2 1
Module recognition
Z045 Subunit 4 0 … 1 0
Z046 Subunit 5 0: No modules are recognized.
Unable to read/write.
Z047 Subunit 6
1: Modules are recognized.
Z048 Subunit 7
Z089 Main unit Slot number
Z090 Subunit 1 16 2 1
Z091 Subunit 2 0 … 1 0
Abnormal slot
Z092 insubunit Subunit 3 Fiber-optic FA-bus module
Z093 transmission line Subunit 4 0: Normal transmission line;
Unspecified transmission line;
Z094 Subunit 5 or Loaded with the wrong module
1: Abnormal transmission line
Z095 Subunit 6 (Failure or changeover in
Z096 Subunit 7 transmission line)
* For information on error numbers (codes) to be saved in these special registers, see Table A8.2,"Details of Self-
diagnosis."
AP020201.EPS

App.2-3
CAUTION
• The Z041 to Z048 (Module Recognition) self-diagnosis status registers are only
available with the Rev.8 or later version of the F3SP21, F3SP25 and F3SP35.
• The Z089 to Z096 (Abnormal Slot in Subunit Transmission Line) self-diagnosis status
registers are only available with the Rev.8 or later version of the F3SP21, F3SP25 and
F3SP35.
See Also
more information on the Z089 to Z096 special registers (Abnormal Slot in Subunit
Transmission Line).

App.2-4
Appendix 2.3 Utility Registers

Table Appendix 2.3 Utility Registers
Type Utility Registers
Stores "year" as a BCD-coded value.
Z049 Lower-order two digits Example: 1999 as $0099
(write-enabled) of calendar year 2000 as $0000
Z050 Stores "month" as a BCD-coded value.

Month
(write-enabled) Example: January as $0001
Stores "day of month" as a BCD-coded
Z051 Day of month value.
(write-enabled) Example: 28th as $0028
Z052 Hour Stores "hour" as a BCD-coded value.

(write-enabled) Example: 10 o'clock as $0010
Clock data
Z053 Minute Stores "minute" as a BCD-coded value.
(write-enabled) Example: 15 minutes as $0015
Z054 Stores "second" as a BCD-coded value.

Second Example: 30 seconds as $0030
(write-enabled)
Stores "day of week" as a BCD-coded
Z055 Day of week value.
($0000 to $0006) Example: Wednesday as $0003
Z056 Constant scan time 0.1 ms increments

Value of constant scan time
(Note) Example: 10 ms as 100
Z057 1 ms increments
Constant scan time Value of constant scan time Example: 10 ms as 10
Z058 Scan time Value of scan time 1 ms increments

monitoring time monitoring time Example: 200 ms as 200
Note: Available with the F3SP21, F3SP25 and F3SP35 only.

AP020301.EPS
● Clock Data Setting

Follow the procedure given below to set clock data.
(1) Write the clock data to the special registers Z049 to Z054 (use a MOV P instruction,
for example).
(2) Set the special relay M172 to ON within the same scan as that in step 1 (use a DIFU
instruction, for example).
(3) Set the special relay M172 to OFF in the scan subsequent to that in step (2).
Also stop writing the clock data to the special registers Z049 to Z054 in that scan.
Note that no change is made to the clock data and the data reverts to its original values if
the values being set are incorrect.
● Clock Data Accuracy

The accuracy of clock data is specified as:
Maximum monthly error ±8 s (±2 s, when actually measured)
The clock accuracy is reset to the maximum daily error of -1.2 s/+2 s, however, when the
power is turned off and on again. In addition, it is possible to input a corrective value from
the programming tool. If you input a precise corrective value, the clock data is corrected
during the power-off-and-on sequence, thus offsetting the cumulative amount of error.

App.2-5
Appendix 2.4 FA Link Module Status Registers

FA Link module status registers indicate the status of FA link.
See Also
Special relays/registers sections in FA Link H Module F3LP02-0N Fiber-optic FA Link H

Module F3LP12-0N (IM34M5H43-01E), for more information on the FA link module status
registers.
Table Appendix 2.4 FA Link Module Status Registers

Type FA Link Module Status Registers
No. Name Status Data Description
2: Online
Cyclic transmission FA link 1
2: Online

(Note) 2: Online
(Note)
(Note) 2: Online
(Note)
(Note) 2: Online
(Note)
(Note) 2: Online
(Note)
(Note) 2: Online
(Note)
(Note) 2: Online
(Note)
Note: Available with the F3SP25 and F3SP35 only.
AP020401.EPS

App.2-6
Appendix 2.5 CPU Module Status Registers

CPU module status registers indicate the status of a CPU.
Table Appendix 2.5 CPU Module Status Registers
Type CPU Module Status Registers
No. Name Description Remarks
See Section A6.14, "User Log
Z105 Number of stored Management Function," for
user logs information on user logs.
Refers to the length of time from when
input refreshing is started for the sen-
CB execution time sor control block to when the program
Z109
is executed and output refreshing is
completed.
(Note)
Maximum CB Refers to the maximum time taken to
Z111 execution time execute the sensor control block.
(Note) (Unit: 10 µs)
Note: Only available with the F3SP28, F3SP38, F3SP53 and F3SP58.
AP020501.EPS

App.3-1
Appendix 3. Forms for System Design

■ Program Coding Sheet
Approved Checked Prepared Sheet
System Name
by by by No.
Model Drawing No.
Instruction No. Instruction Operand Remarks

0
0
TAP0301.EPS

App.3-2
■ Relay Devices Assignment Table
System Name
by by by No.
Model Drawing No.
Device No. Signal Name Description Device No. Signal Name Description
1 3
2 4
3 5
4 6
5 7
6 8
7 9
8 0
9 1
0 2
1 3
2 4
3 5
4 6
5 7
6 8
7 9
8 0
9 1
0 2
1 3
2 4
3 5
4 6
5 7
6 8
7 9
8 0
9 1
0 2
1 3
2 4
TAP0302.EPS

App.3-3
■ Register Devices Assignment Table
System Name
by by by No.
Model Drawing No.
Device No. Signal Name Description Device No. Signal Name Description
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
0 0
TAP0303.EPS

App.3-4
■ Timer/Counter Setpoints Table
System Name
by by by No.
Model Drawing No.
Device No. Setpoint Signal Name Description

1
2
TAP0304.EPS

Index-1
FA-M3
Index
Number executing specified blocks ................................... A6-7
100-ms continuous timer ................................... A4-29 extended shared register (R) ............................. A4-36
100-ms timer ..................................................... A4-29 extended shared relay (E) .......................... A4-6, A4-9
10-ms timer ....................................................... A4-29 extended system configuration .................. B2-2, C2-2
1-ms timer ......................................................... A4-29
F
B F3SP05 .............................................................. B1-1
basic system configuration ............... A2-1, B2-1, C2-1 F3SP08 .............................................................. C1-1
block ................................................................... A5-3 F3SP21 .............................................................. A1-1
block protection ................................................. A6-18 F3SP25 .............................................................. A1-1
block start status ............................................... A4-22 F3SP35 .............................................................. A1-1
FA link module status ............................. A4-26, A4-43
C FA link system .................................. A2-4, B2-3, C2-3
clearing device .................................................... A6-3
FA-M3 Value ....................................................... B1-1
clearing memory ................................................. A6-3
FA-M3 Value II .................................................... C1-1
command .......................................................... A6-39
file register (B) .................................................. A4-46
communication procedure ................................. A6-37
forced reset ....................................................... A6-15
computation method ........................................... A3-6
forced set .......................................................... A6-15
configuration .................................... A1-7, B1-6, C1-6
constant scan time .............................................. A6-5 I
counter ............................................................. A4-30 I/O address allocation ......................................... A4-2
CPU module status ........................................... A4-44 immediate detection mode .................................. A3-3
CPU service ..................................................... A3-14 index register (V) ............................................... A4-45
current value ..................................................... A6-16 initial data ......................................................... A4-38
interrupt processing .......................................... A3-17
D interrupt processing control ............................... A3-18
data code type, specifying ................................... A4-3
input relay (X) ..................................................... A4-1
data register (D) ................................................ A4-32
input sampling interval ........................................ A4-3
data value, changing ......................................... A6-16
input/output processing ....................................... A3-8
debug mode ...............................................A3-1, A6-3
input/output relay number .......... A1-17, B1-11, C1-11
device ................................................................. A4-1
internal relay (I) ..........................................A4-5, A4-9
device list ......................................... A1-5, B1-5, C1-5
interrupt program ................................................ A5-8
device management function ............................ A6-46
DIO (input/output module) setup ......................... A4-3 L
ladder diagram support program M3 ..........A2-7, B2-6
E link refresh ........................................................ A3-15
exclusive access right ....................................... A6-26
link register (W) ...................................... A4-16, A4-21
executable program ............................................ A5-4
link relay (L) ........................................... A4-11, A4-21
executable program protection .......................... A6-17
link service ........................................................ A3-11
executing all blocks ............................................. A6-6

Index-2
M shared refresh .................................................. A3-12
macro instruction .............................................. A6-47 shared register (R) ............................................ A4-33
main routine program .......................................... A5-6 shared relay (E) ........................................ A4-6, A4-9
main unit .................................... A1-14, B1-10, C1-10 slot number ................................ A1-15, B1-11, C1-11
minor failure ...................................................... A8-10 standard mode .................................................... A3-3
mnemonic language ........................................... A5-2 step operation ................................................... A6-13
mode status ...................................................... A4-24 stop mode ................................................. A3-1, A6-3
moderate failure ................................................ A8-10 stop refresh function ......................................... A6-16
momentary power failure detection mode ............ A3-3 structured programming language ...................... A5-1
multi-CPU system configuration .......................... A2-1 subroutine program ............................................. A5-7
subunit ....................................... A1-14, B1-10, C1-10
O
operation in case of complete power failure ......... A3-4 T
operation in case of momentary power failure ..... A3-3 tool service ....................................................... A3-10
operation mode ..........................................A3-1, A6-3
operation mode of CPU ...................................... A3-1
U
unit ............................................ A1-14, B1-10, C1-10
output hold .......................................................... A4-4
user log management function .......................... A6-57
output relay (Y) ................................................... A4-2
utility relay ..............................................A4-23, A4-42
output reset ......................................................... A4-4
P W
WideField ........................................ A2-5, B2-4, C2-4
partial operation ................................................ A6-15
PC link function ................................................. A6-31
PC link system ................................. A2-3, B2-3, C2-3
program memory ................................................ A5-9
programming language ....................................... A5-1
programming tool ............................. A2-5, B2-4, C2-4
R
RAS function ....................................................... A8-1
remote I/O system ........................... A2-3, B2-2, C2-2
reset ................................................................... A4-4
response ........................................................... A6-39
response delay ................................................... A3-9
ROM Clear function .......................................... A6-25
ROM Copy function ........................................... A6-25
ROM Cross-check function ............................... A6-25
ROM resident ................................................... A6-20
ROM Transfer function ...................................... A6-25
ROM Writer function ......................................... A6-20
S
sampling trace function ..................................... A6-27
scan operation .................................................. A6-14
scan time ............................................................ A7-1
scan time monitoring time, setting ....................... A7-2
self diagnosis ...................................................... A8-1
self diagnosis status ............................... A4-25, A4-40
sequence operation .......................................... A4-24
sequence operation status ................................ A4-39
setpoint ............................................................. A6-16

i
Revision Information
Document Name : Sequence CPU Instruction manual - Functions (for F3SP21, F3SP25 and F3SP35)
Document No. : IM 34M6P12-02E
Edition Date Revised Item

1st Sep, 1995 New Publication
2nd July, 2001 Support for WideField
3rd Oct, 2001 Incorporation of addendum (support for CE marking) into manual.
Addition of Part C for CPUs designed for FA-M3 Value II.
Correction of errors.
Written by Product marketing Departments, IT controller Center

Yokogawa Electric Corporation
Published by Yokogawa Electric Corporation
2-9-32 Nakacho, Musashino-shi, Tokyo 180-8750, JAPAN
Printed by Yokogawa Graphic Arts Co., Ltd.

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Instruction

■ Safety Precautions when Using/Maintaining the Product

Alternating current. Indicates alternating current.

Direct current. Indicates direct current.

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

■ Exemption from Responsibility

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

● Avoid installing the FA-M3 controller in the following locations:

● Use the correct types of wire for external wiring:

● Securely tighten screws:

● Securely lock connecting cables:

● Interlock with emergency-stop circuitry using external relays:

● Ground for low impedance:

● Configure and route cables with noise control considerations:

● Configure for CE Marking Conformance:

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

● Discharge static electricity before operating the system:

● Never use solvents such as paint thinner for cleaning:

● Avoid storing the FA-M3 controller in places with high temperature or

● Always turn off the power before installing or removing modules:

● Do not touch components in the module:

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

■ Structure of the Manual

● Part A: Standard Version

● Part B: F3SP05-0P Sequence CPU for FA-M3 Value

● Part C: F3SP08-0P Sequence CPU for FA-M3 Value II

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

● Work Flow from System Design to System Operation, and Chapters to Be

Determination of system configuration

Ladder symbols Debugging Program modification

Program storage on floppy/hard disk or

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

● Symbol Marks Used in This Manual

■ Other Instruction Manuals

Be sure to read each of the following manuals, in addition to this manual.

● For information on the specifications*, configuration, installation, wiring,

● When creating programs using ladder language, refer to:

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

● For information on the functions of FA link H and fiber-optic FA link H

● For information on the functions of F3SP28, F3SP38, F3SP53 and F3SP58

● For information on the functions of BASIC CPU modules, refer to:

● For information on the functions of the F3FP36 sequence CPU module,

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

Copyright and Trademarks

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

Sequence CPU Instruction Manual - Functions

PART A for F3SP21, F3SP25 and F3SP35

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

PART B for CPU module designed for the FA-M3 Value

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

PART C for CPU module designed for the FA-M3 Value II

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

Sequence CPU Instruction Manual - Functions

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00

IM 34M6P12-02E 3rd Edition : Oct 1, 2001-00