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N65LP 2.4GHz RF LC-tank VCO Process Vehicle Report

____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________

Process: N65LPGV2
TM#: TMT501, TMT504
Designer: RFDP/SDP/tsmc
Report Date: August 31, 2007
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Version: Preliminary 0.1v

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Contents
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Introduction
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Specification
Schematic
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Pre-Simulation
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Extraction Flow
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1) Calibre Extraction Flow

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2) Assura Extraction Flow

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Simulation vs. Silicon Measurement

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GDS Layout
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Test Bench
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1) PCB Board
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2) Test Equipment
Summary
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2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007

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1. Introduction

This design guide of N65LP 2.4GHz LC-tank VCO is for process vehicle purpose to verify design flow
from process, spice model, PDK, circuit and silicon measurement. The meaning is from frond-end of circuit

____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________

to back-end overall flows verification in tsmc N65LP process technology. In this design guide, we start from
VCO core circuit, output buffer design, especially in frequency tuning, phase noise, current and output
power circuit simulation. Second, we had done back-end flow in GDS layout, parasitic capacitance
extraction and post-simulation. Finally, the silicon measurement is compare to all of design procedure in
pre-simulation and post-simulation results.
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2. Specification
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(1) LC-VCO DC Specification

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Item Parameter Condition MIN. TYP MAX Unit

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Vdd VCO core Supply Voltage 1.2 V

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Vd25_buf Buffer Supply Voltage 2.5 V

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VIL Logic low for control signal 0.2VDD V

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VIH Logic high for control voltage 0.8VDD V

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Ivdd VCO core current consumption TT, 25C 1 mA

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Ivd25_buf Buffer current consumption TT, 25C 16 mA

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(2) LC-VCO AC Specification

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Item Parameter Condition MIN. TYP MAX Unit

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Fout VCO Output frequency 2300 2400 2600 MHz

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PN Phase noise @1MHz offset 110 dBc/Hz

Kvco VCO gain 100 MHz/V
Vout Output Swing Single-end 0.5 Vpp
Cload Output Load Drive @buffer 1 pF
Rout Output impedance 50 ohm

2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007

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3. Schematic
This design has used a complementary cross-coupled LC-tank VCO structure to provide negative
resistance to sustain VCO oscillation. The device is 1.2v core device, 3X1Z1U metal scheme of inductor,
MIM capacitor of ac coupling application and varactor for tunable of frequency output. Figure 1 shows the

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VCO core schematic.
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Fig. 1 LC-tank VCO

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TSMC PDK Inductor Finder:

The LC-tank VCO generally consists of an LC tank and a negative resistance circuit. And the quality factor (Q)
of LC-tank is one of main parameters that affect phase noise. In modern CMOS process, the dominant factor of

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the quality factor of an LC-tank is the inductor.
In the TSMC PDK, there is a function to search suitable inductor.
<i> Choose inductor and select Edit -> properties
<ii> Press Finder item and fill in the design spec.
Design Frequency ; L value ; available L value ; minimum Q factor ; inductor area
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<iii>Press FIND
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Fig. 2 TSMC PDK Inductor Finder

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As shown in Fig3, after searching inductor, each parameter of inductor is listed and can be
trade off with the design spec. When the suitable inductor is chosen, the graph of inductance and quality factor
will pop out after pressing LQ preview item.

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Fig. 3 TSMC PDK Inductor Finder results

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The output buffer has used 2.5V device and driving external 50-Ohm load of design. This output buffer
is a differential pair with AC coupling input, self-bias DC circuit and differential output. And, it provides
300mVp-p(single) output swing. Figure 4 shows output buffer design. Power supply for the output buffer is

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2.5V and the current consumption is 16mA.
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Fig 4 VCO output buffer

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4. Pre-Simulation
The VCO target frequency, tuning range and phase noise are key performance of VCO design.
Simulation of those parameters can be done by PSS and pnoise simulation in cadence spectreRF. And this
design also need to consider the corner effect in VCO performance. The following of setting figure is for

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PSS, pnoise and corner simulation.
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Fig 6 PSS and pnoise setting in cadence ADE environment

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Corner simulation setup procedure: ADE Tools ----> corner

load xxx.pcf from pdk models path.

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Fig 7 Corner setting

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1) Tuning Frequency
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This is VCO output frequency vs. tuning voltage. The output frequency is from 2.3GHz to 3GHz.
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That is related varator capacitor tuning selection with inductor value to define frequency range.
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Fig 8 frequency tuning range

2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007

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2) Phase Noise
In following figure, phase noise of VCO is shown at different offset frequencies with respect to center
frequency. They are –82dBc/Hz and -117dBc/Hz at 100KHz, 1MHz offset frequency, respectively.

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Offset Freq. Pre-sim

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(dBc/Hz)
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1K -30
10K -56.4
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100K -82.2
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1M -117
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10M -140
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Fig 9 phase noise

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3) Transient Signal
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This diagram shows VCO core output transient signal and swing. The output swing is 400mV.
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Fig 10 transient signal

2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007

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5. Extraction Flow
The purpose of this section is to show parasitic extraction flow. A 2.4G complementary cross-coupled VCO is

presented to go through the whole extraction flow. There are two ways for RLC extraction flow. One is Calibre

____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________

extraction simulation and the other is Assura extraction simulation.

A.) Calibre Extraction Flow

1. Calibre Demo Environment
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1.1 PDK version

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PDK version：
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CRN65LP_PDK_1.1a_official_2007_05_31_all_12v25v3x1z1u
Please copy below directory to local directory
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CRN65LP_PDK_1.1a_official_2007_05_31_all_12v25v3x1z1u/Calibre
on 3 IS /2
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1.2 Extraction rule file

Please download rule deck with specific metal scheme from EDW system
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(Need to request from PDK team )

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For this case, rule deck file : RC_xCalibre_crn65lp_1p6m_3X1Z1U_alrdl_typical_v1.0.tar

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The setup is as follows :

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<i> Untar and include the file “crn65lp_1p06m+alrdl_typical.res” into rules

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<ii> Include the file “rules” into “/local directory/…/…/Calibre/rcx/calibre.rcx”

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<iii> The new caliber.rcx has used for RLC extraction

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Note: To avoid double count

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** calibre.rcx need to be added** LAYOUT CASE YES

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LVS COMPARE CASE NAMES

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PEX IDEAL XCELL YES

where the three lines was added manually

2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007

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2. Setup Calibre PEX step-by-step
2.1 Run LVS and check LVS clean
LVS： from layout view，pull down caliber menu and press Run LVS；
LVS result should look like

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2.2 Run Calibre PEX

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PEX： from layout view，pull down caliber menu and press Run PEX；
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Setp1. Rules :
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a.) Choose your run directory

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2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007

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Setp2. Inputs
a.) Disable the Export from layout viewer box if you already have GDS file.
Or enable it to make sure the new update GDS file

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b.) Choose the correct netlist

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c.) Please enable H-cell file with the Gate level output

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Setp3. Outputs
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a.) Select the Gate level type to avoid double counting inside RF device.
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b.) Choose CALIBRE VIEW output format

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d.) If you want to extract some specified net, choose Specified Nets.

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Setp4. PEX Options

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a.) Disable Ground coupling capacitor for accuracy guarantee

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 ____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
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RFDP/SDP/tsmc/2007
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b.) Recognize gates should be chosen none

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c.) Enable Output looped resistance to RC netlist for accuracy guarantee
Parasitics to output to RC netlist should be chosen All

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c.) Fill in the operating Frequency

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Setp5. Run PEX
After PEX Run
a.) Remember to check correctness of Cell map File
b.) Fill in view name and click OK of the Caliber View

____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________

PEX result should look like
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B.) Assura Extraction Flow
1. Assura Demo Environment
1.1 PDK version
PDK version：

____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________

CRN65LP_PDK_1.1a_official_2007_05_31_all_12v25v3x1z1u
Please copy below directory to local directory
CRN65LP_PDK_1.1a_official_2007_05_31_all_12v25v3x1z1u/Assura
1.2 Extraction rule file
Please download rule deck with specific metal scheme from EDW system
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(Need to request from PDK team )

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For this case, rule deck file : RC_Assura_crn65lp_1p06m+alrdl_typical.tar

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The setup is as follows :

<i> Untar and place them into “/local directory/…/…/Assura/lvs_rcx”
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<ii>Note: To avoid double count

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Add new option into

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a.) “/local directory/…/…/Assura/techRuleSets”

b.) “/local directory/…/… /Assura/lvs_rcx/compare.rul “
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c.) “/local directory/…/… /Assura/lvs_rcx/rcxrsf “

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a.) Add RcxInclude into techRuleSets

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2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007

 ____________________ TSMC Confidential Information 385694 USC/ISI/MOSIS 10/30/2010 ____________________
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2.4GHz RF LC-tank VCO Process Vehicle Report

b.) Add hcell path into compare.rul

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c.) Add hcell path into rcxrsf

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2. Setup Assura RCX step-by-step
2.1 Enable PreserveCells
a.) Choose Modify avParametersSelect
b.) Select ?preserveCells and choose hcell path

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2.2 Run LVS and check LVS clean

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LVS： from layout view，pull down Assura menu and press Run LVS；
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LVS result should look like

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2.3 Run Assura RCX
RCX： from layout view，pull down Assura menu and press Run RCX；
Setp1. Setup
a.) RSF file should be enabling

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b.) Please choose Extracted View output format
c.) Fill in Extracted View name
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Setp2. Extraction
a.) Choose Extraction Mode: RC ; RLC ; RLCK ; R Only ; C Only
b.) Set Max fracture length
c.) Select cap Extraction Mode “coupled” for C extraction accuracy guarantee

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d.) Select extracted region (will be described in the following )
e.) Choose Extraction Mode: Full chips All Nets ; Selected Nets ; Excluded Nets
f.) Select the net that required inductance extraction from schematic
g.) Fill in Ref node name (It’s usually “gnd!”)
h.) Fill in Global Frequency
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RFDP/SDP/tsmc/2007
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Edit the layout region and the layers used in the layout

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d.) Select extracted region

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Setp3. Filtering
a.) Disable Exclude Self Capacitance for accuracy guarantee
b.) Enable Dangling R
c.) Set Via parasitic resistor merging policy

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Setp5. Run RCX

RCX result should look like

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6. Simulation vs. Silicon Measurement

This is post-simulation with measurement results, and samples were from TMT501 and TMT504. From
these results, it had same of frequency results between shuttle measurements. To compare pre-simulation and

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silicon measurement results, there has just below 5% difference.
1. Calibre RCCL mode and RCC mode
1.1 Frequency tuning range
This is pre-simulation, post-simulation and silicon measurement result.
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3.00E+09
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2.80E+09
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Frequency (Hz)

2.60E+09
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2.40E+09
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Measurement-TMT504
Measurement-TMT501
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2.20E+09 Post-layout simulation_Calibre RCCL

Post-layout simulation_Calibre RCC
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2.00E+09
0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40
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Vtune (V)
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Fig 11 Pre-sim, post-sim vs. measurement

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1.2 Phase Noise

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This is phase noise pre-simulation and silicon measurement data. Please see the fig 13 and summary
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table. They have close of noise results between pre-simulation and measurement.
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Fig 12 phase noise

2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007

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SSB Phase Noise (dBc/Hz) @Vtune=0.6v

0 Offset Freq. Pre-sim Si Meas. Si Meas.
-20 (dBc/Hz) TMT501 TMT504
Phase Noise (dBc/Hz)

Pre-sim
-40
(dBc/Hz) (dBc/Hz)

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-60
Si-meas. 1K -30 -39 -32
-80
-100 10K -56.4 -65.6 -65
-120 100K -82.2 -75.5 -87.05
-140
1M -117 -113.35 -114.45
-160
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1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Offset frequency (Hz)
10M -140 -137 -135
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Fig 13 Phase noise summary tables

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TMT504
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1.3 Output Power

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Output power post-sim and silicon measurement results.

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-10.00
0.00 0.20 0.40 0.60 0.8 0 1 .00 1.20 1.40

-11.00

-12.00

-13.00
TMT501
Output Power (dBm)

-14.00

-15.00

-16.00

-17.00
TMT501 M easurement
TMT504 M easurement
-18.00
Post-layout simulation (Calibre RCCL)
Post-layou simulation (Calibre RCC)
-19.00
Vtune (V )

Fig 14 Output Power

2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007

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2. Assura RCCL mode and RCC mode
TBD

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7. GDS Layout
For easy measurement on probe station and COB (Chip on Board), this layout plan is put DC pad on the top
area, and SGS pad on the bottom.
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Fig 15 VCO Layout

2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007

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8. Test Bench

1. PCB Board

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PVDD RPS22 RP22 PVDDD

2
2

2ohm 2ohm
C220ua TP201 TP202 CPS19 CPS20 CPS21 CPS22 CPS23 CPS24 CP22 CP23 CP24 CP19 CP20 CP21 TP01DD TP02DD C220ub
220u PWD PWD PWD PWD 220u
10u 1u 1u 10n 1u 100p 10n 1u 100p 1u 1u 1u

1
1

RT22 PVTUNE

2
2ohm
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CT22 CT23 CT24 CT19 CT20 CT21 TP01T TP02T

20

19
22

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24

23
PWD PWD
10n 1u 100p 10u 1u 1u

1
VTUNE

VSS2
VSS

VSS1

VDD

VDDD
1 18
NC NC
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2 17
NC NC

1) DIE as short as possible with SMA

3 16
2) Component put on the top of PCB NC NC
C

3) Layout for COB and QFN application

2D4VCO
4) 50 ohm layout
4 QFN_2D4GHz 15
NC NC
Component_1
5 14
NC NC
C

6 13
NC NC
OUTN

OUTP
VSS3

NC

NC
NC
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COUTN1 COUTP1

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10u 10u
OUTNN OUTPP
1

1
GND

IN
SMAOUTP
IN
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2 SMA
GND
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SMAOUTN
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Size Number
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Fig 16 PCB schematic and layout

2. Test Equipment
Agilent E5052A

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9. Summary

For this preliminary version of design flow and report, RFDP have implement circuit design from

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pre-simulation, post-simulation procedure and compare to silicon chip measurement results. It look well of this
results.
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2.4GHz RF LC-tank VCO Process Vehicle Report RFDP/SDP/tsmc/2007