Lab Project 8: 16-bit RISC Processor © 201 4 R . W.

A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

Team Members
We are submitting our own work, and we understand severe penalties Estimated Work Hours Point Scale
will be assessed if we submit work for credit that is not our own.
1 2 3 4 5 6 7 8 9 10 4: Exemplary
3: Complete
Print Name ID Number 2: Incomplete
5%will be deducted from total score 1: Minor effort
for each day late 0: Not submitted
Print Name ID Number
Score = Points awarded (Pts) x Weight (Wt)
GRADER Total In‐Lab
Days Score
# Demonstration Wt Pts Score Grader Signature Date
Late
Demo working Integer Datapath 3
1 Documentation / Source Code 4
Testbench / Simulation-Verification 3

General Statement: Your team (2 people) is to complete the “301 16-bit RISC Processor.” This is done by
connecting the CPU_EU with a “timing and control unit” (CU) verilog module and the 256x16 Memory (developed
in lab7). The CU will be a “Moore” implementation of a finite state machine, where the outputs (control signals for
the CPU_EU and Memory) are a function of the present state. The CU will control the execution of instructions
defined for the 301 RISC Processor (see 16-bit RISC Processor specifications document).

At “reset,” the 301

RISC Processor 3
W_Adr
will begin fetching rw_en
3
and executing 3
R_Adr
S_Adr
instructions 4
starting at memory Alu_Op
s_sel
location 0x00. adr_sel

ir_ld CPU_EU
pc_ld
pc_inc
CU pc_sel
16
IR_out
(Finite 3
ALU_Status
State
Address D_out D_in
Machine)
16 16 16

Address D_in D_out

256x16
Memory
mw_en

301 16-bit RISC Processor

301 Lab Assignment 8 – Page 1

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

Top‐Level and I/O and Specifications: Your “top level” verilog module will interconnect the (1) 16-bit RISC
Processor, (2) Memory, (3) Display Controller and (4) Debounce modules. The Display Controller is
to display the Address outputs and the D_in inputs from/to the CPU_EU module based upon the AD_sel
input (sw7).

Additional control signals not provided by the CU are shown below. The reset signal is to be provided to every
logic block using synchronous logic. Both the CU and CPU_EU modules are to be clocked using the “step clk”
button (debounced). The “step_mem” button (debounced), “AD_sel” and “dump_mem” signals will be used for
displaying the contents of Memory after the 301 RISC Processor executes a “Halt” instruction. Memory is
clocked with the 50Mhz FPGA board clock. Memory is to be generated (CoreGen) with the three initialization
files (e.g. ram_256x16_lab8a.coe).

reset step step AD dump

mem clk sel mem

btn btn btn sw sw

3 1 0 7 0

Verification: To verify that all instructions of your RISC Processor are working, you must execute (by stepping
through) the instructions for all three memory modules. The binary content of the memory modules that you
will generate are shown on pages 9 to 11. Your team must complete those three pages by disassembling the
machine code, fill in the “Register Written” column (where applicable), fill in the “Final Contents” of CPU and
Memory registers that were written to by the program that is executed as well as the exact number of
instructions that were executed, including the HALT instruction.

Deliverables: Your team must turn in (1) pages 1-2 of these cover sheets, followed by (2) the print outs from all
verilog modules, logically sequenced in a “top-down” manner, starting with the “top-level” module, followed
by (3) all three memory modules (pages 9-11) completed with applicable assembly instructions, completed
“Register Written” column (where applicable), completed “Final Contents” of CPU and Memory registers along
with the number of instructions executed, and lastly, (4) the completed “Team Accountability Reporting Sheet
(p. 12).”

As always, you will be penalized for each violation related to inputs, outputs, and operation specifications.
You will be penalized for not adhering to documentation specifications of the “deliverables,” as well as
“substandard” documentation practices (i.e. meaningless or inaccurate comments, “wrap-around” in print
outs, illegible documentation, etc.).

Due Date: Monday, December 1, 2014 {Monday of Week 15}

301 Lab Assignment 8 – Page 2

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

Control Unit Design Specifications: The control signals for the CU module are described below:
Inputs:
IR_out: This is the 16-bit instruction code currently in the IR, which consists of the 4-bit opcode and three 3-bit
register select codes.
The 4-bit opcode is used in the “decode” state to determine what instruction to execute (i.e. what
“execute” state to go to).
The W_Adr, R_Adr, and S_Adr outputs will be derived from the three 3-bit register select codes, based
upon the 4-bit opcode (e.g. for “add” W_Adr = IR[8:6], R_Adr = IR[5:3] and S_Adr = IR[2:0]).
ALU_Status: These three 1-bit values are the N, Z and C status indicators from the ALU, based upon the current ALU
opcode. These 3 bit values may or may not be stored in the actual RISC Processor’s “flag register”
based upon what state the processor is current in (e.g. the “add” state versus the “store” state).
Outputs:
W_Adr: The 3-bit “Write Address” to specify which register (R0 to R7) to write to (if rw_en is asserted).
rw_en: The register file “write enable.” When rw_en=1, the register specified by W_Adr will be written to.
R_Adr: The 3-bit “R Address” to specify which register (R0 to R7) will be output from the R port of the register file.
Note that addresses for Memory registers to be read from or written to must come from the R port of the
register file.
S_Adr: The 3-bit “S Address” to specify which register (R0 to R7) will be output from the S port of the register file.
Note that data to be written to Memory must come from the S port of the register file.

Alu_Op: This is the 4-bit ALU opcode (specified in lab 6) to control which ALU operation to perform.
s_sel: If s_sel=0 the S-port of the ALU gets data from the S-port of the register file. If s_sel=1 the S-port of the
ALU gets data from the memory (i.e. the DS datapath inputs).
adr_sel: If adr_mux=0, the “Address” outputs from CPU_EU come from the PC, else they come from the R-port of
the register file.
ir_ld: If ir_ld=1 @(posedge clk), the instruction register (IR) will be loaded, presumably with an instruction from
Memory. If ir_ld=0 @(posedge clk), the IR will remain the same.
pc_ld: If pc_ld=1 @(posedge clk), PC  PC + sign_extension (IR[7:0]). This operation is an addition to the
CPU_EU logic needed for jump instructions.
pc_inc: If pc_inc=1 @(posedge clk), PC  PC + 1. Note that pc_ld and pc_inc are mutually exclusive outputs.
pc_sel: If pc_sel=0, inputs to the PC come from the “PC+sign_extension” logic. If pc_sel=1, the inputs to the PC
come from the Datapath (Alu_out). Refer to the PC Modifications page.
mw_en: The Memory “write enable.” If mw_en=1, the Memory register specified by the Address outputs of CPU_EU
will be written with the data on the D_Out outputs of the CPU_EU. If mw_en=0, Memory will not be written
to.

It is IMPORTANT to note that ALL of the CU outputs must be assigned values in EVERY state!

Memory Address Multiplexing:

In order for us to display the contents of Memory, independent of CPU_EU generated addresses, there is the need
for the “top level” verilog module to multiplex an address to the Memory module. This is the purpose of the
“dump_mem” switch. The “top level” module is to have an 16-bit mem_counter register (initialize to 00h at reset).
If dump_mem = 0, the address given to Memory comes from the CPU_EU Address outputs. If dump_mem = 1, the
address given to Memory comes from the 16-bit mem_counter. Use a conditional continuous assignment statement
to implement this 2-to-1 mux function, as follows:
assign madr = dump_mem ? mem_counter : Address;
where the LHS (madr) is the wire used in the instantiation of the Memory module and the two RHS arguments are
the mem_counter (defined in the “top level” module) and the Address outputs of the CPU_EU module.
Note: since the Memory module has only 256 locations (8-bit addr), instantiate it using madr[7:0].
The step_mem button is used to increment the 16-bit mem_counter. Thus, at every positive edge of step_mem, the
mem_counter is to be incrememted by 1. The AD_sel selects displaying either 16-bit Data (AD_sel=0) or 16-bit
address (AD_sel =1).

301 Lab Assignment 8 – Page 3

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

RESET: CU
FETCH: State Diagram
PC = 00h; IR  M[PC]
{nf, zf, cf} = 3’b0
PC  PC +1 (Partial)

ADD: IR[15:9] = 70h IR[15:9] = 7Fh JMP:

R[d]  R[d] + R[s] DECODE: PC  R[s]
{nf,zf,cf}={N,Z,C}

IR[15:9] = 74h IR[15:9] = 7Ch

SHL: JE:
R[d]  R[s] << 1 if (zf==1)
{nf,zf,cf}={N,Z,C} PC  PC + seIR
IR[15:9] = 78h IR[15:9] = 7Bh

LOAD:
R[d]  M[ R[s1] ] HALT:

IR[15:9] = 79h IR[15:9] = 7Ah

STORE: LOAD_ imm:

M[ R[d] ]  R[s1] R[d]  M[PC]
PC  PC +1

FETCH

`timescale 1ps / 100fs

/***********************************************************************
* Date: August 11, 2014
* File: 301_control_unit.v
*
* A “Moore” finite state machine that implements the major cycles for
* fetching and executing instructions for the 301 16-bit RISC Processor.
************************************************************************/

//*******************************************************************
module cu (clk, reset, IR, N, Z, C, // control unit inputs
W_Adr, R_Adr, S_Adr, // these are
adr_sel, s_sel, // the control
pc_ld, pc_inc, pc_sel, ir_ld, // word output
mw_en, rw_en, alu_op, // fields
status); // LED outputs
//*******************************************************************

input clk, reset; // clock and reset

input [15:0] IR; // instruction register input
input N, Z, C; // datapath status inputs
output [2:0] W_Adr, R_Adr, S_Adr; // register file address outputs
output adr_sel, s_sel; // mux select outputs
output pc_ld, pc_inc, pc_sel, ir_ld; // pc load, pcinc, pc select, ir load
output mw_en, rw_en; // memory_write, register_file write
output [3:0] alu_op; // ALU opcode output
output [7:0] status; // 8 LED outputs to display current state

301 Lab Assignment 8 – Page 4

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

/****************************
* data structures *
****************************/

reg [2:0] W_Adr, R_Adr, S_Adr; //these 12

reg adr_sel, s_sel; // fields
reg pc_ld, pc_inc; // make up
reg pc_sel, ir_ld; // the
reg mw_en, rw_en; // control word
reg [3:0] alu_op; // of the control unit

reg [4:0] state; // present state register

reg [4:0] nextstate; // next state register
reg [7:0] status; // LED status/state outputs
reg ps_N, ps_Z, ps_C; // present state flags register
reg ns_N, ns_Z, ns_C; // next state flags register

parameter RESET=0, FETCH=1, DECODE=2,

ADD=3, SUB=4, CMP=5, MOV=6,
INC=7, DEC=8, SHL=9, SHR=10,
LD=11, STO=12, LDI=13,
JE=14, JNE=15, JC=16, JMP=17,
HALT=18,
ILLEGAL_OP=31;

/*********************************
* 301 Control Unit Sequencer *
*********************************/

// synchronous state register assignment

always @(posedge clk or posedge reset)
if (reset)
state = RESET;
else
state = nextstate;

// synchronous flags register assignment

always @(posedge clk or posedge reset)
if (reset)
{ps_N,ps_Z,ps_C} = 3'b0;
else
{ps_N,ps_Z,ps_C} = {ns_N,ns_Z,ns_C};

// combinational logic section for both next state logic

// and control word outputs for cpu_execution_unit and memory
always @( state )
case ( state )

RESET: begin // Default Control Word Values -- LED pattern = 1111_111

W_Adr = 3'b000; R_Adr = 3'b000; S_Adr = 3'b000;
adr_sel = 1'b0; s_sel = 1'b0;
pc_ld = 1'b0; pc_inc = 1'b0; pc_sel=1’b0; ir_ld = 1'b0;
mw_en = 1'b0; rw_en = 1'b0; alu_op = 4'b0000;
{ns_N,ns_Z,ns_C} = 3'b0;
status = 8'hFF;
nextstate = FETCH;
end

FETCH: begin // IR <-- M[PC], PC <- PC+1 -- LED pattern = 1000_000

W_Adr = 3'b000; R_Adr = 3'b000; S_Adr = 3'b000;
adr_sel = 1'b0; s_sel = 1'b0;
pc_ld = 1'b0; pc_inc = 1'b1; pc_sel=1’b0; ir_ld = 1'b1;
mw_en = 1'b0; rw_en = 1'b0; alu_op = 4'b0000;
{ns_N,ns_Z,ns_C} = {ps_N,ps_Z,ps_C}; // flags remain the same
status = 8'h80;
nextstate = DECODE;
end

301 Lab Assignment 8 – Page 5

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

DECODE: begin // Default Control Word Values -- LED pattern = 1100_0000

W_Adr = 3'b000; R_Adr = 3'b000; S_Adr = 3'b000;
adr_sel = 1'b0; s_sel = 1'b0;
pc_ld = 1'b0; pc_inc = 1'b0; pc_sel=1’b0; ir_ld = 1'b0;
mw_en = 1'b0; rw_en = 1'b0; alu_op = 4'b0000;
{ns_N,ns_Z,ns_C} = {ps_N,ps_Z,ps_C}; // flags remain the same
status = 8'hC0;
case ( IR[15:9] )
7'h70: nextstate = ADD;
7'h71: nextstate = SUB;
7'h72: nextstate = CMP;
7'h73: nextstate = MOV;
7'h74: nextstate = SHL;
7'h75: nextstate = SHR;
7'h76: nextstate = INC;
7'h77: nextstate = DEC;
7'h78: nextstate = LD;
7'h79: nextstate = STO;
7'h7a: nextstate = LDI;
7'h7b: nextstate = HALT;
7'h7c: nextstate = JE;
7'h7d: nextstate = JNE;
7'h7e: nextstate = JC;
7'h7f: nextstate = JMP;
default: nextstate = ILLEGAL_OP;
endcase
end

ADD: begin // R[ir(8:6)] <-- R[ir(5:3)] + R[ir(2:0)] -– LED pattern = {ps_N,ps_Z,ps_C,5’b00000}

// PUT CONTROL WORD FOR EXECUTION OF ADD HERE!!!
nextstate = FETCH; // go back to fetch
end

SUB: begin // R[ir(8:6)] <-- R[ir(5:3)] - R[ir(2:0)] -– LED pattern = {ps_N,ps_Z,ps_C,5’b00001}

// PUT CONTROL WORD FOR EXECUTION OF SUB HERE!!!
nextstate = FETCH; // go back to fetch
end

CMP: begin // R[ir(5:3)] - R[ir(2:0)] -– LED pattern = {ps_N,ps_Z,ps_C,5’b00010}

// PUT CONTROL WORD FOR EXECUTION OF CMP HERE!!!
nextstate = FETCH; // go back to fetch
end

MOV: begin // R[ir(8:6)] <-- R[ir(2:0)] -– LED pattern = {ns_N,ns_Z,ns_C,5’b00011}

// PUT CONTROL WORD FOR EXECUTION OF MOV HERE!!!
nextstate = FETCH; // go back to fetch
end

SHL: begin // R[ir(8:6)] <-- R[ir(2:0)] << 1 -– LED pattern = {ps_N,ps_Z,ps_C,5’b00100}

// PUT CONTROL WORD FOR EXECUTION OF SHL HERE!!!
nextstate = FETCH; // go back to fetch
end

SHR: begin // R[ir(8:6)] <-- R[ir(2:0)] >> 1 -– LED pattern = {ps_N,ps_Z,ps_C,5’b00101}

// PUT CONTROL WORD FOR EXECUTION OF SHR HERE!!!
nextstate = FETCH; // go back to fetch
end

INC: begin // R[ir(8:6)] <-- R[ir(2:0)] + 1 -– LED pattern = {ps_N,ps_Z,ps_C,5’b00110}

// PUT CONTROL WORD FOR EXECUTION OF INC HERE!!!
nextstate = FETCH; // go back to fetch
end

301 Lab Assignment 8 – Page 6

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

DEC: begin // R[ir(8:6)] <-- R[ir(2:0)] - 1 -– LED pattern = {ps_N,ps_Z,ps_C,5’b00111}

// PUT CONTROL WORD FOR EXECUTION OF DEC HERE!!!
nextstate = FETCH; // go back to fetch
end

LD: begin // R[ir(8:6)] <-- M[ir(2:0)] -– LED pattern = {ps_N,ps_Z,ps_C,5’b01000}

// PUT CONTROL WORD FOR EXECUTION OF LOAD HERE!!!
nextstate = FETCH; // go back to fetch
end

STO: begin // M[ir(8:6)] <-- R[ir(2:0)] -– LED pattern = {ps_N,ps_Z,ps_C,5’b01001}

// PUT CONTROL WORD FOR EXECUTION OF STO HERE!!!
nextstate = FETCH; // go back to fetch
end

LDI: begin // R[ir(8:6)] <-- M[PC], PC <-- PC + 1 -– LED pattern = {ps_N,ps_Z,ps_C,5’b01010}

// PUT CONTROL WORD FOR EXECUTION OF LDI HERE!!!
nextstate = FETCH; // go back to fetch
end

JE: begin // if (ps_Z=1) PC <-- PC + se_IR[7:0] -– LED pattern = {ps_N,ps_Z,ps_C,5’b01100}

// PUT CONTROL WORD FOR EXECUTION OF JE HERE!!!
nextstate = FETCH;
end

JNE: begin // if (ps_Z=0) PC <-- PC + se_IR[7:0] -– LED pattern = {ps_N,ps_Z,ps_C,5’b01101}

// PUT CONTROL WORD FOR EXECUTION OF JNE HERE!!!
nextstate = FETCH;
end

JC: begin // if (ps_C=1) PC <-- PC + se_IR[7:0] -– LED pattern = {ps_N,ps_Z,ps_C,5’b01110}

// PUT CONTROL WORD FOR EXECUTION OF JC HERE!!!
nextstate = FETCH;
end

JMP: begin // PC <-- R[ir(2:0)] -– LED pattern = {ps_N,ps_Z,ps_C,5’b01111}

// PUT CONTROL WORD FOR EXECUTION OF JMP HERE!!!
nextstate = FETCH;
end

HALT: begin // Default Control Word Values -– LED pattern = {ps_N,ps_Z,ps_C,5’b01011}

// PUT CONTROL WORD FOR HALT HERE!!!
nextstate = HALT; // loop here forever
end

ILLEGAL_OP: begin // Default Control Word Values -- LED pattern = 1111_0000

// PUT CONTROL WORD FOR ILLEGAL OPCODE HERE!!!
nextstate = ILLEGAL_OP; // loop here forever
end
endcase

endmodule

Note that the 8-bit “status register” is used to drive the eight LED’s (LD7 to LD0) with unique patterns to display what
state the CU is in. In addition, for the execution states for all opcodes, we display the concatenation of the present
state of the flags register and the instruction opcode.
Once the RISC Processor executes a “Halt” instruction, press reset. Then set the “dump_mem” switch to “1.”
Memory will now display location M[00h]. To step through memory, just press the step_mem button to increment
the internal “mem_counter.” This will allow you to verify the address (AD_sel=1) and contents (AD_sel=0) of memory.

301 Lab Assignment 8 – Page 7

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

Lab #8 – PC Modifications
General Statement: In order for your RISC processor to be able to execute both conditional and unconditional jump
instructions, there must be some modifications to the CPU_EU module developed in Lab #7. The conditional jump
instructions require the PC to be loaded with 16-bit values that are “relative” to its current value. Almost all processors do
“relative jumps” by adding the current contents of the PC to a signed “offset.” If the offset is expressed in less bits than
the PC itself (as is usually the case) then there must be a “sign extension” of the offset to make it the same size as the PC
before the addition. The logic diagram showing the modifications that must be made to accommodate this kind of
arrangement is show below.
The sign extension function is easily done in Verilog using the “replication” operator: {n{exp}} is equal to “n” copies of
“exp” concatenated together. Thus, for example, {5{IR[7]}} = {IR[7], IR[7], IR[7], IR[7], IR[7]}. The “SignExt” logic
in the diagram becomes nothing more than one conditional assignment statement that uses the replication operator for sign
extending our 8-bit signed offset to a 16-bit signed offset that is added to the PC.
Note, all logic color coded in yellow is combinational logic, whereas all logic color coded in blue is sequential logic. Also
note that the only extra control line needed for CPU_EU is the pc_sel control for the 2-to-1 MUX.

CPU_EU
DS
Integer
Datapath

Reg_Out ALU_Out

16

16

16-bit add
1 0
pc_sel
PC_mux 16
16 16

SignExt
pc_ld
PC 8
pc_inc ir_ld
16 IR

16
1 0
adr_sel adr_mux

16 D_out D_in
Address

301 Lab Assignment 8 – Page 8

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

Memory Address Binary Content Instruction Register Written

00 1111010_000_000_000
01 0101_1100_1010_1010
02 1111010_001_000_000
03 1010_0011_0101_0101
04 1111010_010_000_000
05 0000_0000_0011_0001
06 1110101_011_000_010
07 1110000_100_001_000
08 1111001_011_000_100
09 1110111_011_000_011
0A 1110100_101_000_001
0B 1111001_011_000_101
0C 1110111_110_000_011
0D 1111001_110_000_010
0E 1110110_000_000_100
0F 11111100_00000001
10 1111011_111111111
11 1110110_101_000_000
12 1110001_111_110_101
13 1111001_111_000_001
14 1111011_111111111
15 0000_0000_0000_0000
16 0000_0000_0000_0000
17 0000_0000_0000_0000
18 0000_0000_0000_0000
19 0000_0000_0000_0000
1A 0000_0000_0000_0000
1B 0000_0000_0000_0000
1C 0000_0000_0000_0000
1D 0000_0000_0000_0000
1E 0000_0000_0000_0000
1F 0000_0000_0000_0000

Detailed contents of “ram_256x8_lab8a.coe” initialization file

Final Contents of
CPU Reg’s and Memory:
R0 = R4 = M[15] =
R1 = R5 = M[16] =
R2 = R6 = M[17] =
R3 = R7 = M[18] =

Total # of instructions executed = ________

301 Lab Assignment 8 – Page 9

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

Memory Address Binary Content Instruction Register Written

00 1111010_000_000_000
01 0000_0000_0001_0000
02 1111010_001_000_000
03 0000_0000_0000_1000
04 1111010_010_000_000
05 0000_0000_0000_0001
06 1111010_011_000_000
07 0000_0000_1111_1110
08 1110000_011_011_010
09 1111001_000_000_011
0A 1110110_000_000_000
0B 1110100_011_000_011
0C 1110111_001_000_001
0D 11111010_11111010
0E 1111011_111111111
0F 1111011_111111111
10 0000_0000_0000_0000
11 0000_0000_0000_0000
12 0000_0000_0000_0000
13 0000_0000_0000_0000
14 0000_0000_0000_0000
15 0000_0000_0000_0000
16 0000_0000_0000_0000
17 0000_0000_0000_0000
18 0000_0000_0000_0000
19 0000_0000_0000_0000
1A 0000_0000_0000_0000
1B 0000_0000_0000_0000
1C 0000_0000_0000_0000
1D 0000_0000_0000_0000
1E 0000_0000_0000_0000
1F 0000_0000_0000_0000

Detailed contents of “ram_256x8_lab8b.coe” initialization file

Final Contents
of Memory
M[10] = M[14] =
M[11] = M[15] =
M[12] = M[16] =
M[13] = M[17] =

Total # of instructions executed = _________

301 Lab Assignment 8 – Page 10

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

Memory Address Binary Content Instruction Register Written

00 1111010_000_000_000
01 0000_0000_0001_1000
02 1111000_001_000_000
03 1110110_000_000_000
04 1111000_010_000_000
05 1111010_000_000_000
06 0000_0000_0001_0000
07 1111010_011_000_000
08 0000_0000_0000_1001
09 1111001_000_000_001
0A 1110101_001_000_001
0B 1110110_000_000_000
0C 1110010_000_000_010
0D 11111000_00000001
0E 1111111_000_000_011
0F 1111011_111111111
10 0000_0000_0000_0000
11 0000_0000_0000_0000
12 0000_0000_0000_0000
13 0000_0000_0000_0000
14 0000_0000_0000_0000
15 0000_0000_0000_0000
16 0000_0000_0000_0000
17 0000_0000_0000_0000
18 1111_1111_1111_1111
19 0000_0000_0001_1000
1A 0000_0000_0000_0000
1B 0000_0000_0000_0000
1C 0000_0000_0000_0000
1D 0000_0000_0000_0000
1E 0000_0000_0000_0000
1F 0000_0000_0000_0000

Detailed contents of “ram_256x8_lab8c.coe” initialization file

Final Contents
of Memory
M[10] = M[14] = M[18] =
M[11] = M[15] = M[19] =
M[12] = M[16] =
M[13] = M[17] =

Total # of instructions executed = ________

301 Lab Assignment 8 – Page 11

Lab Project 8: 16-bit RISC Processor © 201 4 R . W. A l l ison
Revision: August 8, 2014 C ECS 301 – CS ULB

CECS 301 Team Accountability Reporting Sheet

Team Member #1: ___________________________ Signature: ______________________________

Modules/dates you worked on:______________________________________ Hours: _______

_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______

Modules/dates you debugged: _______________________________________ Hours: _______

_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______

Team Member #2: ___________________________ Signature: ______________________________

Modules/dates you worked on:______________________________________ Hours: _______

_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______

Modules/dates you debugged: _______________________________________ Hours: _______

_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______
_________________________________________ Hours: _______

Percentage of Work Summary: Team Member#1 __________ Team Member#2 __________

301 Lab Assignment 8 – Page 12