University of British Columbia

ELEC 501 – Analog Integrated Circuit Design

Nyquist-Rate DAC and ADC
Assignment #2
Name: Mateo Rendon Instructor: Dr. Reza Molavi
UBC Student Code: 94907193 Section: 201
Due Date: February 3rd, 2022 Hours: 17h30 – 18h30
1. In the following R-2R based DAC.

c) Using an ideal op-amp model and appropriate switch model to provide an 80mV voltage drop, validate
the calculations on b) with SPICE/Cadence simulations (25 points).
As previously demonstrated, the configuration of the R-2R DAC basically shifts the voltage drop in the
switches to the input voltage −𝑉𝑟𝑒𝑓 as an effect of non-linearity. Therefore, if the DAC is designed to have
switches with a drop of 80 [mV], the maximum value won’t be 𝑉𝑟𝑒𝑓 but 𝑉𝑟𝑒𝑓 − 80 [𝑚𝑉]. Consider a 𝑉𝑟𝑒𝑓 of
1 [𝑉], the LSB value for this non-ideal implementation would be:
𝑉𝑟𝑒𝑓 − 𝑉𝑑𝑟𝑜𝑝 1 − 0.08
𝑉𝐿𝑆𝐵 = = = 57.5 [mV]
2𝑁 24
This deviation from the ideal value of 𝑉𝐿𝑆𝐵 = 62.5 [mV] without a voltage drop. Furthermore, the binary
word of 1111 would be represented by 862.5 [mV] instead of 937.5 [mV].

Figure 1: R-2R based 4-bit DAC implementation using nMOS transistors as switches.
 The implementation in Cadence is shown in Fig 1. An Ideal OpAmp is used for this circuit. The resistors
have values of 𝑅 = 𝑅𝐹 = 500 [Ω] so that the gain of the circuit is 1. The bit word 𝑏1 𝑏2 𝑏3 𝑏4 is simulated using
vpulse sources with periods of 1 [𝜇𝑠], 2 [𝜇𝑠], 4 [𝜇𝑠], 8 [𝜇𝑠] so that the full truth table can be reproduced. The
nominal supply voltage is 1 [𝑉] as well as 𝑉𝑟𝑒𝑓 .

The length of the transistors was kept as 𝐿 = 45 [nm] to minimize the on-resistance while the different
values of 𝑊, 𝑊1 , 𝑊2 , 𝑊3 , 𝑊4 corresponding to the S4 switch and bit words respectively were sized to obtain a
𝑉𝐷𝑆 voltage drop of ~80 [𝑚𝑉] using the values from Fig. 2.

Figure 2: Variables used for the design.

The voltage drop in the transistors (i.e. the 𝑉𝐷𝑆 value) is shown in Fig. 3. On the left, it can be seen that
all the voltages are centered around 80 [𝑚𝑉] and peaks with a higher voltage occur when the input binary word
𝑏1 𝑏2 𝑏3 𝑏4 switches (as can be seen from the fact that they only happen in multiples of 0.5 [𝜇𝑠] which is the on-
value of the signal). A zoomed version is presented on the right where it can be observed that for each
transistor, the sizing selected produces voltage drops in the range of [79.5041mV, 80.809mV].

Figure 3: Vds Values of the nMOS switches in the DAC.

The inputs of the DAC are presented in Fig. 4 where it is evident that the whole truth table for the DAC
is being formed and that the reference voltage has a value of -1.
 Figure 4: DAC Inputs

The output of the DAC is presented in Fig. 5 where the staircase behavior expected is observed. The key
values of 𝑏1 𝑏2 𝑏3 𝑏4 = 0000 and 𝑏1 𝑏2 𝑏3 𝑏4 = 1111 have been marked. Note that there are glitches happening
during each word transition. The highest value of the glitches occur with the transition 0111 → 1000 followed
by the transitions 0011 → 0100 and 1011 → 1100 as expected .

Figure 5: DAC Output

Using a 𝑉𝑟𝑒𝑓 value of 1 [𝑉], a switch drop of 80 [𝑚𝑉] and for a 4-bit DAC, the expected and actual
values are presented in Table 1 along with the absolute difference and relative error. It can be noted that the
actual and expected voltages match closely mainly due to the having such a tight range around 80 [𝑚𝑉] for the
voltage drops. The average relative error is therefore %0.25. Finally, the absolute difference between expected
and actual voltages is plotted in Fig. 6 where it can be observed that binary words 0 and 8 represent the major
sources of error.
Table 1: Results Summary

Figure 6: Absolute Difference between the Expected and Actual Voltages per Binary Code
 Furthermore, a deeper analysis of the errors produced due to non-linearity is presented in Table 2. The
offset and gain errors for the case of 1V as reference voltage are presented, as well as the INL and DNL errors
for each binary word.
Table 2: Errors due to non-linearity summary
Question 3 – Annex
Figure 7 was created as a diagram to understand the MSB from Question 3. As the question stated, the
internal voltages of the bolding block (Va to Vd) are being used to obtain the MSB bits b1, b2, and b3. This is
helpful since it means that an additional MSB block doesn’t need to be designed, so the input signal Vin doesn’t
need to be loaded to additional BJTs or comparators. Therefore, the load capacitance seen by Vin is only
dependent of the 4 folding blocks with a folding rate of 8, that is 32C.

Figure 7: Diagram of a folding block with a folding rate of 8 where the MSB bits are obtained from the internal voltages