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UNIT IV
ANALOG TO DIGITAL CONVERTER & DIGITAL TO ANALOG CONVERTER

4.1 INTRODUCTION
Most of the real-world physical quantities such as voltage, current,
temperature, pressure and time etc. are available in analog form. Even though an
analog signal represents a real physical parameter with accuracy, it is difficult to
process, store or transmit the analog signal without introducing considerable error
because of the superimposition of noise as in the case of amplitude modulation.
Therefore, for processing, transmission and storage purposes, it is often convenient
to express this variable in digital form. It gives better accuracy and reduces noise.
The operation of any digital communication system is based upon analog to digital
(A/D) and digital to analog (D/A) conversion.
Fig 4.1 highlights a typical application within which A/D and D/A conversion is
used. The analog signal obtained from the transducer is band limited by antialiasing
filter. The signal is then sampled at a frequency rate more than twice the maximum
frequency of the band limited signal. The sampled signal has to be held constant
while conversion is taking place in A/D converter. This requires that ADC should be
preceded by a sample and hold (S/H) circuit. The ADC output is a sequence in
binary digit. The micro-computer or digital signal processor performs the numerical
calculations of the desired control algorithm. The D/A converter is to convert digital
signal into analog and hence the function of DAC is exactly opposite to that of ADC.
The D/A converter are usually operated at the same frequency as the ADC. The
output of a D/A converter is commonly a staircase. This staircase-like digital output is
passed through a smoothing filter to reduce the effect of quantization noise.

Fig: 4.1Circuit showing application of A/D and D/A converter

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The scheme given in Fig. 4.1 is used either in full or in part in applications
such as digital audio recording and playback, computer, music and video synthesis,
pulse code modulation transmission, data acquisition, digital multimeter, direct digital
control, digital signal processing, microprocessor based instrumentation.
Both ADC and DAC are also known as data converters and are available in
1C form. It may be mentioned here that for slowly varying signal, sometimes sample
and hold circuit may be avoided without considerable error. The A-D conversion
usually makes use of a D-A converter so we shall first discuss DAC followed by
ADC.
4.2 BASIC DAC TECHNIQUES
The schematic of a DAC is shown in Fig. 4.2. The input is an n-bit binary word
D and is combined with a reference voltage VR to give an analog output signal. The
output of a DAC can be either a voltage or current. For it voltage output DAC, the
D/A converter is mathematically described us

_______(1)
Where Vo — output voltage
VFS = full scale output voltage
K = scaling factor usually adjusted to unity
dI d2....dn= n-bit binary fractional word with the decimal point located at the left
d1= most significant bit (MSB) with a weight of VFS/2
dn - least significant bit (LSB) with a weight of VFS/2n

Fig 4.2 Schematic of a DAC

Here discuss the fallowing resistive techniques only: Weighted resistor DAC R-2R
ladder Inverted R-2R Ladder
4.3 WEIGHTED RESISTOR DAC
One of the simplest circuits shown in Fig 4.3(a) uses a summing amplifier with
a binary weighted resistor network. It has n-electronic switches dI d2....dn controlled
by binary input word. These switches are single pole double throw (SPDT) type. If
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the binary input to a particular switch id 1, the resistance to the reference voltage (-
V/R). And if the input bit is 0, the switch, connects the resistor to the ground. From
Fig. 4.3(a), the output current for an ideal op-amp can be written as

_______(2)
Comparing Eqn. (1) with Eqn. (2) it can be seen that if Rf = R then K = 1 and VFS =
VR.
The circuit shown in Fig. 4.3(a) uses a negative reference voltage. The analog
output voltage is therefore positive staircase as shown in Fig. 4.3(b) for a 3-bit
weighted resistor DAC. It may be noted that

(i) Although the op-amp in Fig. 4.3(a) is connected in inverting mode, it can also be
connected in non-inverting mode.
(ii) The op-amp is simply working as a current to voltage converter.
(iii) The polarity of the reference voltage is chosen in accordance with the type of the
switch used. For example, for TTL compatible switched, the reference voltage should
be + 5V and the output will be negative.
The accuracy and stability of a DAC depends upon the accuracy of the
resistors and the tracking of each other with temperature. There is however a
number of problems associated with this type of DAC One of the disadvantages of
binary weighted type DAC is the wide range of resistor values required. It may be
observed that for better resolution, the input binary word length has to be increased.
Thus, as the number of bit increases, the range of resistance: value increases.
The largest resistor is 128 times the smallest one for only 8-bit DAC. For a 12-
bit DAC, the largest resistance required is 5.12 MΩ if the smallest is 2,5 kΩ. The
fabrication of such a large resistance in IC is not practical. Also the voltage drop
across such a large resistor due to the bias current would also affect the accuracy.
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The choice of smallest resistor value as 2.5kΩ is reasonable- otherwise loading

effect will be there. The difficulty of achieving and maintaining accurate ratio over
such a wide range especially in monolithic form restricts the use of weighted resistor
DACs to below 8-bits.
The switches shown in Fig. 4.3 (a) are in series with resistors and therefore,
their own resistance must be very low and they should have zero Offset voltage.
Bipolar transistors do not perform well as voltage switches, due to the inherent offset
voltage when in saturation. However, by' using MOSFET, this can be achieved.

Fig.4.3 (a) A simple weighted resistor DAC (b) Transfer characteristics of a 3 bit DAC

4.4. R-2R LADDER CIRCUIT

Wide range of resistors is required in binary weighted resistor type DAC. This
can be avoided by using R-2R ladder type DAC where only two values of resistor are
required. It is well suited for integrated circuit realization. The typical value of R
ranges from 2.6 KΩ to 10 KΩ. For simplicity, consider a 3-bit DAC as shown in Fig
4.4(a), where the switch position d1,d2,d3 corresponds to the binary word 100. The
circuit can be simplified to the equivalent form of Fig.4.4 Then, voltage at node C can
be easily calculated by the set procedure of network analysis as

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Fig.4.4 (a) R-2R ladder DAC (b) Equivalent circuit of (a), (c) Equivalent circuit of (b)

The switch position corresponding to the binary word 001 in 3 bit DAC is
shown in Fig. 4.5 (a). The circuit can be simplified to the equivalent form of Fig. 4.5
(b). The voltages at the nodes (A, B, C) formed by resistor branches are easily
calculated in a similar fashion and the output voltage becomes

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Fig.4.5 (a) R-2R ladder DAC for switch positions 001 (b) Equivalent circuit

4.5. INVERTED R-2R LADDER

In weighted resistor type DAC and R-2R ladder type DAC, -current flowing in
the resistors changes as the input data changes. More power dissipation causes
heating, which in turn, creates non-linearity In DAC, This is a serious problem and
can be avoided completely in 'Inverted R-2R ladder type DAC. A 3-hit Inverted R-2R
ladder type DAC is shown in Fig. 4.6(a) where the position of MSB end LSB is
interchanged. Here each input binary word connects the corresponding switch either
to ground or to the inverting input terminal of the op- amp which ie also at virtual
ground, Since both the terminals of switches are at ground potential, current
flowing1 in the reactance is constant and independent of switch position, i.e.
independent of input binary word.

In Fig, 4.6 (a), when switch di is at logical 0 i.e., to the left, the current through
2R resistor flows to the ground and when the switch di is at logical ‘1’ ie„ to the right,
the current through 2R sinks to the virtual ground. The circuit has the important
property that the current divides equally at each of the nodes. This is because the
equivalent resistance to the right or to the left of any node is exactly 2 R.

The division of the current is shown, in Fig 4.6 (b). Consider a reference
current of 2 mA. Just to the right of node A. similarly to the right of node B, the
equivalent resistor is 2 R Thus 1 mA of current further divides to value 0.5 mA at
node B. Similarly, current divides equally at node C to 0.25 mA. The equal division of
current in successive nodes remains the same in the 'inverted R-2R ladder
irrespective of the input binary word. Thus the Currents remain constant in each
branch of the ladder.
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Fig.4.6(a) Inverted R-2R ladder DAC (b) Inverted R-2R ladder DAC showing division
of current for digital input word 001

4.6 ANALOG TO DIGITAL CONVERTER

An analog-to-digital converter (ADC, A/D, or A to D) is a device that converts
a continuous physical quantity (usually voltage) to a digital number that represents
the quantity's amplitude.

The conversion involves quantization of the input, so it necessarily introduces

a small amount of error. Instead of doing a single conversion, an ADC often performs
the conversions ("samples" the input) periodically. The result is a sequence of digital
values that have been converted from a continuous-time and continuous-
amplitude analog signal to a discrete-time and discrete-amplitude digital signal.

An ADC is defined by its bandwidth (the range of frequencies it can measure)

and its signal to noise ratio (how accurately it can measure a signal relative to the
noise it introduces). The actual bandwidth of an ADC is characterized primarily by
its sampling rate and to a lesser extent by how it handles errors such as aliasing.
The dynamic range of an ADC is influenced by many factors, including the resolution
(the number of output levels it can quantize a signal to), linearity and accuracy (how
well the quantization levels match the true analog signal) and jitter (small timing
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errors that introduce additional noise). The dynamic range of an ADC is often
summarized in terms of its effective number of bits (ENOB), the number of bits of
each measure it returns that are on average not noise.

4.7 SAMPLE & HOLD CIRCUIT

A sample and hold circuit samples an input signal and holds on to its Last
sampled value until the input is sampled again. This type of circuit is very useful in
digital interfacing and analog to digital and pulse code modulation systems. One of
the simplest practical sample and hold circuit configuration is shown in Fig. 4.7(a).
The n-channel E-MOSFET works as a switch and is controlled by the control voltage
vc and the capacitor C stores the charge.

The analog signal vi to be sampled is applied to the drain of E-MOSFET and

the control voltage vc is applied to its gate. When v is positive, the E MOSFET turns
on and the capacitor C charges to the instantaneous value of input vi with a time
constant [R0 + rDS(ON)]C.Here R0 is the output resistance of the MOSFET when ON.
Thus the input voltage vi appears across the capacitor C and then at the output
through the voltage follower A2 .

During the time when control voltage Vc is zero, the E-MOSFET is off. The
capacitor C is now facing the high input impedance of the voltage follower A2 and
hence cannot discharge. The capacitor holds the voltage across it. The time period
Ts the time during which voltage across the capacitor is equal to input voltage called
sample period. The time period TH of Vc during which the voltage across the
capacitor is held constant is called hold period. The frequency of the control voltage
should be kept higher than the input so as to retrieve the input waveform. A low
leakage capacitor such as polystyrene, Mylar or Teflon should be used to retain the
storage charge.

Fig.4.7 (a) Sample and hold circuit (b) Input and output waveforms
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4.8 DAC /ADC SPECIFICATIONS

Both D/A and A/D converters are available with wide range of specifications.
The various important specifications of converters generally specified by the
manufacturers are analyzed.

Resolution: The resolution of a converter is the smallest change m voltage which

may be produced at the output (or input) of the converter. For example, an 8-bit D/A
converter have 28-1 = 255 equal intervals. Hence the smallest change in output
voltage is (1/255) of the full scale output range. In short, the resolution is the value of
the LSB

Similarly, the resolution of an A/D converter is defined as the smallest change

in analog input for a one bit change at the output. As an example, the input range of
an 8-bit A/D converter divided into 255 intervals. So the resolution for a 10 V input
range is 39.52mV (= 10 V/25-5).
Linearity:The linearity of an A/D or D/A converter is an important measure of its
accuracy and tells us how close the output is to its ideal transfer-characteristics.

Accuracy: Absolute accuracy is the maximum deviation between the actual

converter output and the ideal converter output. Relative accuracy is the maximum
deviation after gain and offset errors have been removed.

Monotonocity: A monotonic DAC is the one whose analog output increases for an
increase in -digital input. Figure 4.8 represents the transfer curve for a non-mono
tonic DAC, since the output decreases when input code changes from 001 to 010. A
monotonic characteristic is essential in control applications, otherwise oscillations
can result. In successive approximation ADCs, a non monotonic characteristic may
lead to missing codes.

Fig.4.8 A non-monotonic 3-bit DAC

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Settling time: The most important dynamic parameter is the settling time. It
represents the time it takes for the output to settle within a specified band ± (1/2)
LSB of its final value following a code change at the input (usually a full scale
change).
Stability: The performance of converter changes with temperature, age and power
supply variations. So all the relevant parameters, such as offset, gain, linearity error
and monotonicity must be specified over the full temperature and power supply
ranges.

DIRECT TYPE ADCs

4.9 THE PARALLEL COMPARATOR/FLASH
This is the simples possible A/D Converter. It is at the same time the fastest
and most expensive technique.fig shows a 3-bit A/D converter. The circuit consists of
a resistive divider network,8 op-amp comparators and a 8-line to 3-line encoder. The
comparator and its truth table are shown in Fig.4.9. A small amount of hysteresis is
built into the comparator to resolve any problems that might occur if both inputs were
of equal voltage as shown in the truth table. Coming back to Fig. 4.9 (a), at each
node of the resistive divider, a comparison voltage is available.

Since all the resistors are or equal value, the voltage levels available at the
nodes are equally divided between the reference voltage V R and the ground. The
purpose of the circuit is to compare the analog input voltage V a with each of the node
voltages. The truth table for the flash, type AD converter is shown in fig. 4.9 (c).The
circuit has the advantage of high speed as the conversion take place simultaneously
rather than sequentially. Typical conversion time is l00 ns or less. Conversion time is
limited only by the speed of the comparator and of the priority encoder.

This type of ADC has the disadvantage that the number of comparators
required almost doubles for each added bit. A 2-bit ADC requires 3 comparators, 3-
bit ADC needs 7, whereas 4-bit requires 15 comparators. In general the number of
comparators required is 2" — 1 where n is the desired number of bits. Hence the
number of comparators approximately doubles for each added bit. Also the larger the
value of n, the more complex is the priority encoder.

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Fig.4.9 (a) Basic circuit of flash type ADC (b) comparator truth table

Fig.4.9(c) Truth table for a flash type ADC

4.10 DUAL SLOPE

Figure 4.10(a) shows the functional diagram of the dual-slope or dual-romp
converter. The analog part of the circuit consists of a high input impedance buffer Al ,
precision integrator A2 and a voltage comparator. The converter first integrates the
analog input signal Va for a fixed duration of '2n clock periods as shown in Fig.4.10
(b). Then it integrates an internal reference voltage VR of opposite polarity until the
integrator output is zero. The number N of clock cycles required to return the
integrator to zero is proportional to the value of VA averaged over the integration
period. Hence N represents the desired output code. The circuit operates as follows:
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Fig4.10 (a) Functional diagram of Dual slope ADC (b) integrated output waveform

Before the START command arrives, the switch SW1, is connected to ground
and SW2 is closed. Any offset voltage present in the A1, A2, comparator loop after
integration, appears across the capacitor CAZ till the threshold of the comparator is
achieved. The capacitor CAZ thus provides automatic compensation for the input-
offset voltages of all the three amplifiers. Later, when SW2, opens, CAZ acts as a
memory to hold the voltage- required to- keep the offset nulled.

At the arrival of the START command at t=t1, the control logic opens SW2
and connects SW1 to Va and enables the counter starting- from zero. The circuit
uses an n-stage ripple counter and therefore the counter resets to zero after
counting' 2n pulses. The analog voltage Va is integrated For a fixed number 2n
counts of clock pulses after which, the counter resets to zero. If the clock period is T,
the integration takes place for a time T1=2" X T and the output is a ramp .going
downwards as shown in Fig 4.10.

The counter resets itself to zero at the end of the interval T1, and the switch
SW1, is connected to the reference voltage (-VR}, the output voltage will now have a
positive slope. As long as V0 is negative, the output of the comparator is positive and
the control logic allows the clock pulse to be counted.
However, when V0 becomes just zero at time t=t3, the control logic issues an
end of conversion (EOC) command and no further clock pulses enter the counter. It

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can be shown that the reading of the counter at t3 is proportional to the analog input
voltage Va

The voltage will be equal to v1 at the instant t2 and can be written as

The main disadvantage of the dual-s-lope ADC is the long conversion time,
For instance, if 2n— T = 1/50is used to reject line pick -up. the conversion time will
he 20 ms.
Dual-slope converters are particularly suitable for accurate measurement of
slowly varying signals,, such as thermocouples and weighing- scales. DuaL-slope
ADCs also farm the basis of digital panel meters and multimeters.

4.11. OVER SAMPLING A/D CONVERTER

In conventional A/D converters (the so-called Nyquist rate category) the input
signal is sampled at a rate that is only twice that of the band of the input signal itself.
The digital output, generated at the same rate, following to the sampling theorem,
retains alt the informative contents of the input signal which represents it. However,
in order to avoid aliasing, the input signal must be band-limited by an anti-aliasing
filter before sampling. Such analog filters suffer from limitations such as noise,
distortion, group delay, and pass band ripple; unless great care is taken, it is difficult
for downstream A/D converters to achieve resolution beyond 18-bits.

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In many applications, brick-wall analog anti-aliasing filters and SAR A/D

converters have been replaced by over sampling A/D converters with digital
filters.A/D converter where the input signal is sampled much faster than the Nyquist
rate, is called an over sampling A/D converter The signal bandwidth of the input
signal is denoted by fb and the Nyquist rate, which is the minimum sampling
frequency required to avoid aliasing, equals

The over sampling ratio is defined as the ratio between the sampling
frequency and the Nyquist rate. In other words, it indicates how much faster the input
signal is sampled than minimally required by the Nyquist theorem,

The principle of using over sampling is that by sampling ihe signal many
times, errors due to noise and coarse quantization arc averaged out. Through the
use of loop-filter and feedback, the noise is shaped to high frequencies, which can
be easily removed by digital filters.

Fig4.11 Block diagram of over sampled ADC

Anti-aliasing filter (AAF): It eliminates spectral components above half the

sampling frequency from the input signal so that the modulator input signal is band-
limited and the subsequent sampling operation does not alias input signals from
higher frequencies into the band of interest.

∑-∆ Modulator: It performs the actual A/D conversion by means of sampling and
quantizing the band-limited input signal as well as by filtering the quantization error

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from the internal quantizer out of the in-band. The internal feedback DAC is
commonly implemented with the same low resolution as the internal quantizer and
thus does not introduce an additional quantization error.

Decimation filter: After quantization, a digital low pass filter uses decimation both to
reduce the sampling frequency to a nominal rate and prevent aliasing at the new,
lower sampling frequency. Quantized data words are output at a lower frequency (for
example, 48 or 96 kHz).

The decimation low pass filter removes frequency components beyond the
Nyquist frequency of the output sampling frequency to prevent aliasing when the
output of the digital filter is resample (under-sampled) at the system's sampling
frequency.
The decimator typically consists of two different blocks. First, a digital low
pass filter is used to remove all the frequency components above to avoid signal
degradation due to aliasing in the down sampling block that follows the digital filter.
This digital filter also removes all the quantization noise which does not fall inside the
signal band. The digital filter operates in the digital domain and its output contains N-
bits words.
The next block in the decimation filter down-samples the output of the digital
filter. Down-sampling by a ratio of OSR can be done by simply keeping a sample and
remove the next OSR-1 samples. Since the sampling rate of signal is changed,
aliasing can occur. However, the decimation process does not result in loss of
information since the digital filter removes all the components that could alias in the
signal band.

4.12. SINGLE SLOPE A/D CONVERTER

The principle of operation of a single slope serial ADC to generate a ramp
voltage using DAC, which is compared with the input voltage. At the start of the
ramp, the counter is started to count from its initial value. When the ramp reaches
the analog voltage, the counter is stopped.

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The digital value in the counter is directly related to the input voltage .this
converter takes longer time to convert a large voltage than a small one and some
control signals are required for the start of conversions and end of conversions. The
maximum conversion time is 2NT, the disadvantage of this ADC is that it is unipolar
due to single slope ramp generator.

Fig 4.12 Block diagram of a single slope serial ADC (b) with EC & SC signals

This convertor consist of Ramp generator Binary counter, Comparator, and

AND gate. Here, the counter is used to generate digital output. Initially analog input
is sampled and Hold, and then applied to positive terminal of Comparator.
The Counter is in reset condition sampled and the clock is applied to counter
through an AND gate. When the first clock pulse is applied, the Ramp generator
starts to integrate a reference voltage V. When analog input voltage V in, is greater
than output of Ramp generator.
The comparator output is high and clock pulse is applied to the counter to
count clock pulse. If output of Ramp generator= Vin, the comparator output is low.
The counter stops counting. The output of the counter is the desired digital output of
analog voltage. Single slope serial ADC with starts of conversion (Sc) and End of
conversion (Ec) is illustrated in fig 4.12. The conversion sequence of single slope
ADC is given below
i. Start of conversation signal resets the counter to zero and enables the gate,
to allow clock pulses to be counted in counter.
ii. The counter outputs are fed into a DAC to generate a ramp output.
iii. Then ramp output is compared with the sampled input signal. The gate output
is high till the ramp voltage equals the input signal.
iv. When the ramp output voltage is equal to the input signal the gate output
becomes low and counting stops.
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v. The gate disabled signal can be used to indicate the end of conversion.

4.13 SUCCESSIVE APPROXIMATION TECHNIQUE

In this technique the basic idea is to adjust the DACs input code such
that its output is within +- ½ LSB of the analog input v1 to be A/D converted. the code
that achieves this represents the desired ADC output.
The successive approximation method uses very efficient code searching
strategy called binary search. It completes searching process for n-bit conversion in
just n clock periods. It consists of a DAC, a comparator and a successive
approximation register(SAR).

Fig 4.13 Block diagram of successive approximation ADC

The searching code process in successive approximation method is similar

to weighing an unknown material with a balance scale and a set of standard weights.
Let us assume that we have 1 kg,2 kg and 4 kg weights (SAR) plus a balance scale
(comparator and DAC).Now we will see the successive approximation analogy for 3-
bit ADC.
The analog voltage Vin is applied at one input of comparator. On receiving
start of conversion signal (SOC) successive approximation register sets 3-bit binary
code 1002 (b2=1) as an input of DAC. This is similar process of placing the unknown
weight on one platform of the balance and 4 kg weight on the other. The DAC
converts the digital word 100 and applies it equivalent analog output at the second
input of the comparator.

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The Comparator then compares two voltages just like comparing unknown
weight with 4 kg weight with the help of balance scale. If the input voltage is greater
than the analog output of DAC, successive approximation register keeps b 2 =1 and
makes b1=1(addition of 2kg weight to have total 6 kg weight ) otherwise it resets
b2=0 and makes b1=1 (replacing 2 kg weight). The same process is repeated for b 1
and b0.the status of b0,b1 and b2 bits gives the digital equivalent of the analog input.

Fig.4.12 Illustration of conversion process

The time for one analog to digital conversion must depend on both the
clock’s period T and number of bits n.It is given as,
TC =T(n+1)
Where TC = conversion time T = clock period N = number of bits

The dark lines in the figure shows setting and resetting actions of bits for
input voltage 5.2v, on the basis of comparison. It can be seen from the Figure that
one clock pulse is required for the successive approximation register to compare
each bit. However an additional clock pulse is usually required to reset the register
prior to performing a conversion.

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PART A(2 MARKS QUESTION AND ANSWER)

1. What is DAC?
A Digital to Analog converter is used to convert a digital signal to an analog signal.
Hence the input is an n-bit binary word D and is combined with a reference voltage
VR to give an analog output signal. The output of a DAC is either voltage or current.

2. What is ADC?
An ADC circuit accepts as analog input voltage Va and produces an output
d1,d2,…,dn of functional value D, so that D = d12-1 + d22-2 +……..+ dn2-n
Where, d1 is the Most Significant Bit (MSB)
dn is the Least Significant Bit (LSB)
3. List the various ADC techniques.
ADC’s are broadly classified into two types
a. Direct Type ADC’s
1.Flash type converter 2. Successive approximation type ADC
3.Tracking or Servo type converter 4. Counter type converter
b. Integrating Type ADC’s
1.Charge balancing type converter 2.Single slope converter
3.Dual slope converter
4. Give some advantages of DAC over ADC.
1.It is simpler than A/D converter 2.It can be used to form A/D converter.
5. What is meant by Direct type ADC?
Direct type ADC compares a given analog signal with the internally generated
equivalent signal.

6. What is meant by Integrating type ADC?

These type of ADC’s perform conversion in an indirect manner by first changing the
analog input signal to a function of time or frequency and then to corresponding
digital code.
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7. Mention the types of DAC techniques.

 Weighted resistor DAC √ Multiplying DAC
 R-2R ladder DAC
 Inverted R-2R ladder DAC (Current mode R-2R)
8. Write some important specifications of a DAC or ADC. (May/June 2013)
 Resolution √ Linearity √ Accuracy
 Monotonic √ Settling time √ Stability
9. What is integrating type converter?
An ADC converter that perform conversion in an indirect manner by first
changing the analog I/P signal to a linear function of time or frequency and then to a
digital code is known as integrating type A/D converter.

10. What are the main advantages of integrating type ADCs?

a. The integrating type of ADC's do not need a sample/Hold circuit at the input.
b. It is possible to transmit frequency even in noisy environment or in an isolated
form.

11. Explain in brief the principle of operation of successive Approximation

ADC.
The circuit of successive approximation ADC consists of a successive approximation
register (SAR), to find the required value of each bit by trial & error. With the arrival
of START command, SAR sets the MSB bit to 1. The O/P is converted into an
analog signal & it is compared with I/P signal. This O/P is low or High. This process
continues until all bits are checked.

12. Where do we use Successive approximation type ADC?

Successive approximation type ADC is used in applications where conversion speed
is an important parameter. Hence it is used in Data logger sand instruments.

13. What are the switches used in DAC?

The switches used in DAC are in series with the resistors and therefore, their ON
resistance must be low. Bipolar transistors do not perform well as voltage switches,
due to the inherent offset voltage when in saturation. However, by using MOSFET,
this can be achieved.

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14. What is the advantage of Inverted R-2R ladder DAC? (Or) Why is an
inverted R-2R ladder network DAC better than weighted resistor DAC and R-2R
ladder network DAC?
The most important advantage of Inverted R-2R ladder DAC is that since the ladder
node voltages remain constant the stray capacitances are not able to produce slow
down effects on the performance of the circuit.

15.Give the two advantages of SA type ADC. (May 2014)

1. Successive approximation type ADC is more versatile and superior than all other
ADCs.
2.n bit conversion takes n clock periods.

16. Define resolution of a data converter. (Apr-2010)

 Resolution is the number of different analog output values that can be
provided by a DAC. For a n-bit DAC, Resolution = 2n
 Resolution is also defined as the ratio of change in output voltage resulting
from a change of 1 LSB at the digital inputs.

17. Compare and contrast binary ladder and R-2R ladder DAC? (OR) What is
the advantage of R-2R DAC over Weighted resistor DAC? (OR) Why is the R-2R
ladder network DAC better than weighted resistor DAC? (Nov-2010)

Binary weighted resistor DAC R-2R Ladder DAC

1. Requires a wide range of resistor

1. Requires only two values of
values
resistors.

2. Due to the higher values of

2. No such restriction as only two
resistor required for the LSB, the
resistor values are used whatever
use of this type is restricted to
may be the number inputs
below 8 bits

18. Define resolution and conversion time of DAC. (Nov-2010,DEC 2011)

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 Resolution is the number of different analog output values that can be

provided by a DAC. For a n-bit DAC, Resolution = 2n
 Conversion time is the time taken by DAC to perform conversion of digital
signal into analog signal.

19. Define settling time of DAC? (May/June 2012)

It is the time required for the output of DAC to settle within plus or minus of LSB of
final value for a given digital input.

20. Define accuracy of D/A converter?(Apr-2011)

 Absolute accuracy is the maximum deviation between the actual converter
output and the ideal converter output.
 Relative accuracy is the maximum deviation after gain and offset error have
been removed.

21. What is Single slope ADC?

The Single slope ADC is also known as single ramp method. Here instead of using a
DAC with ramped output we use an integrator to generate saw tooth waveform,
which is then compared against the analog input by a comparator. The time it takes
for the sawtooth waveform to exceed the input signal voltage level is measured by
means of digital counter closed with a precise frequency square wave.

22. Give the applications Dual slope ADC.

 Dual slope ADC’s are particularly suitable for accurate measurement of slowly
varying signals, such as thermocouples and weighing scales.
 They are also used in the digital panel meters and Millimeters.

23. What are the control lines of ADC?

 Start input to tell ADC when to start the conversion process.
 EOC (End Of Conversion) output to announce when the conversion is
complete.

24. What is the disadvantage of Dual slope ADC? (May/June 2012)

The main disadvantage of dual slope ADC is the long conversion time.

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25. What is the disadvantage of Flash type ADC? (May/June 2013)

The main disadvantage of Flash type A/D converter is that the number of
comparators required almost doubles for each added bit.

26. Give the advantage of integrating type ADC (Apr-2010)

The integrating type of ADC do not require sample and hold circuit at the input.

27. What is the fastest ADC? State the reason? (Apr-2011)

The parallel comparator (Flash type) ADC is the fastest technique because the
conversion takes place simultaneously rather than sequentially.

28. What is sample and hold circuit. (May 2014)

A sample and hold circuit samples an input signal and holds on its last sampled
value the input is sampled again.

29. Draw a sample and hold circuit. (Nov/Dec2013)

30. Give applications of a sample and hold circuit.

 Digital interfacing
 Analog to Digital converters
 Pulse Code Modulation systems

31. List out the advantages of sample and hold circuits.

 It reduces the cross talk in the multiplexer.
 In the case of multi channel ADCs, synchronization can be achieved by
sampling signals from all channels at the same time.

32. What is Voltage to Time converters?

The linear ramp technique is essentially a voltage to time converter. As the name of
this technique implies, a linear ramp is used to convert an analog d.c signal in to a
front panel digital representation.

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33. Give the advantages of Voltage to Time converters.

1. Linearity 2.Accuracy 3. Stability of the oscillator
4. Absolute slope of the ramp and frequency setting

34. What is quantization error?

Quantization error is the error introduced by quantization process. The errors are
random in nature. The randomness occurs simply because of the difference between
the quantized digit and the actual digit at that instant.

35. Calculate the quantizing error for a 12-bit ADC with full scale Input voltage
of 4.095 V.
Quantization error = 0.5mV \\ QE = 0.5Mv
36. The basic step of a 9-bit DAC is 10.3mV. If 000000000 represents 0V, what
is the output for an input of 101101111.(May 15)
GIVEN: Resolution =10.3mV
The input output equation for a DAC is, VO = Resolution x D
Where, D is Decimal value of digital input.
VO is Output voltage
D = Decimal value of (101101111)2 = (367)10
Output voltage = 3.7801 V

37. Find the resolution of a 12-bit DAC.

SOLUTION: Resolution = 2n = 2 12 = 4192

38. Define Monotonicity with respect to DAC.

A monotonic DAC is one whose analog output increases for an increase in digital
input. If a DAC has to be monotonic, the error should be less than at each output
level.

39. What is quantization noise?

The quantization error can be observed by continuously sampling a time varying
analog signal with an ADC, converting it back to analog with a DAC, and taking the
difference between the two. The resulting signal is called quantization noise.

40. What are the sources of errors in DAC?

 Linearity error.

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 Offset error.
 Gain error.

PART B

1. (i) Explain the working of R-2R ladder DAC. (8)

(ii) Explain the working of success approximation ADC. (8)( May - 2010)
2. (i) A dual slope ABC uses a 16-bit counter and a 4 MHz clock rate. The maximum
input voltage is +10V. The maximum integrator output voltage should be -8V
when the counter has recycled through 2n counts. The capacitor used in the
integrator is 0.1µF . Find the value of resistor R of the integrator. (8)
(ii) What is a sample and hold circuit? Briefly explain its construction and
application. (8)( May - 2010)
3. Describe the operation of dual slope and successive approximation type ADC.
What are the advantages of dual slope ADC? [16]( Dec - 2010)
4. (i) Explain voltage mode and current mode operations of R-2R ladder type DAC.
(ii) Discuss the operation of sample and hold circuit with circuit diagram. [16]
(Dec - 2010)
5. (i) Explain the operation of a weighted resistor type D/A converter.(8)
(ii) what are the limitations in weighted resistor type D/A converters and explain
how this problem can be solved in R-2R ladder D/A converters.(8)( May -
2011)
6. (i) with neat block diagram explain in detail the successive approximation type
A/D converter.(8)
(ii)Explain the over sampling A/D converter with functional block diagram(8)
( May - 2011)(May 2015)
7. Explain the following types of D/A converters with suitable circuit diagrams:
(i)binary weighted resistor DAC
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(ii)R-2R ladder DAC

(iii) inverted R-2R ladder DAC (Dec - 2011)(May 2015)
8. (i)Draw the circuit of a flash type ADC and explain.(8)
(ii) What is the purchase of high speed sample and hold circuit? Sketch such a
circuit and explain. Also name the parameters associated with it.(8) (Dec -
2011)
9. (i) Explain the following types of electronic switches used in D/A converter, with
suitable diagrams:
(1) Totem pole MOSFET switch (4)
(2) CMOS inverter as a switch. . (4)
(ii) Explain the working of R-2R ladder DAC, by taking example of a 3-bit DAC
circuit. Sketch the corresponding equivalent circuits and hence obtain the
equation for output. (8)( May - 2012)

10. (i) With neat circuit diagram and wave form of output, explain the working of Dual
slope A/D converter. (10)
(ii) Give a table of comparison of Flash, Dual-slope and Successive
approximation ADCs, in terms of parameters like speed, accuracy, resolution,
and input-hold-time.(6)( May – 2012)
11. (i)Explain the working principle of successive approximation type ADC.
(ii) Explain the any four specifications of data converters.( Dec - 2012)
12. (i).Compare single slope ADC and dual slope ADC.(3)
(ii).Draw the circuit and explain the working of dual slope A/D converter.(8)
(iii) For a particular dual slope ADC t1 is 83.33 ms and the reference voltage is
100mv.calculate t2 if: (5)
1)v1 is 100mv
2) 200mv(May - 2013)
13. Draw the block diagram and explain the working of:
1. Charge balancing VFCS
2.voltage to time converter. (May - 2013)
14. Explain the working of
1) R-2R ladder DAC(8)
2) dual slope A/D converter(8)( Dec - 2013)(May15)
15. Explain the working of
1) weighted resistor D/A converter.(8)
2) Successive approximation A/D converter.(8)( Dec - 2013)(May 15)
16. Explain weighted resistor type and R-2R Ladder type DAC. (16)( May – 2014,15)
17. Explain Flash type, Single type and Dual slope type ADC. (16) ( May - 2014)

191ROS402T LINEAR INTEGRATED CIRCUITS UNIT IV