Hindusthan College of Engineering And Technology

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COURSE CODE & COURSE NAME :: 22MT4201&Processor and Controller
SEMESTER -FOURTH
QUESTION BANK (With Answer Reference)
UNIT – III :: ARM PROCESSOR
Unit # 3::ARM Processor Fundamentals – ARM Architecture – ARM Assembly Language
Programming- ARM Organization and Implementation – ARM Instruction Set

E-Book #
T2-Steve Furber, ARM System- on-Chip Architecture, 2ndEdition, Pearson Publishers.

PART A (2 Mark)
[Book T1/T2/R1]
Mark (Page No. P.)
S.No Questions BTL
s {Figure / Table No
F/ T # }
Abbreviate ‘RISC’. What does ‘ARM’ stands for? R 2 [T2]
1.
(P.35 & 36)
2. List any four principal features of the ARM architecture. R 2 [T2]
(P.47)
3. List few rules that are applicable to ARM data processing R 2 [T2]
instructions. (P.50)
4. List the three basic forms of data transfer instruction in the ARM R 2 [T2]
instruction set. (P.55 & 56)
5. Tell about the stages of 3-stage & 5-stage pipeline in ARM R 2 [T2]
organization. (P.75) (P.79 & 80)
6. Name the six data types supported by ARM processor R 2 [T2]
(P.106)
7. Show and tell about the Little-endian memory organization & R 2 [T2]
Big-endian memory organization (P.106 & 107)
(F#5.1}
8. Tabulate the ARM operating modes and register usage. R 2 [T2]
(P.107 & 108)
(T#5.1}
PART B (14 Mark)
S.No Questions BTL Marks [Book T1/T2]
(Page No. P.)
{Figure / Table No
F/ T #}
 Elaborate on the following ARM programmer’s model with
9. necessary figures. U 14
[T2]
i. ARM’s visible Register
(P-39 to 43 )
ii. ARM CPSR
{F#2.1, 2.2 &2.3}
iii. ARM memory Organization.
iv. Load-Store Architecture &The ARM instruction set
v. The I/O System & ARM exceptions
Explain on ARM development tools. Draw the structure of ARM [T2]
10. cross-development toolkit and provide the necessary outline. U 14 (P- 43 to 47 )
{F# 2.4 }
Illustrate the data processing instructions of ARM processor in [T2]
11. context to the following terms U 14 (P- 50 to55 )
i. Simple register operands {F# 3.1 }
ii. Immediate Operands
iii. Shifted register operands
iv. Setting and Use of Condition codes.
v. Multiplies.
12. Illustrate the data transfer instructions of ARM processor in [T2]
context to the following terms U 14 (P-55 to 63)
i. Register-indirect addressing and initializing an address {F# 3.2 }
pointer {Table # 3.1}
ii. Single register load and store instructions.
iii. Base plus offset addressing & Stack addressing
iv. Multiple register data transfers & Block copy addressing.
13. i. Explain the 3-stage pipeline ARM organization with neat [T2]
sketch. U 14 (P- 75 to 78 )
ii. Enumerate ARM single-cycle instruction 3-stage pipeline {F#4.1, 4.2 & 4.3 }
operation with neat figure
iii. Enumerate ARM multi-cycle instruction 3-stage pipeline
operation with neat figure
14. Explain the 5-stage pipeline ARM organization with neat sketch. [T2]
U 14 (P-78 to 82 )
{F#4.4 }
15. Explain the following types of ARM instruction execution with its [T2]
corresponding data path activity. U 14 (P- 82 to 85)
i. Data processing instructions {F#4.5, 4.6 & 4.7}
ii. Data transfer instructions
iii. Branch instructions.
16. Explain the following in context to ARM instruction set [T2]
i. Exceptions. U 14 (P-108 to 115 )
ii. Condition Execution {F#5.2 & 5.3 }
iii. Branch and Branch with Link {Table #5.2, 5.3 }
PART C (10 Mark)
17. Illustrate the control flow instructions of ARM processor in [T2]
context to the following terms (P- 63 to 68)
i. Branch instructions, Conditional branches & execution Ap 10 {Table #3.2 }
ii. Branch and link instruction & Subroutine return
instructions.
 iii. Supervisor calls and Jump Tables

18. Explain the following with reference to ARM instruction set [T2]
i. Software Interrupts (P-117 to 124)
ii. Data processing instructions Ap 10 {F# 5.5, 5.6 & 5.7 }
iii. Multiply instructions {Table #5.4 & 5.5 }

Faculty in Charge HoD

Dr.Madhusudhanan.R Dr.P.T.Saravanakumar