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Troubleshooting .......................................................................................................... 45
Introduction ................................................................................................................................................... 45
Cross References for Settings, Equations, and Variables .............................................................................. 45
Single-Phase Tripping and Closing Overview .............................................................................................. 63
Control Wiring Overview ..................................................................................................................... 63
Trip and Close Logic Overview............................................................................................................ 63
Available Variation in Single-Phase Tripping and Reclosing .............................................................. 65
Logic Schemes and Diagrams ....................................................................................................................... 66
Cold Load Pickup Scheme .................................................................................................................... 66
Loss-of-Load Diversity Logic ...................................................................................................... 66
Seal-In Logic ................................................................................................................................ 67
Normal Trip Restoration Logic .................................................................................................... 67
Logic for Desensitizing the Minimum Trip Settings .................................................................... 70
Time-Overcurrent (Fast and Delay Curve) Elements ........................................................................... 70
Time-Overcurrent Torque Control Logic ..................................................................................... 70
Figures
Figure 1 27-Pin Recloser Overview (Joslyn TriMod 600R) ................................................................................... 7
Figure 2 SEL-651R Front-Panel Operator Interface ............................................................................................... 9
Figure 3 ACSELERATOR QuickSet HMI With Communications Established to SEL-651R ................................. 43
Figure 4 ACSELERATOR QuickSet HMI Trip and Close Operators for the SEL-651R ........................................ 43
Figure 5 Trip Logic Overview .............................................................................................................................. 63
Figure 6 Close/Reclose Logic Overview .............................................................................................................. 64
Figure 7 Select Trip/Reclose/Lockout Operation Mode ....................................................................................... 65
Figure 8 A-Phase Loss-of-Load Diversity Logic (Similar Logic is Used for B- and C-Phases) .......................... 67
Figure 9 Cold Load Pickup Scheme Seal-In Logic for A-Phase Overcurrent Element (Similar Logic is
Used for B- and C-Phases) ..................................................................................................................... 68
Figure 10 Cold Load Pickup Scheme Seal-In Logic for Ground Overcurrent Elements ........................................ 69
Figure 11 A-Phase Forced Minimum Trip Restoration Logic (Similar Logic is Used for B- and C-
Phases) ................................................................................................................................................... 69
Figure 12 Ground Forced Minimum Trip Restoration Logic ................................................................................. 69
Figure 13 Phase Time-Overcurrent Torque Control ............................................................................................... 71
Figure 14 A-Phase Time-Overcurrent Torque Control (Similar Logic is Used for B- and C-Phases) ................... 71
Figure 15 Ground Time-Overcurrent Torque Control ............................................................................................ 72
Figure 16 Maximum Phase Time-Overcurrent Element Switch Logic .................................................................. 73
Figure 17 A-Phase Time-Overcurrent Element Switch Logic (Similar Logic is Used for B- and C-
Phases) ................................................................................................................................................... 73
Figure 18 Ground Time-Overcurrent Element Switch Logic ................................................................................. 74
Figure 19 Phase High-Current Trip Element Torque Control Logic ...................................................................... 75
Figure 20 A-Phase High-Current Trip Element Torque Control Logic (Similar Logic is Used for B- and
C-Phases) ............................................................................................................................................... 75
Figure 21 Ground High-Current Trip Element Torque Control Logic ................................................................... 76
Figure 22 Phase High-Current Lockout Element Torque Control Logic................................................................ 77
Figure 23 A-Phase High-Current Lockout Element Torque Control Logic (Similar Logic is Used for B-
and C-Phases) ......................................................................................................................................... 77
Figure 24 Ground High-Current Lockout Element Torque Control Logic ............................................................. 77
Figure 25 A-Phase Trip Conditions (Similar Logic is Used for B- and C-Phases) ................................................ 78
Figure 26 A-Phase Close Conditions (Other Than Autoreclosing) ........................................................................ 80
Figure 27 A-Phase Unlatch Close Conditions (Similar Logic is Used for B- and C-Phases) ................................. 81
Figure 28 A-Phase Drive-to-Lockout Conditions (Similar Logic is Used for B- and C-Phases) ........................... 83
Figure 29 Three-Phase Close Logic ....................................................................................................................... 83
Figure 30 Three-Phase Unlatch Close Logic .......................................................................................................... 84
Figure 31 Three-Phase Trip Logic.......................................................................................................................... 85
Figure 32 “Extra” Three-Phase Trip Logic (TR3X) ............................................................................................... 86
Figure 33 Three-Phase Drive-to-Lockout Logic .................................................................................................... 86
Figure 34 “Extra” Three-Phase Drive-to-Lockout Logic (79DTL3X) ................................................................... 87
Figure 35 Phase and Ground Time-Overcurrent Element Sensitivity Comparison ................................................ 88
Figure 36 Three-Phase Tripping for Ground Overcurrent Element Operation ....................................................... 89
Figure 37 Phase Discordance Logic ....................................................................................................................... 91
Figure 38 Single-Phase Trip Failure Logic............................................................................................................. 92
Figure 39 Logic for Tripping All Phases Following a Single-Phase Serial Port Trip Command ........................... 93
Figure 40 Final Trip Coincides With Transition to Lockout .................................................................................. 94
Figure 41 Forcing Three-Phase Trip and Three-Phase Lockout for Final Trip in Autoreclose Cycle .................... 95
Preface
The SEL-651R Advanced Recloser Control, when ordered with the 27-pin option, can be used with the
Joslyn TriMod™ 600R 27-pin recloser for single-phase tripping and reclosing applications (see Figure 1).
Global: System
Table 4 System Frequency Setting
Setting Range Default Units Increment
System Frequency 50, 60 60 Hz
Enter nominal system frequency.
Remote Bits
The operator control logic settings in this design template include remote bits that can be used to remotely
control some operator functions through a serial communications channel using Distributed Network
Protocol (DNP3) or Modbus® protocol. The remote bits used in the default logic are shown in Table 100.
Figure 4 ACSELERATOR QuickSet HMI Trip and Close Operators for the SEL-651R
Introduction
This section contains the following information:
• Cross reference between design settings and relay settings
• Cross reference between design equations and relay settings
• Cross reference between design variables and design settings
• Single-phase tripping and reclosing overview
• Relay logic schemes and diagrams
• Listing of all relay settings
SELOGIC
Settings
Three-Phase
Trip Input Logic 3-Phase Trips
TR3P ESPB:=Y
(Always Enabled)
Extra ESPB:=N
TR3X
3-Phase Trips
Relay
Three-Phase Word
Trip Output Logic Bits
(Group Setting
TRIP3P
ESPB:=N)
SELOGIC
Settings
A-Phase Trips TRIPA
Single-Phase TRA
Trip Logic
(Group Setting B-Phase Trips TRIPB
TRB
ESPB:=Y)
Three-Phase Trip
Single-Phase Trip Three-Phase Reclose
Single-Phase Reclose Three-Phase Lockout
Global setting BKTYP at the top of Figure 7 is always set BKTYP := 1 for the Joslyn TriMod 600R
recloser.
Relay Word
Bits and Analog
Comparisons
Three-Phase Lockout
79LO3P
A-Phase Lockout
79LOA
Reclose Disabled
SV02 SELOGIC
Setting Relay
A-Phase Open Word
SV05 Bit
SPOA SV05
PU
SV05T
(A-phase
0 loss-of-load
Phase Cold Load Scheme Enabled Loss-of-Load diversity)
MV10 <> 0 Diversity Time
Ground Cold Load Scheme Enabled
MV11 <> 0
Figure 8 A-Phase Loss-of-Load Diversity Logic (Similar Logic is Used for B- and C-Phases)
Seal-In Logic
As shown in Figure 9 and Figure 10, the single-phase loss-of-diversity logic is used to activate the cold
load pickup scheme for the phase and ground elements. Latch bits LT10, LT11, and LT12 indicate when
the single-phase cold load pickup scheme is active. Latch bit LT13 indicates when the ground element cold
load pickup scheme is active.
Natural Return
The natural return method uses the logic in the bottom of Figure 9 and Figure 10. A timer is used to time
the condition where the recloser is closed and measured current for the associated element (phase or
ground) is below the minimum trip setting. The default timer pickup delay is 900 cycles (15 seconds).
SELOGIC control equations timers SV08, SV09, SV10, and SV11 are used for the A-phase, B-phase, C-
phase, and ground cold load logic, respectively.
Relay Word
Bits and Analog
Comparisons
A-Phase Loss-of-Diversity SELOGIC
SV05T Settings Relay
Latch Bit 10
SET10 Word
Phase Cold Load Bit
Scheme Enabled S
MV10 <> 0.00 Q LT10
A-Phase Minimum Trip RST10 (A-phase
R
cold load
Forced Restoration scheme
SV31T
Phase Cold Load active)
Scheme Disabled
MV10 = 0.00
Natural
SELOGIC Restoration
Above Minimum Trip–Phase Time Limit
50P6 Setting
SV08 SV08
A-Phase Closed PU
52AA
0
Figure 9 Cold Load Pickup Scheme Seal-In Logic for A-Phase Overcurrent Element
(Similar Logic is Used for B- and C-Phases)
Natural
SELOGIC Restoration
Above Minimum Trip–
Setting Time Limit
50G6 Ground
SV11 SV11
All Phases Closed PU
SV03
0
Figure 10 Cold Load Pickup Scheme Seal-In Logic for Ground Overcurrent Elements
Relay Word
Bits and Analog Restore
Comparisons Minimum Trips
SELOGIC
A-Phase Cold Load Scheme Active Time Limit Relay
LT10 Setting
Word
SV31 SV31 Bit
Phase Forced Restoration Enabled PU
MV12 <> 0.00 SV31T
0 (restore A-phase
A-Phase Closed minimum trip)
52AA
Figure 11 A-Phase Forced Minimum Trip Restoration Logic (Similar Logic is Used for B- and C-Phases)
Relay
Word
Bits
Single-Phase Operation Enabled
SPE SELOGIC
Setting
A-Phase Cold Load Active 51ATC
LT10 (A-phase time-
overcurrent torque
A-Phase Current Above control)
Phase Cold Load Pickup
50A3
Figure 14 A-Phase Time-Overcurrent Torque Control (Similar Logic is Used for B- and C-Phases)
The constants that these shot counters are compared against are contained in two math variables—MV01
and MV02. These two math variables are calculated by the design template using design settings
Operations–Phase Fast Curve and Operations–Ground Fast Curve, respectively. Refer to Table 104 in the
earlier section Cross References for Settings, Equations, and Variables for details on how MV01 and
MV02 are calculated.
The switch logic also selects the delay curve whenever the cold load pickup scheme for the associated
element is active or when fast curve tripping has been disabled through the FAST CURVE ENABLED operator
control pushbutton or by remote control. The logic for the curve switches is shown in Figure 16, Figure 17,
and Figure 18.
Relay Word
Bits and Analog
Comparisons
A-Phase Cold Load Scheme Active
LT10
Figure 17 A-Phase Time-Overcurrent Element Switch Logic (Similar Logic is Used for B- and C-Phases)
Relay Word
Bits and Analog
Comparisons
Activate Three-Phase HCT for
Remaining Trips
MV06 <= 79SH3P
Reclosing Disabled
SV02 SELOGIC
Setting
Single-Phase Operation Enabled 50P2TC
SPE
(three-phase
high-current
Phase HCT Enabled (setting) trip element
MV06 >= 0.00 torque control)
Relay Word
Bits and Analog
Comparisons Activate A-Phase HCT for
Remaining Trips
MV06 <= 79SHA
Reclosing Disabled
SV02 SELOGIC
Setting
Single-Phase Operation Enabled 50A2TC
SPE (A-phase
high-current
Phase HCT Enabled (setting) trip element
MV06 >= 0.00 torque
control)
Reclosing Disabled
SV02
Analog
Comparisons
Activate A-Phase HCLO for Remaining Trips SELOGIC
MV08 <= 79SHA Setting
50A1TC
Phase HCLO Enabled (setting) (A-phase high-
MV08 >= 0.00 current lockout
element
torque control)
Relay Word
Bits and Analog Activate Ground HCLO for
Comparisons
Remaining Three-Phase Trips
MV09 <= 79SH3P
Single-Phase Tripping
Single-phase tripping is accomplished through SELOGIC control equations TRA, TRB, and TRC. These
equations are active only if design setting Enable Single Phase Operation is equal to Y (and thus relay
group setting ESPB := Y). Note from the equations shown in Table 108 that the trip logic for each phase
differs only in phase designation. Therefore, only the A-phase trip logic is discussed in detail.
As shown in the A-phase trip logic diagram in Figure 25, 51AT and 50A2T trip directly when either times
out. If neither 51AT nor 50A2T has timed out, the rest of the trip logic can accelerate tripping for A-phase
if 51AT is timing toward tripping (pickup indication 51A = logical 1) AND:
• 51G1T times out
• OR B-phase is tripping (TRIPB)
• OR C-phase is tripping (TRIPC)
• OR 50G2T times out and the A-phase reclosing relay shot counter (79SHA) is at the “high-current
trip–ground” activation shot level (MV07)
A-phase also trips if the A-phase serial port open command is received (remote bit OCA, supervised by the
front-panel remote enabled function via latch bit output LT03).
Relay Word
Bits and Analog
Comparisons
A-Phase Time-Overcurrent Trip
51AT
SELOGIC
Setting
A-Phase High-Current Trip
50A2T TRA
(A-phase trip)
A-Phase Above Minimum Trip
51A
Ground Time-Overcurrent Trip
51G1T
B-Phase Trip
TRIPB
C-Phase Trip
TRIPC
Figure 25 A-Phase Trip Conditions (Similar Logic is Used for B- and C-Phases)
The outputs from TRA, TRB, and TRC are routed to Relay Word bit trip outputs TRIPA, TRIPB, and
TRIPC, respectively. For additional details, refer to Section 5: Trip and Target Logic in the SEL-651R
Instruction Manual.
Refer to the A-phase close logic diagram in Figure 26. The entire close logic is supervised by:
• Latch bit output LT06 (front-panel hot-line tag function)
• AND SELOGIC control equation variable output SV38 (healthy trip/close capacitor voltage; see
the Test/Simulator Modes subsection for more information)
If HOT LINE TAG is off/disabled (LT06 = logical 1) and trip/close capacitor voltage is healthy (SV38 = logical
1), closing can take place if:
• The front-panel CLOSE operator control pushbutton is pressed and the programmed close time delay
(if any) has expired (SELOGIC control equation timer output SV13T, supervised by the front-panel
pushbuttons locked function via latch bit output LT05). See the Operator Control Logic
subsection for additional details on SV13
• OR the A-phase or three-phase serial port close command is received (CCA or CC3 respectively,
supervised by the front-panel remote enabled function via latch bit output LT03)
Relay Word
Bits and Analog
Comparisons
A-Phase Trip Logic Output
TRIPA
Pushbuttons Unlocked
LT05
A-Phase Close Logic
CLOSEA
Remote Enabled
LT03
Figure 27 A-Phase Unlatch Close Conditions (Similar Logic is Used for B- and C-Phases)
For additional details on the close logic, see Section 6: Close & Reclose Logic in the SEL-651R Instruction
Manual.
As detailed in Figure 28, the A-phase reclosing relay is driven directly to lockout, regardless of whether it
is in the midst of autoreclosing or not, if any of the following conditions become true:
• The A-phase serial port open command is received (remote bit OCA, supervised by the front-panel
remote enabled function via latch bit output LT03)
• OR front-panel reclose enabled function is off/disabled (LT02 = logical 0) or front-panel hot-line
tag function is on/enabled (LT06 = logical 0) and A-phase is open (SPOA) or tripping (TRIPA)
• OR A-phase is tripping (TRIPA) and 50A1T or 50G1T times out (high-current lockout threshold
exceeded) or the A-phase reclosing relay shot counter (79SHA) is at the “operations to lockout–
phase” activation shot level defined by math variable MV03 (effectively at “last shot”).
Remote Enabled
LT03
Reclose Enabled
LT02
A-Phase Trip
TRIPA
Figure 28 A-Phase Drive-to-Lockout Conditions (Similar Logic is Used for B- and C-Phases)
Three-Phase Closing/Reclosing
If design setting Enable Single Phase Operation is equal to N (relay group setting ESPB := N), then the
single-phase close/reclose logic previously discussed is inoperative and three-phase closing/reclosing is
enabled. As shown in Figure 29 and Figure 30, the three-phase manual close conditions and unlatch close
conditions are set very similar to their single-phase counterparts. Because of the similarity in logic, the
detailed discussion of the single-phase manual close and unlatch close logic provided in the preceding
subsection Single-Phase Manual Closing should be sufficient for understanding the three-phase logic.
Relay Word
Bits and Analog
Comparisons
SV13T Close Pushbutton (with time delay)
Pushbuttons Unlocked
LT05
Three-Phase Close Logic
CLOSE3P
Remote Enabled
LT03
Relay
Word
Bits
Phase Time-Overcurrent Trip
51PT
Phase High-Current Trip
50P2T
Ground Time-Overcurrent Trip
51G1T
Ground High-Current Trip
50G2T SELOGIC
Setting
Single-Phase Operation Enabled TR3P
SPE (three-
phase trip)
Faulted Phase Known
SV26T
Underfrequency
81D1T
Phase Discordance
SV04T
Relay
Word
Bits
Phase High-Current Lockout
50P1T
Ground High-Current Lockout
50G1T
Three-Phase Trip
TRIP3P
Reclose Enabled
LT02
No Hot-Line Tag SELOGIC
LT06 Setting
79DTL3P
(three-phase
lockout
Three Poles Open conditions)
3PO
Underfrequency
81D1T
Phase Discordance
SV04T
51PT OR 50P2T
51PT = Maximum phase time-overcurrent element timed out (fast or delay curve)
50P2T = Maximum phase definite-time overcurrent element timed out (phase high-current trip)
51PT and 50P2T (operating on maximum phase current) are automatically set the same as the
corresponding single-phase overcurrent elements (e.g., 51AT and 50A2T for A-phase) for pickup, curve,
and time dial/time delay. 51PT and 50P2T are enabled when single-phase operation is disabled (group
setting ESPB := N; Relay Word bit SPE = logical 0).
Conversely, 51PT and 50P2T are disabled when single-phase operation is enabled (group setting ESPB :=
Y; Relay Word bit SPE = logical 1). Single-phase overcurrent elements (e.g., 51AT and 50A2T for A-
phase) are enabled instead.
This enabling/disabling is done automatically via torque control settings discussed in the earlier subsections
Time-Overcurrent (Fast and Delay Curve) Elements and High-Current Trip and High-Current Lockout
Logic.
Phase Current
Above Minimum Trip SELOGIC
Setting and
Relay Word Bit
Three-Phase Trip and Drive-to-Lockout Logic (in both settings TR3P and 79DTL3P)
SV14T
Trip initiated from front-panel TRIP operator control pushbutton. This bit asserts when the TRIP operator
control pushbutton (PB12) is pressed. If a trip time delay has been set using design setting Trip Pushbutton
Delay, then the SV14T bit asserts following the specified delay. See subsection Operator Control Logic for
more details.
81D1T
This logic subset determines underfrequency trip. In the underfrequency settings in the design template, the
following settings are made:
• Underfrequency Pickup (Hz)
• Underfrequency Time Delay (cycles)
• Underfrequency Voltage Supervision Pickup (V secondary)
The design equations translate these settings into the following respective settings for underfrequency
element 81D1T:
81D1P, 81D1D, 27B81P
Three-Phase Trip and Drive-to-Lockout Logic (in both settings TR3X and 79DTL3X)
R_TRIG SV22T
This logic subset determines whether a yellow operating handle operation has occurred. The pulling of the
handle trips all three phases.
Control input IN204 is connected to indicating contacts from the yellow operating handle. If the yellow
operating handle is operated, input IN204 is de-energized. Input IN204 is used in SELOGIC control
equations to create three-phase drive-to-lockout logic.
R_TRIG SV04T
This logic subset determines whether or not all three phases should eventually trip and be driven to lockout
if one or two phases are already open (deemed a phase discordance or single-pole open [SPO] condition).
The logic in Figure 38 is set as follows:
SV04 := SPO AND MV14 = 1.00 AND (NOT SPE OR (79LOA OR 79LOB OR 79LOC)
AND MV18 <> 1.00 AND MV18 <> 2.00)
SV04PU := 300 cycles qualification time (5 seconds)
SV04DO := 0 cycles
The SV04 output, SV04T, asserts after the 5-second delay if:
• One or two phases are open (SPO)
• AND design setting Enable Phase Discordance Detection is equal to Y (MV14 = 1.00). See
Table 81 in the earlier Design Settings Description and Settings Sheets section for more
information.
• AND either the SEL-651R is set for three-phase operation (group setting ESPB := N; NOT SPE =
NOT (logical 0) = logical 1) or one or more phases are in the lockout state (79LOA, 79LOB, or
79LOC) and the SEL-651R is set for always forcing all three phases to trip/lockout at the final trip
of a reclose cycle (enabled by expression “MV18 <> 1.00 AND MV18 <> 2.00”). MV18 defines
the lockout mode for single-phase operation and is set using design setting Lockout Mode (see
Table 106 in the Single-Phase Tripping and Closing Overview section).
Relay Word
Bits and Analog
Comparisons
One or Two Phases Open
SPO
SELOGIC
Phase Discordance Detection Enabled Setting and
MV14 = 1.00 Relay Word bit
Relay
Word
Single-Phase Mode Enabled Bit
SPE SV04 300
SV04T
Three-Phase Lockout Mode 0 (phase
MV18 <> 1.00 discordance)
R_TRIG SV40T
This logic subset determines that all three phases should trip and drive to lockout if there is a trip failure of
any single phase. The logic, as shown in Figure 38, is set as follows:
SV40 := (TRIPA AND 50LA OR TRIPB AND 50LB OR TRIPC AND 50LC) AND NOT (SV36
OR SV37)
SV40PU := 30 cycles qualification time
SV40DO := 0 cycles
Relay Word
Bits and Analog
Comparisons
A-Phase Trip
TRIPA
B-Phase Trip
TRIPB
SV23
This logic subset determines whether or not all three phases should trip and drive to lockout if a single-
phase serial port open command is received.
The logic, as shown in Figure 39, is set as follows:
SV23 := ((OCA OR OCB OR OCC) AND LT03) AND (MV18 <> 1.00 AND MV18 <> 2.00 OR
NOT SPE)
All three phases are tripped and driven to lockout if:
• The SEL-651R is set for always forcing all three phases to trip/lockout at the final trip of a reclose
cycle (enabled by expression “MV18 <> 1.00 AND MV18 <> 2.00”). MV18 defines the lockout
mode for single-phase operation and is set using design setting Lockout Mode (see Table 106 in
the Single-Phase Tripping and Closing Overview section).
• OR the SEL-651R is set for three-phase operation (group setting ESPB := N; NOT SPE = NOT
(logical 0) = logical 1).
• AND a single-phase serial port open command is received (serial port command OCA, OCB, or
OCC; supervised by the front-panel remote enabled function [latch bit output LT03]).
Relay Word
Bits and Analog
Comparisons
A-Phase Serial Trip
OCA
Figure 39 Logic for Tripping All Phases Following a Single-Phase Serial Port Trip Command
SV25
This logic subset determines whether or not all three phases should trip and drive to lockout if one phase
locks out. The SV25 logic is set as follows:
SV25 := SPE AND SV24T AND ((51A AND 51B OR 51B AND 51C OR 51C AND 51A) AND
MV18 = 2 OR MV18 <> 1 AND MV18 <> 2)
This logic is realized in Figure 41, but the preceding logic in Figure 40 must be understood first.
Figure 40 shows starting logic where at least one of the phases (A, B, or C) is transitioning to the lockout
state following a single-phase trip. SELOGIC control equation variable SV24 is used to detect the single-
phase “trip to lockout” condition and is set as follows:
SV24 := R_TRIG 79LOA AND TRIPA OR
R_TRIG 79LOB AND TRIPB OR
R_TRIG 79LOC AND TRIPC
SV24PU := 0 cycles
SV24DO := 0.5 cycles
Rising Edge
A-Phase in Lockout
79LOA
SELOGIC
Setting and
A-Phase Trip
TRIPA Relay Word Bit
Relay
B-Phase in Lockout Word
79LOB 0.0 Bit
SV24
SV24T
B-Phase Trip 0.5 (one or more
TRIPB
phases tripped
to lockout state)
C-Phase in Lockout
79LOC
C-Phase Trip
TRIPC
Relay Word
Bits and Analog
Comparisons
A-Phase Faulted
51A
B-Phase Faulted
51B
Multiphase
Fault
C-Phase Faulted
51C
Figure 41 Forcing Three-Phase Trip and Three-Phase Lockout for Final Trip in Autoreclose Cycle
SV17
This logic subset determines that all three phases are driven to lockout if an overcurrent trip occurs and:
• Neither phase nor ground operations remain in a reclose cycle
• OR the ground trip precedence logic deems all three phases should be driven to lockout
With the Ground Trip Precedence global setting in the design template, the following Y/N setting is made:
Ground Trip Precedence (Y/N)
A design equation translates this setting into math variable MV16:
MV16 := 1.00 (for “Y”) and MV16 := 0.00 (for “N”)
Thus, if MV16 := 1.00, then expression “MV16 <> 0.00” is true and ground trip precedence is enabled. The
last ground trip operation in a reclose cycle (with ground fault current above the ground minimum trip
pickup level at trip time) causes the SEL-651R to be driven to lockout.
The logic is realized as follows:
SV12 := (51PT OR 51G1T OR 50P2T OR 50G2T) AND TRIP3P
(maximum phase or ground overcurrent trip)
SV15 := MV03 <= 79SH3P (no phase operations remain)
SV16 := MV04 <= 79SH3P (no ground operations remain)
The Operations to Lockout–Phase and Operations to Lockout–Ground settings in the design template make
the effective settings for math variables MV03 and MV04, respectively:
MV03 := “Operations to Lockout–Phase” setting–1
MV04 := “Operations to Lockout–Ground” setting–1
SV17 := (SV15 AND SV16
OR SV16 AND 50G6 AND (MV16 <> 0.00 OR NOT 50P6)
OR SV15 AND 50P6 AND (MV16 = 0.00 OR NOT 50G6))
AND R_TRIG SV12
Sequence Coordination
Sequence coordination keeps the SEL-651R in step with a downstream recloser control to prevent
miscoordination when a fault occurs beyond the downstream recloser. Sequence coordination is enabled
with design setting Sequence Coordination. See Table 18 in the Design Settings Descriptions and Settings
Sheets section for more information on this setting.
Sequence coordination is accomplished by incrementing the appropriate reclose shot counter when the
SEL-651R detects a fault that is subsequently cleared by a downstream protective device. The single-phase
trip capable SEL-651R recloser control utilizes single-phase shot counters 79SHA, 79SHB, and 79SHC for
independent phase reclosing when single-phase operation is enabled (design setting Enable Single Phase
Operation = Y, relay group setting ESPB := Y). When three-phase operation is enabled (ESPB := N), three-
phase shot counter 79SH3P is used.
Conditions required for sequencing the shot counter are:
• Relay Word bit TRIP3P is a logical 0 (ESPB is equal to N) or single-phase trip bit TRIPA,
TRIPB, or TRIPC = logical 0 when ESPB = Y.
• AND recloser is closed.
• AND corresponding sequence coordination SELOGIC control equation is asserted for a minimum
of 1.25 cycles, then deasserted.
The SEL-651R has three single-phase sequence coordination SELOGIC control equations and a three-phase
sequence equation. These equations are set as follows:
79SEQ3P := 79RS3P AND MV15 <> 0.00 AND (51P AND NOT 51PS OR 51G1 AND NOT
51G1S)
79SEQA := 79RSA AND MV15 <> 0.00 AND (51A AND NOT 51AS OR 51G1 AND NOT 51G1S)
79SEQB := 79RSB AND MV15 <> 0.00 AND (51B AND NOT 51BS OR 51G1 AND NOT 51G1S)
79SEQC := 79RSC AND MV15 <> 0.00 AND (51C AND NOT 51CS OR 51G1 AND NOT 51G1S)
When three-phase operation is enabled (ESPB := N), the single-phase reclosing logic is disabled and logic
settings 79SEQA, 79SEQB, and 79SEQC are not used. In the same manner, the three-phase sequence
coordination equation 79SEQ3P is not used when single-phase operation is enabled (ESPB := Y).
SELOGIC
Phase Time-Overcurrent Pickup
51P Setting
79SEQ3P
Phase Slow Curve Enabled (three-phase
51PS sequence
coordination)
Ground Time-Overcurrent Pickup
51G1
Relay Word
Bits and Analog
Comparisons
A-Phase Reclosing in Reset State
79RSA
SELOGIC
A-Phase Time-Overcurrent Pickup
51A Setting
79SEQA
A-Phase Slow Curve Enabled (A-phase
51AS sequence
coordination)
Ground Time-Overcurrent Pickup
51G1
Figure 44 A-Phase Sequence Coordination Logic (Similar Logic Used for B- and C-Phases)
As shown in Figure 43, the following conditions must be true to assert the three-phase sequence
coordination equation (79SEQ3P):
• Three-phase reclosing logic is in the reset state (79RS3P is a logical 1)
• AND sequence coordination is enabled (MV15 <> 0.00). If design setting Enable Sequence
Coordination is equal to Y, the design template sets math variable MV15 setting to 1.00;
otherwise, MV15 is set to 0.00.
• AND any phase fault current detected (51P = 1) with the phase fast curve enabled (51PS = 0) OR
ground fault current detected (51G1 = 1) with ground fast curve enabled (51G1S = 0)
The single-phase sequence coordination equations, as shown above, differ only in phase designation. A
diagram of the 79SEQA logic is shown in Figure 44. The 79SEQB and 79SEQC logic are similar.
Reclose Supervision
After a reclose interval times out, a final check is made of the reclose supervision logic before the
SEL-651R can autoreclose the recloser. Autoreclosing can proceed only when the following conditions are
met:
• Trip and close capacitor voltage is healthy (sufficiently charged)
• Battery is healthy
If these conditions are met within the time period specified by design setting Close Power Wait Time, then
autoreclosing proceeds.
The single-phase trip-capable SEL-651R has a reclose supervision equation for each phase (79CLSA,
79CLSB, 79CLSC) and an equation for three-phase reclosing (79CLS3P). The single-phase equations are
used when single-phase operation is enabled (design setting Enable Single Phase Operation is equal to Y).
When configured for three-phase operation (design setting Enable Single Phase Operation is equal to N),
the SEL-651R uses only the three-phase equation. These four equations are all set using the same logic as
follows:
79CLSx := SV38 AND NOT SV39
where:
SV38 indicates healthy trip/close capacitor voltage (TCCAP) and NOT SV39 indicates healthy
battery
See the following Test/Simulator Modes subsection for more information on SV38 and SV39.
Relay
Word
Bits Pushbutton 01
Pressed
PB01_PUL SELOGIC
Pushbuttons Settings
Unlocked Latch Bit 01 Relay
LT05
SET01 Word
S Bit
Remote Bit 02
RB02 Q LT01
RST01 (1 = set
R 0 = reset)
Remote Enabled
LT03
Remote Bit 01
RB01
Pushbutton Locking
All operator control pushbuttons (except TRIP) can be locked using the PUSH BUTTONS LOCKED operator control
pushbutton (PB06). PB06 must be pressed for three seconds to enable the lock. Once locked, the
pushbutton LED remains illuminated. Figure 46 shows the logic associated with the lock pushbutton and
the 3-second delay function. The logic required to control the PUSH BUTTONS LOCKED LED (PB06_LED) is
shown in Figure 47. Note that the 1 Hz flash timer (SV01) is also driven by the SPO (single-pole open)
condition. This is so that the red and green phase status LEDs blink during a phase discordance condition
(see logic settings for PB11_LED and PB12_LED in the following Trip/Close Pushbuttons subsection).
Counter SC01
SC01CU Count
Up SC01QU
Q Up
SELOGIC Count
Settings Down
SC01R Q Down
Reset
Load Present
Value
Preset Value Preset
SC01PV := 3 Value
SELOGIC
Settings
Latch Bit 05
SET05 Relay
Word
S Bit
Q LT05
RST05
Rising Edge R (1 = unlocked
Detect 0 = locked)
Relay
Word
Bits
3-Second Count Complete
SC01QU
Pushbuttons Not Locked
LT05
Relay
Word
Bit
1 Hz Flash
SV01T PB06_LED
(pushbuttons
Lock Pushbutton Pressed locked LED)
PB06
Relay
Word
Bits Close Pushbutton
Pressed
PB11_PUL
SELOGIC
Setting and Relay
Word Bit
Relay
Word
SV13 SV13 Bit
PU
SV13T
Trip Pushbutton Pressed 0 (time-delayed
PB12_PUL operator close
Any Unlatch Close Bit command)
SV21
Trip Pushbutton Timing
SV14
Pushbuttons Unlocked
LT05
No Hot-Line Tag
LT06
Relay
Word
SV14 SV14 Bit
PU
SV14T
0 (time-delayed
Close Pushbutton Pressed operator trip
PB11_PUL
command)
Close Pushbutton Timing
SV13
SV01T
1 Hz Flash
SPO
SV01T
1 Hz Flash
Display point settings have been included in this design template so that the active operation mode is
displayed via the front-panel LCD. The following display point settings are required to accomplish this (see
also the Rotating Display subsection in Section 11: Front-Panel Operations in the SEL-651R Instruction
Manual):
• Three-Phase Trip/Three-Phase Lockout
• DP01 := SPE,,,“3-PH OPERATION”
DP02 := SPE,,,“MODE ENABLED”
• Note that the above messages are formatted so that the display occurs when SPE is a logical 0 (not
in single-phase mode, thus in three-phase mode)
• Single-Phase Trip/Single-Phase Lockout
• SV28 := SPE AND MV18 = 1.00
DP03 := SV28,,“1-PH LOCKOUT”
DP04 := SV28,,“MODE ENABLED”
• Single-Phase Trip/Single-Phase Lockout (three-phase lockout for multiphase fault)
• SV29 := SPE AND MV18 = 2.00
DP05 := SV29,,“1 AND 3 LOCKOUT”
DP06 := SV29,,“MODE ENABLED”
Test/Simulator Modes
If an SEL-651R is being tested, often it is not completely connected in a field installation. More than likely,
the control cable is disconnected so that the recloser is not connected to the SEL-651R. No current or
recloser status information is then available to the SEL-651R. To compensate for this, some test/simulator
modes can be easily enabled. These test/simulator modes are more attuned to in-house SEL needs, but are
embedded in the single-phase SELOGIC control equations settings that are the focus of this design template
guide and thus should be understood.
Figure 53 shows logic for the SEL-AMS (Adaptive Multichannel Source) test mode (SELOGIC control
equations variable setting/output SV36), and Figure 54 shows the recloser simulator mode logic (SELOGIC
control equations variable setting/output SV37).
SV36 := NOT SV37 AND (LB01 OR SV36) AND NOT (SV36T OR LB03)
SV36PU := 216000 cycles
SV36DO := 0 cycles
SV37 := (LB02 OR SV37) AND NOT (IN201 OR IN202 OR IN203 OR SV37T OR LB03)
SV37PU := 999999 cycles
SV37DO := 0 cycles
SELOGIC
Relay Setting and
Word Relay Word Bit
Bits
Simulator Mode Active
SV37
Relay
Word
Enable AMS Mode (pulse) Bit
LB01 SV36 SV36
PU SV36T
(AMS test
DO mode active)
Group 1
Group Settings
Enable Settings:
ESPB := N E50P := 6 E50N := N E50G := 6
E50Q := N E51P := 2 E51ABC := 2 E51G1 := 2
E51G2 := N E51Q := N ELOAD := N E32 := N
EVOLT := VY E81 := 1 EFLOC := N ELOP := N
EPWR := N E25 := N E79 := 4 ESOTF := N
EDEM := THM ESSI := Y EMV := 22
79DLS3P :=79LO3P
79SKP3P :=0
79STL3P :=TRIP3P
79BRS3P :=51P OR 51G1 # BLOCK 3-PHASE RECLOSE RESET TIMING
79SEQ3P :=79RS3P AND MV15 <> 0.00 AND (51P AND NOT 51PS OR 51G1 AND NOT 51G1S) # 3-PH RECLOSER
SEQUENCE CONTROL
79CLS3P :=SV38 AND NOT SV39 # TCCAP AND NOT BATT FAIL
Pole-Open Settings:
SPOD :=0.50 3POD :=0.50 50LP := 0.05
Group 1
Logic Settings
SET15 :=NA
RST15 :=NA
SET16 :=NA
RST16 :=NA
SET17 :=NA
RST17 :=NA
SET18 :=(CLOSEA OR CLOSE3P) AND SV37 # RECL SIMULATOR A-PHASE
RST18 :=TRIPA OR TRIP3P OR NOT SV37
SET19 :=(CLOSEB OR CLOSE3P) AND SV37 # RECL SIMULATOR B-PHASE
RST19 :=TRIPB OR TRIP3P OR NOT SV37
SET20 :=(CLOSEC OR CLOSE3P) AND SV37 # RECL SIMULATOR C-PHASE
RST20 :=TRIPC OR TRIP3P OR NOT SV37
SELogic Variable and Timer Settings:
SV01PU := 29.75 SV01DO := 29.75
SV01 :=NOT SV01T AND (PB06 OR SPO) # 1 HZ FLASHER FOR LOCK, TRIP, AND CLOSE PB LED
SV02PU := 5.00 SV02DO := 0.00
SV02 :=79SH3P = -1.00 AND 79SHA = -1.00 # RECLOSING DEFEATED
SV03PU := 0.00 SV03DO := 0.00
SV03 := 52AA AND 52AB AND 52AC #3 POLES CLOSED
SV04PU := 300.00 SV04DO := 0.00
SV04 :=SPO AND MV14 = 1.00 AND (NOT SPE OR (79LOA OR 79LOB OR 79LOC) AND MV18 <> 1.00 AND MV18
<> 2.00) # PHASE DISCORDANCE IN 1P TRIP - 3P LO MODE OR 3P TRIP MODE
SV05PU := 108000.00 SV05DO := 0.00
SV05 :=(79LOA OR 79LO3P OR SV02) AND SPOA AND (MV10 <> 0.00 OR MV11 <> 0.00) # A-PHASE LOSS OF
DIVERSITY
SV06PU := 108000.00 SV06DO := 0.00
SV06 :=(79LOB OR 79LO3P OR SV02) AND SPOB AND (MV10 <> 0.00 OR MV11 <> 0.00) # B-PHASE LOSS OF
DIVERSITY
SV07PU := 108000.00 SV07DO := 0.00
SV07 :=(79LOC OR 79LO3P OR SV02) AND SPOC AND (MV10 <> 0.00 OR MV11 <> 0.00) # C-PHASE LOSS OF
DIVERSITY
SV08PU := 900.00 SV08DO := 0.00
SV08 :=NOT 50P6 AND 52AA AND LT10 # A-PHASE COLD LOAD PU NATURAL RESTORATION
SV09PU := 900.00 SV09DO := 0.00
SV09 :=NOT 50P6 AND 52AB AND LT11 # B-PHASE COLD LOAD PU NATURAL RESTORATION
SV10PU := 900.00 SV10DO := 0.00
SV10 :=NOT 50P6 AND 52AC AND LT12 # C-PHASE COLD LOAD PU NATURAL RESTORATION
SV11PU := 900.00 SV11DO := 0.00
SV11 :=NOT 50G6 AND SV03 AND LT13 #GROUND COLD LOAD PU NATURAL RESTORATION
SV12PU := 0.00 SV12DO := 0.00
SV12 :=(51PT OR 51G1T OR 50P2T OR 50G2T) AND TRIP3P # ANY OVERCURRENT ELEMENT 3-POLE TRIP (DTL
LOGIC)
SV13PU := 0.00 SV13DO := 0.00
SV13 :=(PB11_PUL AND NOT SV13 OR NOT PB11_PUL AND SV13) AND NOT PB12_PUL AND NOT SV13T AND NOT
SV21 AND NOT SV14 AND LT05 AND LT06 # CLOSE PUSHBUTTON DELAY
SV14PU := 0.00 SV14DO := 0.00
SV14 :=(PB12_PUL AND NOT SV14 OR NOT PB12_PUL AND SV14) AND NOT PB11_PUL AND NOT SV14T AND NOT
SV13 # TRIP PUSHBUTTON DELAY
SV15PU := 0.00 SV15DO := 0.00
SV15 :=MV03 <= 79SH3P # NO PHASE RECLOSE SHOTS REMAINING IN 3-P TRIP MODE
SV16PU := 0.00 SV16DO := 0.00
SV16 :=MV04 <= 79SH3P # NO GROUND RECLOSE SHOTS REMAINING IN 3-P TRIP MODE
SV17PU := 0.00 SV17DO := 0.00
SV17 :=(SV15 AND SV16 OR SV16 AND 50G6 AND (MV16 <> 0.00 OR NOT 50P6) OR SV15 AND 50P6 AND
(MV16 = 0.00 OR NOT 50G6)) AND R_TRIG SV12 # NO 3-POLE RECLOSE SHOTS REMAINING
SV18PU := 0.00 SV18DO := 0.00
SV18 :=NA
SV19PU := 0.00 SV19DO := 0.00
SV19 :=NA
SV20PU := 0.00 SV20DO := 0.00
SV20 :=NA
SV21PU := 0.00 SV21DO := 0.00
SV21 :=CLOSE3P OR CLOSEA OR CLOSEB OR CLOSEC OR ULCL3P OR ULCLA OR ULCLB OR ULCLC # INTERMEDIATE
LOGIC FOR CLOSE DELAY TIMER
SV22PU := 5.00 SV22DO := 60.00
SV22 :=NOT IN204 # YELLOW HANDLE PULLED
TMB1B :=NA
TMB2B :=NA
TMB3B :=NA
TMB4B :=NA
TMB5B :=NA
TMB6B :=NA
TMB7B :=NA
TMB8B :=NA
General Settings:
EDP := 16 ELB := 3 FP_TO := 5 FP_CONT := 6
FPNGD := IG FPVYD := OFF FPVZD := OFF
LEDENAC := G LEDTRAC := R RSTLED := Y
T10LEDL := Y T10LEDC := R
T10_LED :=81D1T # FREQUENCY
T11LEDL := N T11LEDC := R
T11_LED :=LT07 # PHASE DISCORDANCE TRIP
T12LEDL := N T12LEDC := R
T12_LED :=LT08 # SINGLE-PHASE TRIP FAILURE
T13LEDL := N T13LEDC := G
T13_LED :=79RS3P OR 79RSA AND 79RSB AND 79RSC # 79 RESET
T14LEDL := N T14LEDC := R
T14_LED :=79CY3P OR 79CYA OR 79CYB OR 79CYC # 79 CYCLE
T15LEDL := N T15LEDC := R
T15_LED :=79LOA OR 79LO3P # A-PHASE LOCKOUT
T16LEDL := N T16LEDC := R
T16_LED :=79LOB OR 79LO3P # B-PHASE LOCKOUT
T17LEDL := N T17LEDC := R
T17_LED :=79LOC OR 79LO3P # C-PHASE LOCKOUT
T18LEDL := N T18LEDC := R
T18_LED :=51P OR 51G1 OR SV26 # ABOVE MIN TRIP
T19LEDL := N T19LEDC := R
T19_LED :=LT10 OR LT11 OR LT12 # PHASE COLD LOAD ACTIVATED
T20LEDL := N T20LEDC := R
T20_LED :=LT13 # GROUND COLD LOAD ACTIVE
T21LEDL := N T21LEDC := R
T21_LED :=NOT SPOA
T22LEDL := N T22LEDC := R
T22_LED :=NOT SPOB
T23LEDL := N T23LEDC := R
T23_LED :=NOT SPOC
T24LEDL := N T24LEDC := G
T24_LED :=SPE
Global Settings
General Settings:
NFREQ := 60 PHROT := ABC DATE_F := MDY
PWRDN_AC:= 180 PWRDN_WU:= 20
TESTBATT:=NA
FAULT :=51A OR 51B OR 51C OR 51P OR 51G1 AND (FSA OR FSB OR FSC) # FAULT CONDITIONS
Report Settings
Components
Design templates consist of the following components:
• Design settings that are entered using a custom settings interface
• A set of design equations that use the design settings and/or constants to derive the device settings
• A device settings file that contains a complete set of the derived device settings
While some device settings are calculated by the equations, others are not affected by the design template
(see Figure 55). Generally, these other settings do not require any modification from the default values that
were established when the design template was developed.
Derived Settings
Note: Any SEL-651R 27-pin single-phase operation design template obtained from SEL prior to
09/05/2012 was a preliminary release. Use the most recent settings file for the best results.