تقنيات رقمية Lectures

Digital Techniques Dr.
MOHAMMED KAMIL
Tikrit University
College Of Engineering
Electrical Engineering Dept.
Class: First Year - 2022
Logic circuits
‫ادلوائر املنطقية‬
Done by:
Dr. MOHAMMED KAMIL

Digital Techniques Dr. MOHAMMED KAMIL
List of Contents:
Lecture 1 .... Combinational Logic Analysis............................................................................................................
5–2 Implementing Combinational Logic
5–4 Combinational Logic Using NAND and NOR Gates
5–5 Pulse Waveform Operation
Lecture 2 .. Functions of Combinational Logic (Half and Full Adders, Comparators) ...................
6–1 Half and Full Adders
6–2 Parallel Binary Adders
6–4 Comparators
Lecture 3 .... Decoders, Encoders, and Multiplexers..............................
5 Decoders
The BCD-to-Decimal Decoder
The BCD-to-7-Segment Decoder
6–6 Encoders
6–7 Code Converters
6–8 Multiplexers (Data Selectors)
6–9 Demultiplexers
Lecture 4 .. Latches, D- Flip-Flops................................................
7–1 Latches
7–2 Flip-Flops
The D Flip-Flop
Lecture The J-K Flip-Flop ................................................................................................................................
The J-K Flip-Flop
Asynchronous Preset and Clear Inputs
7–4 Flip-Flop Applications
Lecture 6 . Counters...................................................................................................................................
Asynchronous Counters
A 2-Bit Asynchronous Binary Counter
A 3-Bit Asynchronous Binary Counter
Asynchronous Decade Counters
Partial Decoding
9–3 Synchronous Counters
9–5 Design of Synchronous Counters
Up/Down counter
Textbook: Digital Fundamentals, Thomas L. Floyd, Eleventh Edition, 2015
1
Lecture 1
Combinational Logic Analysis
5–2 Implementing Combinational Logic

• From a Boolean Expression to a Logic Circuit
Example 1: Let’s examine the following Boolean expression:
The first term is formed by ANDing A with B, and the second term is formed by ANDing C,
D, and E. The two terms are then ORed to form the output X. These operations are indicated
in the structure of the expression as follows:
Example 2:
2
• From a Truth Table to a Logic Circuit
Example 5–5 : Design a logic circuit to

implement the operation specified in the
truth table of Table 5–4.
Solution:
Notice that X =1 for only three of the

input conditions. Therefore, the logic
expression is
3
4
5–4 Combinational Logic Using NAND and NOR Gates
• NAND Logic
As you have learned, a NAND gate can function as either a NAND or a negative-OR because,
by DeMorgan’s theorem,
Example: Rewrite the following expression using only NAND gate 𝑋 = 𝐴𝐵 + 𝐶𝐷
Solution:
5
Example: Rewrite the following expression using only NAND gate 𝑋 = (𝐴𝐵 + 𝐶̅ )𝐷 + 𝐸𝐹
Solution:
• NOR Logic
A NOR gate can function as either a NOR or a negative-AND, as shown by DeMorgan’s
theorem.
6
Example: Rewrite the following expression using only NOR gate 𝑋 = (𝐴 + 𝐵 )(𝐶 + 𝐷)
Solution:
5–5 Pulse Waveform Operation

The following is a review of the operation of individual gates for use in analyzing combinational
circuits with pulse waveform inputs:
1. The output of an AND gate is HIGH only when all inputs are HIGH at the same time.
2. The output of an OR gate is HIGH only when at least one of its inputs is HIGH.
3. The output of a NAND gate is LOW only when all inputs are HIGH at the same time.
4. The output of a NOR gate is LOW only when at least one of its inputs is HIGH.
7
8
9
HOMEWORKS -1-
10
Lecture 2
Functions of Combinational Logic
6–1 Half and Full Adders
Half-Adder
Recall the basic rules for binary addition as stated in Chapter 2.
The operations are performed by a logic circuit called a half-adder.
The half-adder accepts two binary digits on its inputs and produces two
binary digits on its outputs—a sum bit and a carry bit.
A half-adder is represented by the logic symbol in Figure 6–1.
Half-Adder Logic
11
The Full-Adder
The full-adder accepts two input bits and an
input carry and generates a sum output and an
output carry.
12
Notice in Figure 6–4(b) there are two half-adders, connected as shown in the block diagram of
Figure 6–5(a), with their output carries ORed. The logic symbol shown in Figure 6–5(b) will
normally be used to represent the full-adder.
13
6–2 Parallel Binary Adders

A single full-adder is capable of adding two 1-bit numbers and an input carry. To add binary
numbers with more than one bit, you must use additional full-adders. When one binary number
is added to another, each column generates a sum bit and a 1 or 0 carry bit to the next column
to the left, as illustrated here with 2-bit numbers.
To add two binary numbers, a full-adder (FA) is required for each bit in the numbers. So, for
2-bit numbers, two adders are needed; for 4-bit numbers, four adders are used; and so on. The
carry output of each adder is connected to the carry input of the next higher-order adder, as
shown in Figure 6–7 for a 2-bit adder.
14
Four-Bit Parallel Adders
A group of four bits is called a nibble. A basic 4-bit parallel adder is implemented with four
full-adder stages as shown in Figure 6–9. Again, the LSBs (A1 and B1) in each number being
added go into the right-most full-adder; the higher-order bits are applied as shown to the
successively higher-order adders, with the MSBs (A4 and B4) in each number being applied to
the left-most full-adder. The carry output of each adder is connected to the carry input of the
next higher-order adder as indicated. These are called internal carries.
15
Adder Expansion
The 4-bit parallel adder can be expanded to handle the addition of two 8-bit numbers by using
two 4-bit adders. The carry input of the low-order adder (C0) is connected to ground because
there is no carry into the least significant bit position, and the carry output of the low-order
adder is connected to the carry input of the high-order adder, as shown in Figure 6–11.
16
An application
An example of full-adder and parallel adder application is a simple voting system that can be
used to simultaneously provide the number of “yes” votes and the number of “no” votes.
17
6–4 Comparators
The basic function of a comparator is to compare the magnitudes of two binary quantities to
determine the relationship of those quantities.
Equality
In order to compare binary numbers containing two bits each, an additional exclusive- NOR
gate is necessary. The two least significant bits (LSBs) of the two numbers are compared by
gate G1, and the two most significant bits (MSBs) are compared by gate G2, as shown in Figure
6–19.
18
Inequality
That is, there is an output that indicates when number A is

greater than number B (A > B) and an output that indicates
when number A is less than number B (A < B), as shown
in the logic symbol for a 4-bit comparator in Figure 6–21.
To determine an inequality of binary numbers A and B, you

first examine the highest order bit in each number. The
following conditions are possible:
1. If A3 = 1 and B3 = 0, number A is greater than number B.
2. If A3 = 0 and B3 = 1, number A is less than number B.
3. If A3 = B3, then you must examine the next lower bit position for an inequality.
19
Lecture 3
Functions of Combinational Logic
(Decoders, Encoders, and Multiplexers)
5 Decoders
A decoder is a digital circuit that detects the presence of a specified combination of bits (code)
on its inputs and indicates the presence of that code by a specified output level. In its general
form, a decoder has n input lines to handle n bits and from one to 2n output lines to indicate the
presence of one or more n-bit combinations.
The 4-Bit Decoder
In order to decode all possible combinations of four bits, sixteen

decoding gates are required (24 = 16). This type of decoder is
commonly called either a 4-line-to-16-line decoder because there
are four inputs and sixteen outputs or a 1-of-16 decoder because
for any given code on the inputs, one of the sixteen outputs is
activated. A list of the sixteen binary codes and their
corresponding decoding functions is given in Table 6–4.
FIGURE 6–28 Logic symbol for a 4-line-to-16-line

(1-of-16) decoder.
20
The BCD-to-Decimal Decoder

The BCD-to-decimal decoder converts each BCD code (8421 code)
into one of ten possible decimal digit indications. It is frequently
referred as a 4-line-to-10-line decoder or a 1-of-10 decoder. The
method of implementation is the same as for the 1-of-16 decoder
previously discussed, except that only ten decoding gates are
required because the BCD code represents only the ten decimal
digits 0 through 9. A list of the ten BCD codes and their
corresponding decoding functions is given in Table 6–5. Each of
these decoding functions is implemented with NAND gates to
FIGURE 6–31 BCD-to-decimal decoder
provide active-LOW outputs.
EXAMPLE 6–10
If the input waveforms in Figure 6–32(a) are applied to the inputs of the BCD-to-decimal
decoder, show the output waveforms.
21
The BCD-to-7-Segment Decoder

The BCD-to-7-segment decoder accepts the
BCD code on its inputs and provides outputs to
drive 7-segment display devices to produce a
decimal readout. The logic diagram for a basic 7-
segment decoder is shown in Figure 6–33.
FIGURE 6–33 Logic symbol for a BCD-to-7-

segment decoder/driver with active-LOW outputs.
EXAMPLE
A 7-segment decoder/driver drives the display in Figure below. If the waveforms are applied
as indicated, determine the sequence of digits that appears on the display.
6–6 Encoders
An encoder is a combinational logic circuit that essentially performs a “reverse” decoder

function. An encoder accepts an active level on one of its inputs representing a digit, such as a
decimal or octal digit, and converts it to a coded output, such as BCD or binary. Encoders can
also be devised to encode various symbols and alphabetic characters. The process of converting
from familiar symbols or numbers to a coded format is called encoding.
22
The Decimal-to-BCD Encoder
This type of encoder has ten inputs—one for

each decimal digit—and four outputs
corresponding to the BCD code, as shown in
Figure 6–36. This is a basic 10-line-to-4-line
encoder.
FIGURE 6–36 Logic symbol for a decimal-to-BCD encoder.
FIGURE 6–37 Basic logic diagram of a decimal-to-BCD encoder. A 0-digit input is

not needed because the BCD outputs are all LOW when there are no HIGH inputs
6–7 Code Converters
Binary-to-Gray and Gray-to-Binary Conversion
The basic process for Gray-binary conversions was covered in Chapter 2. Exclusive-OR gates
can be used for these conversions. Figure 6–40 shows a 4-bit binary-to-Gray code converter,
and Figure 6–41 illustrates a 4-bit Gray-to-binary converter.
23
24
6–8 Multiplexers (Data Selectors)

A multiplexer (MUX) is a device that allows digital
information from several sources to be routed onto a
single line for transmission over that line to a common
destination. The basic multiplexer has several data-input
lines and a single output line. It also has data-select inputs,
which permit digital data on any one of the inputs to be
switched to the output line. Multiplexers are also known
FIGURE 6–43 Logic symbol for a 1-of-4
as data selectors.
data selector/multiplexer.
25
Eight-Input Data Selector/Multiplexer
The eight data inputs (D0–D7) and, therefore, three

data-select or address input lines (S0–S2). Three bits
are required to select any one of the eight data inputs
(23 = 8).
EXAMPLE 6–15
Use an eight-Input Data Multiplexer and any other logic necessary to multiplex 16 data lines
onto a single data-output line.
Solution
26
Multiplexer Applications
• A Logic Function Generator
A useful application of the data selector/multiplexer is in the generation of combinational logic

functions in sum-of-products form. When used in this way, the device can replace discrete
gates, can often greatly reduce the number of ICs, and can make design changes much easier.
27
28
6–9 Demultiplexers
A demultiplexer (DEMUX) basically reverses the multiplexing function. It takes digital
information from one line and distributes it to a given number of output lines. For this reason,
the demultiplexer is also known as a data distributor.
Figure 6–52 shows a 1-line-to-4-line demultiplexer (DEMUX) circuit. The data-input line goes
to all of the AND gates. The two data-select lines enable only one gate at a time, and the data
appearing on the data-input line will pass through the selected gate to the associated data-output
line.
29
30
Homework
31
32
Lecture 4
Latches, D- Flip-Flops
7–1 Latches
The latch is a type of temporary storage device that has two stable states (bistable) and is
normally placed in a category separate from that of flip-flops. Latches are similar to flip-flops
because they are bistable devices that can reside in either of two states using a feedback
arrangement, in which the outputs are connected back to the opposite inputs. The main
difference between latches and flip-flops is in the method used for changing their state.
The S-R (SET-RESET) Latch
A latch is a type of bistable logic device or multivibrator. An active-HIGH input S-R (SET-
RESET) latch is formed with two cross-coupled NOR gates, as shown in Figure 7–1(a); an
active-LOW input 𝑆̅-𝑅̅ latch is formed with two cross-coupled NAND gates, as shown in Figure
7–1(b). Notice that the output of each gate is connected to an input of the opposite gate. This
produces the regenerative feedback that is characteristic of all latches and flip-flops.
33
34
The Gated S-R Latch

A gated latch requires an enable input, EN (G is also used to designate an enable input). The
logic diagram and logic symbol for a gated S-R latch are shown in Figure 7–8. The S and R
inputs control the state to which the latch will go when a HIGH level is applied to the EN input.
The latch will not change until EN is HIGH;
35
The Gated D Latch

Another type of gated latch is called the D latch. It differs from the S-R latch because it has
only one input in addition to EN. This input is called the D (data) input. Figure 7–10 contains
a logic diagram and logic symbol of a D latch. When the D input is HIGH and the EN input is
HIGH, the latch will set. When the D input is LOW and EN is HIGH, the latch will reset.
Stated another way, the output Q follows the input D when EN is HIGH.
36
7–2 Flip-Flops
Flip-flops are synchronous bistable devices, also known as bistable multivibrators. In this case,
the term synchronous means that the output changes state only at a specified point (leading or
trailing edge) on the triggering input called the clock (CLK), which is designated as a control
input, C; that is, changes in the output occur in synchronization with the clock. Flip-flops are
edge-triggered or edge-sensitive whereas gated latches are level-sensitive.
An edge-triggered flip-flop changes state either at the positive edge (rising edge) or at the
negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition
of the clock. Two types of edge-triggered flip-flops are covered in this section: D and J-K. The
logic symbols for these flip-flops are shown in Figure 7–13.
The D Flip-Flop
The D input of the D flip-flop is a synchronous input because data on the input are transferred
to the flip-flop’s output only on the triggering edge of the clock pulse. When D is HIGH, the Q
output goes HIGH on the triggering edge of the clock pulse, and the flip-flop is SET. When D
is LOW, the Q output goes LOW on the triggering edge of the clock pulse, and the flip-flop is
RESET.
37
38
39
Lecture 5
The J-K Flip-Flop
The J-K Flip-Flop
The J and K inputs of the J-K flip-flop are synchronous inputs because data on these inputs are
transferred to the flip-flop’s output only on the triggering edge of the clock pulse.
• When J is HIGH and K is LOW, the Q output goes HIGH on the triggering edge of
the clock pulse, and the flip-flop is SET.
• When J is LOW and K is HIGH, the Q output goes LOW on the triggering edge of the
clock pulse, and the flip-flop is RESET.
• When both J and K are LOW, the output does not change from its prior state.
• When J and K are both HIGH, the flip-flop changes state. This called the toggle mode.
40
Asynchronous Preset and Clear Inputs
Most integrated circuit flip-flops also have asynchronous inputs. These are inputs that affect
the state of the flip-flop independent of the clock. They are normally labeled preset (PRE) and
clear (CLR), or direct set (SD) and direct reset (RD) by some manufacturers. An active level
on the preset input will set the flip-flop, and an active level on the clear input will reset it. A
logic symbol for a D flip-flop with preset and clear inputs is shown in Figure 7–25. These inputs
are active-LOW, as indicated by the bubbles. These preset and clear inputs must both be kept
HIGH for synchronous operation. In normal operation, preset and clear would not be LOW
at the same time.
Figure 7–26 shows the logic diagram for an edge-triggered D flip-flop with active-LOW preset
(PRE) and clear (CLR) inputs. This figure illustrates basically how these inputs work. As you
can see, they are connected so that they override the effect of the synchronous input, D and the
clock.
41
EXAMPLE 7–7
For the positive edge-triggered D flip-flop with preset
and clear inputs in Figure 7–27, determine the Q output
for the inputs shown in the timing diagram in part (a) if
Q is initially LOW.
42
7–4 Flip-Flop Applications

Parallel Data Storage
A common requirement in digital systems is to store several bits of data from parallel lines
simultaneously in a group of flip-flops. This operation is illustrated in Figure 7–35(a) using four
flip-flops. Each of the four parallel data lines is connected to the D input of a flip-flop. The
clock inputs of the flip-flops are connected together, so that each flip-flop is triggered by the
same clock pulse.
43
Frequency Division
Another application of a flip-flop is dividing (reducing) the frequency of a periodic waveform.
When a pulse waveform is applied to the clock input of a D or J-K flip-flop that is connected
to toggle (D = 𝑄̅ or J = K = 1), the Q output is a square wave with one-half the frequency of the
clock input. Thus, a single flip-flop can be applied as a divide-by-2 device, as is illustrated in
Figure 7–36 for both a D and a J-K flip-flop.
Further division of a clock frequency can be achieved by using the output of one flipflop as the
clock input to a second flip-flop, as shown in Figure 7–37. The frequency of the QA output is
divided by 2 by flip-flop B. The QB output is, therefore, one-fourth the frequency of the
original clock input. Propagation delay times are not shown on the timing diagrams.
44
Homework
45
46
Lecture 6
Counters
Asynchronous Counters
The term asynchronous refers to events that do not have a fixed time relationship with each
other and, generally, do not occur at the same time. An asynchronous counter is one in which
the flip-flops (FF) within the counter do not change states at exactly the same time because
they do not have a common clock pulse.
• A 2-Bit Asynchronous Binary Counter
Figure 9–4 shows a 2-bit counter connected for asynchronous operation. Notice that the clock
(CLK) is applied to the clock input (C) of only the first flip-flop, FF0, which is always the least
significant bit (LSB). The second flip-flop, FF1, is triggered by the 𝑄̅0 output of FF0. FF0
changes state at the positive-going edge of each clock pulse, but FF1 changes only when
triggered by a positive-going transition of the 𝑄̅0 output of FF0. Because of the inherent
propagation delay time through a flip-flop, a transition of the input clock pulse (CLK) and a
transition of the 𝑄̅0 output of FF0 can never occur at exactly the same time. Therefore, the two
flip-flops are never simultaneously triggered, so the counter operation is asynchronous.
47
• A 3-Bit Asynchronous Binary Counter
The state sequence for a 3-bit binary counter is listed in Table 9–2, and a 3-bit asynchronous
binary counter is shown in Figure 9–6(a).
48
Asynchronous Decade Counters
The modulus of a counter is the number of unique states through which the counter will
sequence.
One common modulus for counters with truncated sequences is ten (called MOD10). Counters
with ten states in their sequence are called decade counters. A decade counter with a count
sequence of zero (0000) through nine (1001) is a BCD decade counter because its ten-state
sequence produces the BCD code.
To obtain a truncated sequence, it is necessary to force the counter to recycle before going
through all of its possible states. For example, the BCD decade counter must recycle back to
the 0000 state after the 1001 state. A decade counter requires four flip-flops (three flip-flops
are insufficient because 23 = 8).
Let’s use a 4-bit asynchronous counter such as the one in Example 9–1 and modify its sequence
to illustrate the principle of truncated counters. One way to make the counter recycle after the
count of nine (1001) is to decode count ten (1010) with a NAND gate and connect the output
of the NAND gate to the clear (CLR) inputs of the flip-flops, as shown in Figure 9–9(a).
Partial Decoding
Notice in Figure 9–9(a) that only Q1 and Q3 are connected to the NAND gate inputs. This
arrangement is an example of partial decoding, in which the two unique states (Q1 = 1 and Q3
= 1) are sufficient to decode the count of ten because none of the other states (zero through
49
nine) have both Q1 and Q3 HIGH at the same time. When the counter goes into count ten (1010),
the decoding gate output goes LOW and asynchronously resets all the flip-flops.
Q3 Q2 Q1 Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
9–3 Synchronous Counters
The term synchronous refers to events that have a fixed time relationship with each other. A
synchronous counter is one in which all the flip-flops in the counter are clocked at the same
time by a common clock pulse. J-K flip-flops are used to illustrate most synchronous counters
• A 2-Bit Synchronous Binary Counter
Figure 9–12 shows a 2-bit synchronous binary counter. Notice that an arrangement different
from that for the asynchronous counter must be used for the J1 and K1 inputs of FF1 in order to
achieve a binary sequence. A D flip-flop implementation is shown in part (b).
50
• A 3-Bit Synchronous Binary Counter
A 3-bit synchronous binary counter is shown in Figure 9–15, and its timing diagram is shown
in Figure 9–16. You can understand this counter operation by examining its sequence of states
as shown in Table 9–3.
51
9–5 Design of Synchronous Counters
Step 1: State Diagram
The first step in the design of a state machine (counter) is to

create a state diagram. A state diagram shows the
progression of states through which the counter advances
when it is clocked. As an example, Figure 9–26 is a state
diagram for a basic 3-bit Gray code counter. This particular
circuit has no inputs other than the clock and no outputs other
than the outputs taken off each flip-flop in the counter
FIGURE 9–26 State diagram

for a 3-bit Gray code counter.
52
Step 2: Next-State Table
the second step is to derive a next-state table, which

lists each state of the counter (present state) along
with the corresponding next state. The next state is
the state that the counter goes to from its present
state upon application of a clock pulse. The next-
state table is derived from the state diagram and is
shown in Table 9–8 for the 3-bit Gray code counter.
Q0 is the least significant bit.
Step 3: Flip-Flop Transition Table
Table 9–9 is a transition table for the J-K flip-flop. All

possible output transitions are listed by showing the
Q output of the flip-flop going from present states to
next states. QN is the present state of the flip-flop
(before a clock pulse) and QN + 1 is the next state (after
a clock pulse). For each output transition, the J and K
inputs that will cause the transition to occur are listed.
An X indicates a “don’t care” (the input can be either
a 1 or a 0).
Present state Next state

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 1 0 X 1 X X 0
3 0 1 1 0 1 0 0 X X 0 X 1
2 0 1 0 1 1 0 1 X X 0 0 X
6 1 1 0 1 1 1 X 0 X 0 1 X
7 1 1 1 1 0 1 X 0 X 1 X 0
5 1 0 1 1 0 0 X 0 0 X X 1
4 1 0 0 0 0 0 X 1 0 X 0 X
53
Step 4: Karnaugh Maps
Step 6: Counter Implementation
54
D-Flip-Flop
Solution
D-Flip-Flop Transition Table

Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
1 0 0 1 0 1 0 0 1 0
2 0 1 0 1 0 1 1 0 1
5 1 0 1 1 1 1 1 1 1
7 1 1 1 0 0 1 0 0 1
The D inputs are plotted on the present-state Karnaugh maps in Figure 9–31. Also “don’t cares”
can be placed in the cells corresponding to the invalid states of 000, 011, 100, and 110
(0, 3, 4, 6), as indicated by the red Xs.
55
T-Flip-Flop
Construct a synchronous 3-bit Up/Down counter by using T flip-flops
Transition table for a T flip-flop

Output Transitions Flip-Flop Input
QN QN+1 T
0 0 0
0 1 1
1 0 1
1 1 0
56

M Q2 Q1 Q0 Q2 Q1 Q0 T2 T1 T0
0 0 0 0 0 0 1 0 0 1
0 0 0 1 0 1 0 0 1 1
0 0 1 0 0 1 1 0 0 1
Up -Counter
0 0 1 1 1 0 0 1 1 1
0 1 0 0 1 0 1 0 0 1
0 1 0 1 1 1 0 0 1 1
0 1 1 0 1 1 1 0 0 1
0 1 1 1 0 0 0 1 1 1
1 0 0 0 1 1 1 1 1 1
1 0 0 1 0 0 0 0 0 1
1 0 1 0 0 0 1 0 1 1
Down -Counter
1 0 1 1 0 1 0 0 0 1
1 1 0 0 0 1 1 1 1 1
1 1 0 1 1 0 0 0 0 1
1 1 1 0 1 0 1 0 1 1
1 1 1 1 1 1 0 0 0 1
00 01 11 10 00 01 11 10 00 01 11 10
00 1 00 1 1 00 1 1 1 1
01 1 01 1 1 01 1 1 1 1
11 1 11 1 1 11 1 1 1 1
10 1 10 1 1 10 1 1 1 1
𝑇1 = 𝑀 ̅̅̅ ̅ 𝑄0
𝑄0 + 𝑀 𝑇0 = 1
̅̅̅1 𝑄
𝑇2 = 𝑀𝑄 ̅̅̅0 + 𝑀
̅ 𝑄1 𝑄0
57
Homework
Fig. 9-75
58

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Digital Techniques Dr.

Electrical Engineering Dept.

Class: First Year - 2022

Dr. MOHAMMED KAMIL

Textbook: Digital Fundamentals, Thomas L. Floyd, Eleventh Edition, 2015

5–2 Implementing Combinational Logic

• From a Truth Table to a Logic Circuit

Example 5–5 : Design a logic circuit to

Notice that X =1 for only three of the

5–4 Combinational Logic Using NAND and NOR Gates

Example: Rewrite the following expression using only NAND gate 𝑋 = 𝐴𝐵 + 𝐶𝐷

5–5 Pulse Waveform Operation

The operations are performed by a logic circuit called a half-adder.

A half-adder is represented by the logic symbol in Figure 6–1.

6–2 Parallel Binary Adders

Four-Bit Parallel Adders

That is, there is an output that indicates when number A is

To determine an inequality of binary numbers A and B, you

1. If A3 = 1 and B3 = 0, number A is greater than number B.

2. If A3 = 0 and B3 = 1, number A is less than number B.

The 4-Bit Decoder

In order to decode all possible combinations of four bits, sixteen

FIGURE 6–28 Logic symbol for a 4-line-to-16-line

The BCD-to-Decimal Decoder

The BCD-to-7-Segment Decoder

FIGURE 6–33 Logic symbol for a BCD-to-7-

An encoder is a combinational logic circuit that essentially performs a “reverse” decoder

The Decimal-to-BCD Encoder

This type of encoder has ten inputs—one for

FIGURE 6–36 Logic symbol for a decimal-to-BCD encoder.

FIGURE 6–37 Basic logic diagram of a decimal-to-BCD encoder. A 0-digit input is

6–7 Code Converters

Binary-to-Gray and Gray-to-Binary Conversion

6–8 Multiplexers (Data Selectors)

Eight-Input Data Selector/Multiplexer

The eight data inputs (D0–D7) and, therefore, three

• A Logic Function Generator

A useful application of the data selector/multiplexer is in the generation of combinational logic

The S-R (SET-RESET) Latch

The Gated S-R Latch

The Gated D Latch

Asynchronous Preset and Clear Inputs

7–4 Flip-Flop Applications

• A 2-Bit Asynchronous Binary Counter

• A 3-Bit Asynchronous Binary Counter

Asynchronous Decade Counters

9–3 Synchronous Counters

• A 2-Bit Synchronous Binary Counter

• A 3-Bit Synchronous Binary Counter

9–5 Design of Synchronous Counters

Step 1: State Diagram

The first step in the design of a state machine (counter) is to

FIGURE 9–26 State diagram

Step 2: Next-State Table

the second step is to derive a next-state table, which

Step 3: Flip-Flop Transition Table

Table 9–9 is a transition table for the J-K flip-flop. All

Present state Next state

Step 4: Karnaugh Maps

Step 6: Counter Implementation

D-Flip-Flop Transition Table

Present state Next state

Transition table for a T flip-flop

Present state Next state