ECEN620: Network Theory

Broadband Circuit Design

Fall 2023

Lecture 9: Digital PLLs

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• HW3 due Oct 31

• HW4 due Nov 7

2
Agenda
• Digital PLL Overview
• Linear Model
• Design Procedure
• Noise Analysis
• Time-to-Digital Converters
• Conclusion

3
References
• Techniques for High-Performance Digital
Frequency Synthesis and Phase Control,
C.-M. Hsu, MIT Thesis, 2008.

• [Kratyuk TCAS2 2007] provides a nice

design procedure

• TDC papers posted on the website

4
Analog PLL Issues
PFD
D UP ICP
Q
in R
Vctrl
VCO out
fb R DN
Q R C2
D
ICP
C1

Divider

1/N

• Charge pump suffers from UP/DN current mismatch,

low output impedance, and leakage
• Loop filter is large area and has noise and leakage
• Can we map this functionality to the digital domain?
5
Digital Mapping of CP & Loop Filter
𝑉 𝑠 1 𝛽
𝑅 ⇒𝐻 𝑧 𝛼
𝐼 𝑠 𝑠𝐶 1 𝑧
ICP
Charging 
Vctrl
IN  OUT
Discharging R C2  
ICP
C1
F(s) CLK

• Analog filter resistive proportional and capacitive integral gain is

mapped to a digital filter
• Large filter capacitor is replaced with a small digital accumulator
• Requires a digital input from a phase/time-to-digital converter

6
Digital PLL
Digital Loop Filter
DCO

in 
TDC  DAC VCO out
fb  
Z-1

Divider

1/N

• Time-to-digital (TDC) converts input phase error to

a digital word
• Digital loop filter provides PI control to allow for a
Type 2 system
• Digitally-controlled oscillator (DCO) produces the
output clock signal 7
Agenda
• Digital PLL Overview
• Linear Model
• Design Procedure
• Noise Analysis
• Time-to-Digital Converters
• Conclusion

8
Digital PLL Model
TDC DCO
TDC Loop DAC
Gain Filter Gain DT-CT
in[k] T 1 VFS KVCO
 H(z) T out(t)
2 t 2B j2f
z=ej2fT
fb[k]
CT-DT

1 1
N T
[Hsu Thesis 2018]
Divider

• A hybrid discrete- and continuous-time

model is used to capture the effects of
important noise sources 9
TDC Model
e[k]
fb(t) t t t t
1
t
te

t
in(t)
 e[k]

• TDC converts the time difference between the input and feedback
clocks to a digital code at a resolution t
1
TDC Gain = with units of 𝑠
∆
• Phase-domain model requires an initial scaling factor to convert the
input phase error to a timing error
𝑇
𝑡 𝜙
2𝜋
𝑇
Effective TDC Gain = with units of 𝑟𝑎𝑑
2𝜋∆ 10
Digital Loop Filter
 Analog Filter Transfer Function
IN  OUT 1
𝑅 𝑠
  𝐹 𝑠
𝑅𝐶
𝑠

CLK
w/ Bilinear Transform
𝛽 𝛽
𝛼 𝑠
2 𝛽
𝑂𝑈𝑇 𝛽 𝛼 𝑇
2
𝐻 𝑧 𝛼 𝐻 𝑠
𝐼𝑁 1 𝑧 𝑠

• Matching the analog filter transfer function results in

𝑇 𝑇
𝛼 𝑅 𝛽
2𝐶 𝐶
11
DCO Model
VFS
R/2
DCO
R
DAC
VCO out Gain DT-CT
R
VFS KVCO
DCO[k] T out(t)
R/2
2B j2f

DCO[k] Decoder
B

• DCO modelled as a DAC followed by a VCO

𝑉
DAC Gain = V/LSB
2
• Converting from DT-CT requires scaling by reference period T
• Standard phase-domain VCO model utilized
𝑉 𝑟𝑎𝑑
DCO Gain = 𝑇𝐾
2 𝑠 · 𝐿𝑆𝐵
12
Linear Digital PLL Model
TDC DCO
TDC Loop DAC
Gain Filter Gain DT-CT
in[k] T 1 VFS KVCO
 H(z) T out(t)
2 t 2B j2f
z=ej2fT
fb[k]
CT-DT

1 1
N T

Divider
𝛼 𝛽 𝛼𝑧 𝛼 𝛽 𝛼𝑒
𝐻 𝑧 𝐻 𝑒
1 𝑧 1 𝑒
𝑇 1 𝑉 𝐾
𝜙 𝑁 · 𝑇 · 𝐿𝐺 𝑓 𝑇 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓
𝜙 1 𝐿𝐺 𝑓 𝑇 1 𝑉 𝐾 1
1 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁
13
DT & CT Spectral Density Calculations
Since 𝐻 𝑓 is computed with a DT input, a CT 𝑆 𝑓 must be first converted to a
1
DT 𝑆 𝑒 by scaling with
𝑇
CT-DT

1 Sx(ej2fT)
Sx(f) H(f) Sy(f)
T

1
𝑆 𝑒 𝑆 𝑓
𝑇
Computing a CT 𝑆 𝑓 output with a DT 𝑆 𝑒 input through 𝐻 𝑓 requires
1
scaling by 1
𝑇 𝑆 𝑓 𝐻 𝑓 𝑆 𝑒
𝑇
Total system output with 𝑆 𝑓

1
𝑆 𝑓 𝐻 𝑓 𝑆 𝑓
𝑇 14
14GHz Digital PLL
Closed-Loop Transfer Function (Initial Design)
Parameter
Fref 156.25MHz
N 90
Fvco 14GHz
fu 2MHz
m 60°
f3dB 2.7MHz
t 10ps
2π*1MHz/LSB
(VFS/2B)Kvco
(10b)
 1.49
 7.11e-2

𝑇 1 𝑉 𝐾
𝜙 𝑓 1 𝑇 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓
𝜙 𝑓 𝑇 𝑇 1 𝑉 𝐾 1
1 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁
15
Digital PLL Loop Gain
TDC DCO
TDC Loop DAC
Gain Filter Gain DT-CT
in[k] T 1 VFS KVCO
 H(z) T out(t)
2 t 2B j2f
z=ej2fT
fb[k]
CT-DT

1 1
N T

Divider

𝑇 1 𝑉 𝐾 1
𝐿𝐺 𝑓 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁

16
Agenda
• Digital PLL Overview
• Linear Model
• Design Procedure
• Noise Analysis
• Time-to-Digital Converters
• Conclusion

17
Second-Order Digital PLL Design Procedure
• Design the digital PLL to emulate a second-order analog
charge-pump PLL [Kratyuk TCAS2 2007]
Digital PLL Analog PLL
𝑇 1 𝑉 𝐾 1 𝐼 𝑅 𝑠 𝜔 𝐾 1
𝐿𝐺 𝑓 𝐻 𝑒 ⟺ 𝐿𝐺 𝑠
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁 2𝜋 𝑠 𝑠 𝑁

𝑇 1 𝐼
Digital PLL PDC Gain ⟺ Analog PLL PFD Gain
2𝜋 Δ 2𝜋

Digital PLL 𝛽 𝑅 𝑠 𝜔 Analog PLL

Loop Filter 𝐻 𝑧 𝛼
1 𝑧
⟺𝐹 𝑠
𝑠 Loop Filter

Digital PLL 𝑉 Analog PLL

𝐾 ⟺ 𝐾
Effective DCO Gain 2 VCO Gain

18
Second-Order Digital PLL Design Procedure
1. Set z based on u and m specs PLL Specs
𝜔
𝜔 Parameter
tan Φ Fref 156.25MHz

𝜔 2𝜋 ∗ 2𝑀𝐻𝑧 & Φ 60° → 𝜔 2𝜋 ∗ 1.16𝑀𝐻𝑧 N 90

Fvco 14GHz
2. Compute an equivalent ICP based on TDC gain fu 2MHz
𝑇 m 60°
𝐼
Δ
t 10ps
𝐹 156.25𝑀𝐻𝑧 & Δ 10𝑝𝑠 ⟶ 𝐼 640𝐴
2π*1MHz/LSB
(VFS/2B)Kvco
3. Set an equivalent R value to achieve (10b)

required loop gain ??
 ??
2𝜋𝑁 𝜔
𝑅
𝑉 𝜔 𝜔
𝐼 𝐾
2

𝑉 2𝜋 ∗ 1𝑀𝐻𝑧
𝑁 90 & 𝐾 →𝑅 1.53Ω
2 𝐿𝑆𝐵 19
Second-Order Digital PLL Design Procedure
4. Set an equivalent C value to achieve z PLL Specs
1 Parameter
𝐶
𝜔 𝑅 Fref 156.25MHz
N 90
𝐶 90.1𝑛𝐹 Fvco 14GHz
fu 2MHz
5. Compute  and  from equivalent m 60°

R and C values
t 10ps
𝑇 𝑇 2π*1MHz/LSB
𝛼 𝑅 𝛽 (VFS/2B)Kvco
(10b)
2𝐶 𝐶
 ??
 ??
𝛼 1.49 & 𝛽 7.11 ∗ 10

20
Simulated Responses
𝑇 1 𝑉 𝐾
𝑇 1 𝑉 𝐾 1 𝜙 𝑓 1 𝑇 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓
𝐿𝐺 𝑓 𝐻 𝑒 𝑇 1 𝑉 𝐾 1
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁 𝜙 𝑓 𝑇 1 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁

• Design achieves fu=2MHz and m=60°

• Closed loop response has f3dB=2.7MHz
21
Agenda
• Digital PLL Overview
• Linear Model
• Design Procedure
• Noise Analysis
• Time-to-Digital Converters
• Conclusion

22
 Common Digital PLL Noise Sources
TDC DCO
TDC Loop DAC
n,in(t) CT-DT tq[k] Gain Filter DACq[k] Gain DT-CT n,DCO(t)

1 in[k] T 1 VFS KVCO

in(t)    H(z)  T  out(t)
T 2 t 2B j2f
z=ej2fT
fb[k]
CT-DT

1 1
N T

Divider

1
𝑆 𝑓 𝑆 𝑓 𝑁𝑇𝐹 𝑓
𝑇
1
𝑆 𝑓 𝑆 𝑒 𝑁𝑇𝐹 𝑓
𝑇
1
𝑆 𝑓 𝑆 𝑒 𝑁𝑇𝐹 𝑓
𝑇
𝑆 𝑓 𝑆 𝑓 𝑁𝑇𝐹 𝑓
𝑆 𝑓 𝑆 𝑓 𝑆 𝑓 𝑆 𝑓 𝑆 𝑓
23
Noise Transfer Functions
𝜙 𝑁 · 𝑇 · 𝐿𝐺 𝑓
𝑁𝑇𝐹 𝑓
𝜙 1 𝐿𝐺 𝑓
𝜙 𝑁 · 2𝜋 · 𝐿𝐺 𝑓
𝑁𝑇𝐹 𝑓
𝑡 1 𝐿𝐺 𝑓

𝐾
𝜙 𝑇
𝑗2𝜋𝑓
𝑁𝑇𝐹 𝑓
𝑞 1 𝐿𝐺 𝑓
𝜙 1
𝑁𝑇𝐹 𝑓
𝜙 1 𝐿𝐺 𝑓

• Input reference and TDC quantization noise is low-pass filtered

• Loop filter output DAC quantization noise (DCO input noise) is
band-pass filtered
• DCO output phase noise is high-pass filtered
24
Input Reference Noise
1 1 𝑁 · 𝑇 · 𝐿𝐺 𝑓
𝑆 𝑓 𝑆 𝑓 𝑁𝑇𝐹 𝑓 𝑆 𝑓
𝑇 𝑇 1 𝐿𝐺 𝑓

• After PLL: j,in = 217fsrms (10kHz – 10MHz)

• Including CDR: j,in = 46fsrms (100Hz – 7GHz)
25
TDC Quantization Noise
e[k]
fb(t) t t t t
1
t
te

t
in(t)
 e[k]

• Using the TDC output w/ t=10ps

∆
directly results in 𝑆 𝑒 231𝑑 𝐵 ⁄𝐻 𝑧
12
quantization noise
with a uniform power
spectral density

26
TDC Quantization Noise
1 1 𝑁 · 2𝜋 · 𝐿𝐺 𝑓
𝑆 𝑓 𝑆 𝑒 𝑁𝑇𝐹 𝑓 𝑆 𝑒
𝑇 𝑇 1 𝐿𝐺 𝑓

• After PLL: j,tq = 671fsrms (10kHz – 10MHz)

• Including CDR: j,tq = 345fsrms (100Hz – 7GHz)
• This is too high! Will need to increase TDC resolution.
27
Loop Filter DAC Quantization Noise
VFS
R/2

VCO out

R
1
𝑆 𝑒 10.8𝑑 𝐵⁄𝐻 𝑧
R/2 12

DCO[k] Decoder
B

DCO
DAC
DACq[k] Gain DT-CT
Loop
VFS KVCO
Filter  T out(t)
2B j2f
Output

• Truncating the digital filter output at a certain resolution

and applying it to the DAC results in quantization noise
with a uniform power spectral density
28
Loop Filter DAC Quantization Noise
𝐾
1 1 𝑇
𝑗2𝜋𝑓
𝑆 𝑓 𝑆 𝑒 𝑁𝑇𝐹 𝑓 𝑆 𝑒
𝑇 𝑇 1 𝐿𝐺 𝑓

• After PLL: j,DACq = 332fsrms (10kHz – 10MHz)

• Including CDR: j,DACq = 211fsrms (100Hz – 7GHz)
• This is too high! Will need to increase DAC resolution.
29
DCO Noise
1
𝑆 𝑓 𝑆 𝑓 𝑁𝑇𝐹 𝑓 𝑆 𝑓
1 𝐿𝐺 𝑓

• After PLL: j,in = 228fsrms (10kHz – 10MHz)

• Including CDR: j,in = 115fsrms (100Hz – 7GHz)
30
Total Noise
PLL Output
DCO
8%
Ref Clk
7%
DAC
17%

TDC
68%

Jitter
Variance DCO
7%
Ref Clk
DAC 1%
25%

TDC
67%
After CDR

• After PLL: j,Total = 842fsrms (10kHz – 10MHz)

• Including CDR: j,Total = 423fsrms (100Hz – 7GHz)
• TDC quantization noise dominates over much of the spectrum
• Loop filter DAC quantization noise is also significant
• Higher effective resolution TDC & DAC is necessary!
31
Increase TDC & DAC Resolution
PLL Output
DCO Ref Clk
42%
38%

DAC TDC
14%
6%

Jitter
Variance Ref Clk
3%
TDC DAC
4%
8%

DCO
85%
After CDR

• Increase resolution: TDC t=2ps & (VFS/2B)KVCO=250kHz (12b)

• After PLL: j,Total = 353fsrms (10kHz – 10MHz)
• Reference clock noise dominates at low frequency
• DCO dominates near loop bandwidth and higher
• Including CDR: j,Total = 151fsrms (100Hz – 7GHz)
• Now DCO noise clearly dominates total 32
 Delta Sigma Modulation
1
DACqraw[k] 𝑆 𝑒 𝑁𝑇𝐹∆ 𝑒
 Modulator 12
1
NTF(z) DCO 1 𝑒
12
=1-z-1 DAC
Gain DT-CT
Loop DACq[k]
STF(z) VFS KVCO
Filter  T out(t)
=1 2B j2f
Output

• DS modulation provides high-

pass quantization noise
shaping to dramatically
reduce low-frequency content

33
With Delta-Sigma Modulation
PLL Output
DCO Ref Clk
52.4% 47.2%

TDC & DAC <1%

Jitter
Variance
Ref Clk
12%
TDC
8% DAC
6%
DCO
74%
After CDR

• Add  modulation to TDC t=2ps & (VFS/2B)KVCO=250kHz (12b)

• After PLL: j,Total = 316fsrms (10kHz – 10MHz)
• Reference clock noise dominates at low frequency
• DCO dominates near loop bandwidth and higher
• Including CDR: j,Total = 133fsrms (100Hz – 7GHz)
• Now DCO noise clearly dominates total
• Some contribution from TDC & DAC at high frequency 34
With Delta-Sigma Modulation
& Relaxed TDC & DAC
PLL Output
Ref Clk
46.7%
DCO
51.8%

TDC
1%
DAC 0.5%

Jitter
Variance Ref Clk
3%
TDC DAC
14% 6%

DCO
77%
After CDR

• Include  modulation with relaxed TDC t=5ps & (VFS/2B)KVCO=500kHz (11b)

• After PLL: j,Total = 318fsrms (10kHz – 10MHz)
• Reference clock noise dominates at low frequency
• DCO dominates near loop bandwidth and higher
• Including CDR: j,Total = 169fsrms (100Hz – 7GHz)
• Now DCO noise clearly dominates total
• Increased contribution from TDC & DAC at high frequency could be reduced with additional
passive filter after DAC and/or operating  with higher frequency clock 35
Agenda
• Digital PLL Overview
• Linear Model
• Design Procedure
• Noise Analysis
• Time-to-Digital Converters
• Conclusion

36
Flash TDC
e[k]
CLKFB(t) t t t t
1
t
te

t
CLKIN(t)
 e[k]

• Flash TDC converts the time difference

between the input and feedback clocks
to a digital code at a resolution t with
a single delay chain

• Unit cell delay limits TDC resolution

and can introduce significant
quantization noise
37
Vernier TDC
t = t1 - t2
e[k]
CLKFB(t) t1 t1 t1 t1
1
t
te

t
CLKIN(t) t2 t2 t2
 e[k]

• Both inputs pass through different delay lines

• Increases TDC resolution to t1-t2
• Sensitive to mismatch between the two delay lines
• Delay stage count scales with increased resolution
to cover a given full scale range
38
Two-Step TDC
[Ramakrishnan VLSID 2006]

• Coarse conversion with input flash TDC

• Time residue transferred to Vernier TDC for fine conversion
• Allows for Vernier resolution with reduced area for a given
full scale range
39
Two-Step TDC w/ Time Amplification

[Lee JSSC 2008]

• Utilizes two single delay chain

TDCs with a time amplifier
between stages to improve
resolution
• Time amplifier is based on
unbalanced SR latches
• Achieves 1.25ps LSB in 90nm
40
Interpolating TDC
• Interpolation with
passive resistors
provides a simple
technique to increase
TDC resolution
• Delay line output is
cycled through the
loop to increase
conversion range
[Henzler ISSCC 2008]

41
 Oscillator-Based TDC
[Hsu JSSC 2008]

• Gated ring oscillator (GRO) is enabled between rising

edges of the two input clocks
• Counting the oscillator transitions performs the conversion
• The GRO retains internal state between measurements,
providing first-order quantization noise shaping 42
Oscillator-Based TDC
[Hsu JSSC 2008]

• All transitions of the oscillator’s multiple phases can be

counted to increase resolution
• Resolution is further increased with a multipath ring oscillator
• Achieves 6ps resolution in 0.13um
43
Conclusion
• Digital PLLs can eliminate analog charge
pump non-idealities and allow for lower-
area loop filters
• Key blocks are the input TDC, digital PI
loop filter, and DCO
• Quantization noise is introduced by the
TDC and loop filter DAC/DCO
• Advanced TDC architectures can achieve
sub-inverter delay resolution
44
Next Time
• Fractional-N Frequency Synthesizers

45