MUNHUMUTAPA SCHOOL OF COMMERCE

DEPARTMENT OF ACCOUNTING & INFORMATION SYSTEMS

NAME : EPAPHRAS SIMANGO

REG NUMBER : M101947

PROGRAMME : BCOM HONS INFORMATION SYSTEMS

LEVEL : 1.1 (BLOCK RELEASE)

MODULE TITLE : COMPUTER ARCHITECTURE

MODULE CODE : ISH 114

LECTURER : MRS NYAMAPFENI L

ASSIGNMENT NO : 01

MARK : ……………………………….

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LECTURERS’ REMARKS:…………………………………………………………………..

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1 .What is the distinction between computer structure and computer function? (2)
Structure is how devices are interrelated, while function is the individual characteristics of
each one.
• Structure: The way in which the components are interrelated.
• Function: The operation of each individual component as part of the structure

2. List and define the main structural components of a computer. (3)

CPU (Central processing unit): known as processor as well, it’s the main computer
component, responsible for the main functions of the computer.
I/O: responsible for the communication between the computer and the external world.
Data storage: device responsible for data saving.
System bus: responsible for the interconnection between data storage, CPU and I/O

3. Explain Moore’s Law (4)

Moore's Law states that the number of transistors on a microchip doubles every two years.
The law claims that we can expect the speed and capability of our computers to increase
every two years because of this, yet we will pay less for them.

Moore's Law states that the number of transistors on a microchip doubles about every two
years, though the cost of computers is halved.

In 1965, Gordon E. Moore, the co-founder of Intel, made this observation that became
known as Moore's Law.

Another tenet of Moore's Law says that the growth of microprocessors is exponential .

4. What is meant by register transfer? Explain in detail .Also discuss three-state bus
buffer (5)
The information transformed from one register to another register is represented in symbolic
form by replacement operator is called Register Transfer. The term Register Transfer refers
to the availability of hardware logic circuits that can perform a given micro-operation and
transfer the result of the operation to the same or another register.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state
buffers.

o The outputs generated by the four buffers are connected to form a single bus line.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
o A 2 * 4 decoder ensures that no more than one control input is active at any given
point of time
5. Explain register stack and memory stack with neat sketches (4)

A stack is a data storage structure in which the most recent thing deposited is the most recent
item retrieved .it is based on the LIFO, last in first out concept . The stack is a collection of
memory locations containing a register that stores the top of element address in digital
computers. Stack is implemented using Two ways which are register stack and memory stack
.

Register Stack Memory stack

Register stacks are momentary spaces for Memory stacks are a series of memory
internal processes that are being done by spaces that is used in the processes that is
the processer done by processor and are temporarily
stored in registers .

Register stack is generally on CPU Memory stack is on RAM

Access to register stack is faster Access to memory stack is slower

It is limited in size It is larger in size

In the figure, the SP points to a beginning value ‘2001’. Therefore, the stack increase with
decreasing addresses. The first element is saved at address 2000, the next element is saved at
address 1999 and the last element is saved at address 1000.

The data register can read an element into or from the stack. It can use push operation to
insert a new element into the stack.

SP ← SP – 1

K ← SP [DR]

It can insert another element into the stack, the stack pointer is decremented by 1. It can point
to the address of the next location/word. A word from DR is inserted into the top of the stack
using memory write operation.

It can delete an element from the stack. It can use the pop operation which is as follows −
DR ← K [SP]

SP ← SP + 1

The top element is read into the DR and then the stack pointer is decremented to point to the
next element in the stack.

Two processor registers can check the stack limits. One processor register influence the upper
limit (1000) and the other influence the lower limit (2001). During push operation, the SP is
compared with the upper limit to check if the stack is full. During pop operation, the SP is
compared with the lower limit to check if the stack is empty.

The stack can be arranged as a set of memory words or registers. Consider a 64-
word register stack arranged as displayed in the figure. The stack pointer register
includes a binary number, which is the address of the element present at the top of
the stack. The three-element A, B, and C are located in the stack.
The element C is at the top of the stack and the stack pointer holds the address of C
that is 3. The top element is popped from the stack through reading memory word at
address 3 and decrementing the stack pointer by 1. Then, B is at the top of the stack
and the SP holds the address of B that is 2. It can insert a new word, the stack is
pushed by incrementing the stack pointer by 1 and inserting a word in that
incremented location.
The stack pointer includes 6 bits, because 2 6 = 64, and the SP cannot exceed 63
(111111 in binary). After all, if 63 is incremented by 1, therefore the result is
0(111111 + 1 = 1000000). SP holds only the six least significant bits. If 000000 is
decremented by 1 thus the result is 111111.
Therefore, when the stack is full, the one-bit register ‘FULL’ is set to 1. If the stack is
null, then the one-bit register ‘EMTY’ is set to 1. The data register DR holds the
binary information which is composed into or readout of the stack.
First, the SP is set to 0, EMTY is set to 1, and FULL is set to 0. Now, as the stack is
not full (FULL = 0), a new element is inserted using the push operation.
The push operation is executed as follows −

SP←SP + 1 It can increment stack pointer

K[SP] ← DR It can write element on top of the stack

If (SP = 0) then (FULL ← 1) Check if stack is full

EMTY ← 0 Mark the stack not empty

The stack pointer is incremented by 1 and the address of the next higher word is
saved in the SP. The word from DR is inserted into the stack using the memory write
operation. The first element is saved at address 1 and the final element is saved at
address 0. If the stack pointer is at 0, then the stack is full and ‘FULL’ is set to 1.
This is the condition when the SP was in location 63 and after incrementing SP, the
final element is saved at address 0. During an element is saved at address 0, there
are no more empty registers in the stack. The stack is full and the ‘EMTY’ is set to 0.
A new element is deleted from the stack if the stack is not empty (if EMTY = 0). The
pop operation includes the following sequence of micro-operations −

DR←K[SP] It can read an element from the top of the stack

SP ← SP – 1 It can decrement the stack pointer

If (SP = 0) then (EMTY ← 1) Check if stack is empty

FULL ← 0 Mark the stack not full

The top element from the stack is read and transfer to DR and thus the stack pointer
is decremented. If the stack pointer reaches 0, then the stack is empty and ‘EMTY’
is set to 1. This is the condition when the element in location 1 is read out and the
SP is decremented by 1.
6. A computer uses a memory unit with 256k words of 32-bit each. A
binary instruction code is stored in one word of memory. The instruction
has four parts : an indirect bit ,an operation code, a register code part to
specify one of 64 registers and an address part
a. how many bits are there in operation code, the register code part and
the address part
b. Draw the instruction word format and indicate the number of bits in
each part
c. How many bits are there in the data and address inputs
of the memory [7
a) Data
1 word = 32 bits = 4 bytes
Memory size = 256k words = 218 words
Indirect bits = 1
Number of registers = N = 64

Formula
Number of bits needed to present a register = [log 2 N]
= [log 2 64]
=6
Binary instruction (32 bit) = Indirect bit + Operation code + Register code +
Address part
= 1 + operation code + 6 + 18 = 32
operation code = 32 – 18 – 6 – 1
=7
Therefore, Operation Code = 7 bits, Register Code = 6 bits and Address Code
= 18 bits

b) 1 7 6 18

I Operation Register Address

code code code
 c) Data = 32 bits
Address = 18 bits

References
https://www.tutorialspoint.com/index.htm

COMPUTER ORGANIZATION AND DESIGN THE

HARDWARE/SOFTWARE INTERFACE FIFTH EDITION DAVID A.
PATTERSON JOHN L HENNESSY
STRUCTURED COMPUTER ORGANIZATION FIFTH EDITION
Andrew S Tanenbaum
COMPUTER ORGANISATION and ARCHITECTURE Designing for
performance Tenth Edition William Stallings