3/26/24, 12:23 PM Physical Design Interview Questions

Physical Design Interview Questions

Total points 8/20

1.When did hold analysis depends on the frequency of the clock * 0/1

single cycle path

it never depends

half cycle path

multicycle path

Correct answer

half cycle path

2.Why do we add tap cells * 0/1

to prevent DRC's

to prevent latch up

to maintain well continuity

All of the above

Correct answer

to prevent latch up

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3.If the schematic has 11 and layout is 10 nets then, what might be *0/1
reason

opens

All of the above

shorts

ERC

Correct answer

opens

4.High positive skew leads to * 1/1

hold violation

setup violation

All of the above

DRC

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5. For multi-voltage blocks which power cells are used * 0/1

All of the above

level shifters

retention cells

isolation cells

Correct answer

All of the above

6. What is a physical cell? * 0/1

cell is not synthesized

cell which doesn't have any functionality

cell which is inserted only in layout

All of the above

Correct answer

All of the above

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7.Which of the following is not present in SDC * 1/1

max current density

max cap

max fanout

max trans

8.Which slew value will be propagated to slew _out of slew _A is 100 ps *0/1
and slew_B is 80ps for hold analysis

80 ps

100 ps

20 ps

180 ps

Correct answer

100 ps

9. Digital signals transmitted on a single conductor must be transmitted *1/1

in

digital

None of the above

slow speed

serial

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10. Static power can be reduced by placing * 1/1

None of the above

LVT Cells

HVT Cells

SVT/RVT cells

11. End Cap cell is used * 0/1

To avoid the dynamic drop

To avoid cell damage at the end of row

To avoid dynamic power dissipation

To connect the Gap between cells

Correct answer

To avoid cell damage at the end of row

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12.Capacitiance table can be created by * 0/1

.sdc

.lib file

.tf file

.lef file

Correct answer

.lef file

13. Which of the following is preferred while placing macros. * 1/1

Macros placed left and right side of die

Macros placed based on the connectivity of the I/O

Macros placed top and bottom side of die

Macros placed center of the side

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14. Filler cells are added * 0/1

Before detail routing

After placement of STD cells

Before placement of STD cells

Before floorplanning

Correct answer

Before detail routing

15. In soft Blockage cells are placed * 1/1

Any cells

No cells

Only buffer and inverters

Only Sequential

16. FRAM view has * 1/1

Layout information and used place & route

Abstract view and used at the time of tape-out

Abstract view and used in place and route

Layout information and used at the time of tape-out

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17. Tap cells are used * 0/1

To avoid the dynamic IR drop

To avoid latch up problem

To avoid dynamic power dissipation

To connect the gap between cells

Correct answer

To avoid latch up problem

18. Which of the following metal layers has max resistance. * 0/1

Metal 2

Metal 3

Metal 4

Metal 5

Correct answer

Metal 2

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19.Maximum current density of a metal is available in * 1/1

.tf

.v

.sdc

.lib

20.Chip utilization depends on * 0/1

Standard cells and macros

Only on standard cells

Standard cells macros and IO pads

Only on macros

Correct answer

Standard cells and macros

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