12 SDH Bavsics

Department of: technology programs and customer service
SDH Basics
Code: TS12TEC05En
1 PDH Multiplexing Pages (1-12)
Sub - Sections
Principles and Characteristics of
2 Pages (1-16)
the SDH
3 Basic Elements of STM-1 Pages (1-7)
4 Mapping Pages (1-50)
5 Pointer Pages (1-16)

SDH Basics
6 Overhead Pages (1-26)
Monitoring, Maintenance and

7 Pages (1-33)
Control in the SDH
8 Appendix Pages (1-25)
This document consists of 185 pages.

Chapter 1: PDH Multiplexing
Chapter 1 PDH Multiplexing
Aim of study
This chapter introduces principles of PDH multiplexing and multiplexing / demultiplexing
of PDH signals.
Contents Pages
1 Introduction 2
2 Principles of PDH Multiplexing 2
3 ANSI / CEPT Bit Rates 3
4 Frame Structure of a PDH Signal 7
5 Multiplexing / Demultiplexing of PDH Signals 7
6 Summary 10
7 Exercise 11
8 Solution 12
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Chapter 1
PDH Multiplexing
1 Introduction
In the early 1970s, digital transmission systems began to appear, utilizing a

method known as Pulse Code Modulation (PCM), first proposed in 1937.
PCM allowed analog waveforms, such as the human voice, to be represented
in binary form, and using this method it was possible to represent a standard 4
kHz analog telephone signal as a 64 kbit/s digital bit stream. Engineers saw
the potential to produce more cost effective transmission systems by
combining several PCM channels and transmitting them down the same
copper twisted pair as had previously been occupied by a single analog signal.
In Europe, and subsequently in many other parts of the world, a standard

TDM scheme was adopted whereby thirty 64 kbit/s channels were combined,
together with two additional channels carrying control information, to produce
a channel with a bit rate of 2.048 Mbit/s.
2 Principles of PDH Multiplexing
PDH signals with a higher transmission rate are obtained by multiplexing

several lower rate signals. The term PDH will be defined in the next few
pages, however, let us consider the following concepts:
Multiplex Operation
Four input signals with the same nominal bit rate are combined to form one
multiplex signal and then relayed to the receive side via one common
transmission path.
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De-multiplex Operation:
On the receive side, the sum signal is again distributed to the corresponding
outputs.
Fig. 1
3 ANSI / CEPT Bit Rates
As demand for voice telephony increased, and levels of traffic in the network
grew ever higher, it became clear that the standard 2 Mbit/s signal was not
sufficient to cope with the traffic loads occurring in the trunk network. In
order to avoid having to use excessively large numbers of 2 Mbit/s links, it
was decided to create a further level of multiplexing. The standard adopted in
Europe involved the combination of four 2 Mbit/s channels to produce a single
8 Mbit/s channel. This level of multiplexing differed slightly from the
previous in that the incoming signals were combined one bit at a time instead
of one byte at a time i.e. bit interleaving was used as opposed to byte
interleaving. As the need arose, further levels of multiplexing were added to
the standard at 34 Mbit/s, 140 Mbit/s, and 565 Mbit/s to produce a full
hierarchy of bit rates.
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The multiplexing hierarchy described above appears simple enough in

principle but there are complications. When multiplexing a number of 2
Mbit/s channels they are likely to have been created by different pieces of
equipment, each generating a slightly different bit rate. Thus, before these 2
Mbit/s channels can be bit interleaved they must all be brought up to the same
bit rate (called "adaptation"), adding 'dummy' information bits, or 'justification
bits'. The justification bits are recognize as such when demultiplexing occurs,
and discarded, leaving the original signal. This process is known as
plesiochronous operation, from Greek, meaning "almost synchronous".
The same problems with synchronization, as described above, occur at every

level of the multiplexing hierarchy, so justification bits are added at each
stage.
The use of plesiochronous operation throughout the hierarchy has led to

adoption of the term "Plesiochronous Digital Hierarchy", or PDH.
Another Explanation to help define PDH is:
If two digital signals are Plesiochronous, their transitions occur at “almost” the
same rate, with any variation being constrained within tight limits. These
limits are set down in ITU-T recommendation G.703. For example, if two
networks need to interwork, their clocks may be derived from two different
PRCs. Although these clocks are extremely accurate, there’s a small frequency
difference between one clock and the other. This is known as a Plesiochronous
difference.
It may be useful to explain the term Asynchronous at this stage:
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In Asynchronous signals, the transitions of the signals don’t necessarily occur

at the same nominal rate. Asynchronous, in this case, means that the
difference between two clocks is much greater than a Plesiochronous
difference.
Standardized Bit Rates in the "Plesiochronous Digital Hierarchy" (PDH)
Traditionally, digital transmission systems and hierarchies have been based on

multiplexing signals which are plesiochronous (running at almost the same
speed).Also, various parts of the world use different hierarchies which lead to
problems of international interworking; for example, between those countries
using 1.544 Mbit/s systems (U.S.A. and Japan) and those using the 2.048
Mbit/s system.
To recover a 64 kbit/s channel from a 140 Mbit/s PDH signal, it’s necessary to
demultiplex the signal all the way down to the 2 Mbit/s level before the
location of the 64 kbit/s channel can be identified. PDH requires “steps” (140-
34, 34-8, 8-2 demultiplex; 2-8, 8-34, 34- 140 multiplex) to drop out or add an
individual speech or data channel. This is due to the bit stuffing used at each
level.
Comparison of the ANSI and CEPT Hierarchies
We will consider only two hierarchies, even though Japan has its own
hierarchy it will not be studied in this course.
• PDH in accordance with ANSI (American National Standards Institute);

basic bit rate employed is 1,5 Mbit/s, e.g. USA.
• PDH in accordance with CEPT (Conférence Européene des
Administrations des Postes et des Telécommunications) basic bit rate
employed is 2 Mbit/s, e.g. Europe.
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Fig. 2
Fig. 3 Plesiochronous digital hierarchy
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4 Frame Structure of a PDH Signal
Every signal within a CEPT hierarchy level has a specific frame structure
which basically consists of the following blocks:
Fig. 4 Frame structure of a PDH signal
5 Multiplexing / Demultiplexing of PDH Signals
A multiplex sum signal is generated from the partial signals 1, 2. 3 and 4 (also
termed input, incoming, or sub signals) through the method of bit interleaving
==> bit-by-bit multiplexing.
Fig 5
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Fig. 6
Here, the insertion of the Frame Alignment Signal (FAS), the justification bits,
etc. into the multisignal is not yet taken into consideration.
The bits of the frame alignment signals (FAS) contained in the input signals I
and II respectively are also inserted bit-by-bit into the multiplexed signal.
Fig. 7
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Caution!
After the multiplex operation, the two FAS no longer form a joint unit. Beside
performing the bit interleaving, the multiplexer has also the function to create
a new CEPT frame for the multiplexed signal. Within this frame, the tributary
information is represented by the two complete CEPT frames of input signals I
and II.
Fig. 8
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There is no phase relationship between the FAS of the multiplexed signal and
the individual frame alignment signals of the tributary signals 1 and 2. A new
frame for the multiplexed signal is created. This new frame has its own FAS.
Fig. 9
6 Summary
Principles of PDH Multiplexing:
• Bit rates in accordance with ANSI: 1,5 Mbit/s, 6 Mbit/s and 45 Mbit/s
• Bit rates in accordance with 2 Mbit/s, 8 Mbit/s, 34 Mbit/s and 140 Mbit/s
CEPT:
• Every signal has a separate frame structure.
• Bit-by-bit multiplexing.
• No frame synchronization of the tributary signal inputs.
• The input signals of the tributaries are plesiochronous to each other, i.e.
their clock rates have the same nominal value, but there is, however, a
slight amount of variation between the two.
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7 Exercise
1. What are the bit rates of the CEPT Hierarchy?
2. What are the elements of PDH frames and what is their function?
3. How many different FAS do exist in a 140 Mbit frame?
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8 Solution
1. What are the bit rates of the CEPT Hierarchy?
2 Mbit/s
8 Mbit/s
34 Mbit/s
140 Mbit/s
2. What are the elements of PDH frames and what is their function?
FAS Frame Alignment Signal
D+N bit Service bits
TB Tributary bits
CB Control bits for justification
JB Justification opportunity bit
3. How many different FAS do exist in a 140 Mbit frame?
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Chapter 2: Principles and Characteristics of the SDH
Chapter 2 Principles and Characteristics of the

SDH
Aim of study
This chapter introduces introduction to the Synchronous Digital Hierarchy SDH.
Contents Pages
1 Introduction to the Synchronous Digital Hierarchy SDH 2

2 ITU-T and SDH, an Introduction 4
3 ITU-T Recommendations for SDH Bit Rates 6
4 Structure of an STM-1 Frame 7
5 Byte-by-Byte Multiplexing of SDH Signals 8
6 Synchronization of STM-1 Frames 9
7 Line Codes used in SDH 11
8 Summary 14
9 Exercise 15
10 Solution 16
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Chapter 2
Principles and Characteristics of the SDH
1 Introduction to the Synchronous Digital Hierarchy SDH
Why use SDH instead of PDH?
The problem of flexibility in a plesiochronous network is illustrated by

considering what a network operator may need to do in order to be able to
provide a business customer with a 2 Mbit/s leased line. If a high speed
channel passes near the customer, the operation of providing him with a single
2 Mbit/s line from within that channel would seem straightforward enough. In
practice, however, it is not so simple.
The use of justification bits at each level in the PDH means that identifying
the exact location of the frames in a single 2 Mbit/s line within say a 140
Mbit/s channel is impossible. In order to access a single 2 Mbit/s line the 140
Mbit/s channel must be completely demultiplexed to its 64 constituent 2
Mbit/s lines via 34 and 8 Mbit/s. Once the required 2 Mbit/s line has been
identified and extracted, the channels must then be multiplexed back up to 140
Mbit/s.
Obviously this problem with the "drop and insert" of channels does not make
for very flexible connection patterns or rapid provisioning of services, while
the "multiplexer mountains" required are extremely expensive.
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Another problem associated with the huge amount of multiplexing equipment

in the network is one of control. On its way through the network, a 2 Mbit/s
leased line may have traveled via a number of possible routes. The only way
to ensure it follows the correct path is to keep careful records of the
interconnection of the equipment. However, as the amount of reconnection
activity in the network increases it becomes more difficult to keep records
current and the possibility of mistakes increases. Such mistakes are likely to
affect not only the connection being established but also to disrupt existing
connections carrying live traffic.
Another limitation of the PDH is its lack of performance monitoring

capability.
Operators are coming under increasing pressure to provide business customers

with improved availability and error performance, and there is insufficient
provision for network management within the PDH frame format for them to
be able to do this.
Hence the development of the SDH technology.
What do we mean by Synchronous Digital Signals in an SDH network?
Having just described why we may want to use SDH in preference to PDH, let
us now define a PDH and SDH network in simple terms.
When data signals with the same nominal bit rate (which could have different
sources, as in plesiochronous signals), are controlled by a central clock
frequency (the master clock), the signals are termed synchronous, (i.e. as in a
synchronous network). Thus we can say:
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In a plesiochronous network, the individual link sections are not synchronous

to each other.
In the synchronous network, on the other hand, the link sections are
synchronous to each other.
Now let us focus on a system that uses synchronous digital signals, i.e. SDH.
2 ITU-T and SDH, an Introduction
Background
Before SDH, the first generations of fiber-optic systems in the public

telephone network used proprietary architectures, equipment line codes,
multiplexing formats, and maintenance procedures. The users of this
equipment wanted standards so they could mix and match equipment from
different suppliers.
The task of creating such a standard was taken up in 1984 by the Exchange
Carriers Standards Association (ECSA) in the U.S. to establish a standard for
connecting one fiber system to another. In the late stages of the development,
the CCITT became involved so that a single international standard might be
developed for fiber interconnects between telephone networks of different
countries. The resulting international standard is known as Synchronous
Digital Hierarchy (SDH).
SDH Advantages
The primary reason for the creation of SDH was to provide a long-term
solution for an optical mid-span meet between operators; that is, to allow
equipment from different vendors to communicate with each other.
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This ability is referred to as multivendor interworking and allows one SDH-

compatible network element to communicate with another, and to replace
several network elements, which may have previously existed solely for
interface purposes. SDH (Synchronous Digital Hierarchy) is a standard for
telecommunications transport formulated by the International
Telecommunication Union (ITU), previously called the International
Telegraph and Telephone Consultative Committee (CCITT).
SDH was first introduced into the telecommunications network in 1992 and
has been deployed at rapid rates since then. It’s deployed at all levels of the
network infrastructure, including the access network and the long-distance
trunk network. It’s based on overlaying a synchronous multiplexed signal onto
a light stream transmitted over fiber-optic cable. SDH is also defined for use
on radio relay links, satellite links, and at electrical interfaces between
equipment.
The comprehensive SDH standard is expected to provide the transport

infrastructure for worldwide telecommunications for at least the next two or
three decades. The increased configuration flexibility and bandwidth
availability of SDH provides significant advantages over the older
telecommunications system. These advantages include:
• A reduction in the amount of equipment and an increase in network

reliability.
• The provision of overhead and payload bytes; the overhead bytes
permitting management of the payload bytes on an individual basis and
facilitating centralized fault sectionalization.
• The definition of a synchronous multiplexing format for carrying lower
level digital signals (such as 2 Mbit/s, 34 Mbit/s, 140 Mbit/s) which
greatly simplifies the interface to digital switches, digital cross-
connects, and add-drop multiplexers.
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• The availability of a set of generic standards, which enable multi vendor

interoperability.
• The definition of a flexible architecture capable of accommodating
future applications, with a variety of transmission rates.
3 ITU-T Recommendations for SDH Bit Rates
The ITU-T (International Telecommunication Union -Telecommunication

sector) specified a base signal, the STM-1 (Synchronous Transport Module-1)
with 155,520 Mbit/s.
All multiplex levels in the SDH are positive integer multiples of this base
signal "STM-1".
In this way, a world-wide uniform concept for the transmission of 155 Mbit/s
data signals was provided, which means that all previous PDH signals (CEPT
/ ANSI ) must be interleaved to the SDH base signal by a procedure called
"MAPPING".
Fig. 1
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4 Structure of an STM-1 Frame
The two-dimensional representation of an STM-1 frame includes 9 rows with

270 bytes each.
The sequence of transmission is: top left to bottom right.
Fig. 2
The STM-1 frame consists of three blocks:
• Pointer (PTR): indicates the start address of the tributary information.

• Section OverHead (SOH): additional transmission capacity.
• Payload: tributary information.
The frames are transmitted in intervals of 125 µs.
The STM-1 frame is repeated (1s: 125 µs) = 8000 times per second.
Thus, every byte in an STM-1 frame has a transmission capacity of 64 kbit/s.
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Fig. 3
5 Byte-by-Byte Multiplexing of SDH Signals
Multiplex Technique (Transmitter)
Contrary to the PDH, the SDH uses the method of BYTE INTERLEAVING
to generate the multiplex sum signal * out of the sub-signals I and II
byte-by-byte multiplexing.
The multiplex signal STM-4 has the same frame duration as the STM-1, i.e.
125µs.
NOTE!
The explanation given in the example has been simplified. SDH equipment
adds SOH at different stages of the multiplex process. There is no need to go
into too much detail at this stage. This is sufficient to give an understanding of
the principles.
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For a better understanding, the generation of an STM-4 frame was explained

here with only 2 STM-1 frames, although in practice 4 STM-1 frames are
multiplexed.
Fig. 4
Fig. 5 Frame 2 x STM-1 ----> 1 x STM-2
6 Synchronization of STM-1 Frames
Even in a synchronous network, the frames STM-1 # 1 and STM-1 # 2(3, 4)

are usually delayed in time (e.g. due to different run times).
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Fig. 6
Prior to multiplexing, the subsignals STM-1 # 1 and STM-1 # 2(3, 4) are

synchronized to each other that means frame alignment signal and pointer are
synchronized but the tributary information is neither modified nor delayed.
The modification of the pointer during synchronization is called "pointer

adjustment operation".
Fig. 7
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7 Line Codes used in SDH
7.1 Codes and Interfaces of SDH
The optical line code for all STM-N signals is a scrambled
"NON - RETURN -TO -ZERO (NRZ)" -Code!
By scrambling the NRZ code it is ensured that when sending an STM signal
on the line, the signal includes sufficient clock edges to allow timing recovery
on the receiver side. The transmission of long "0" or "1" bit sequences must
therefore be avoided.
STM-1, STM-N Scrambler
Fig. 8 STM-N scrambling
When sending an STM signal on the line it must be ensured that the signal
includes sufficient clock edges to allow timing recovery on the receiver side.
The transmission of long „0“ or „1“ bit sequences must therefore be avoided.
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For transmission on coaxial lines the established practice for electric signals is
to select a line code which suffices to enable clock recovery on the receiver
side.
Both STM-1 and STM-N are provided for transmission on optical fiber routes.
Scrambling of the electrical signal is sufficient for transmission of the optical

signal. Long „0“ or „1“ bit sequences are avoided and no elaborate line code is
required. In addition to the optical interface, a CMI-coded electrical interface
is defined (G.703) for the STM-1 signal.
General Scrambler Function
The scrambler is a transmit-side device, which converts an existing digital

signal to a different signal with a pseudo-random bit sequence without altering
the bit rate. A descrambler on the receive side then reconstructs the original bit
sequence. The scrambler/descrambler is technically implemented through a
shift register whose output is logically linked with the input.
Application to STM-N
The STM signal of the synchronous hierarchy is scrambled only prior to its
optical conversion for transmission on optical fiber. Accordingly, an STM-1
or STM-N signal is not scrambled if it is first being encoded to a higher-level
multiplex signal. Only a multiplex signal, which is converted, to an optical
transmission signal is subjected to the scramble procedure.
The scramble procedure is applied to all bytes in the respective STM-1 or

STM-N frame apart from the first row in the overhead section (Fig. 8). The
first row (N x 9 bytes) includes the frame alignment signal amongst others.
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As this frame alignment signal is not scrambled, the synchronization to this

FAS is possible without previous descrambling.
7.1.1 STM-1, Electrical Interface
The following values in conformity with G.703 are apply to electrical

interface.
Bit rate: 155.52 Mbit/s
Code: CMI (coded mark inversion code)
Level: 1,0 VSS + 0,1 V
The CMI code is a binary transmission code. The binary values „1“ are
alternately represented by a positive and negative status and the binary values
„0“ are always represented by a negative status in the first half and a positive
status in the second half of the binary interval.
Fig. 9 CMI code for electrical interface
7.1.2 STM-1 and STM-N, Optical Interface
Bit rate: N x 155.52 Mbit/s scrambled
Code: NRZ
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8 Summary
Principles and Characteristics of the SDH:
• Bit rates exceeding 140 Mbit/s are standardized on a worldwide basis.

• Both synchronous and plesiochronous operation is possible.
• All current PDH signals (CEPT/ANSI) can be transmitted within the
SDH (except 8 Mbit/s).
• The "Section OverHead" bytes provide a high transmission capacity for
monitoring, maintenance and control tasks.
• High-level multiplex signals are integer multiples (=N) of the basic bit
rate (155,520 Mbit/s).
• For the first time, the optical line code is standardized worldwide.
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9 Exercise
1. What are the bit rates in the SDH?
2. How many bytes are transmitted in a STM-1 signal?
3. What are the three main blocks of the STM-1 signal?
4. List the line codes used for SDH optical and electrical line signals?
5. What is the main function of scrambler?
6. Which part of the STM-N is not scrambled?
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10 Solution
1. What are the bit rates in the SDH?
155.52 Mbit/s
622.08 Mbit/s
2.5 Gbit/s, 9953,228 Mbit/s, and 39813,12 Mbit/s
Nx155.52 Mbit/s
2. How many bytes are transmitted in a STM-1 signal?
2430
3. What are the three main blocks of the STM-1 signal?
SOH Pointer Payload
4. List the line codes used for SDH optical and electrical line signals?
CMI (electrical)
NRZ (optical)
5. What is the main function of scrambler?
Generation of a bit sequence with balanced number of 0 and 1 to ensure clock

recovery on the receiving end.
6. Which part of the STM-N is not scrambled?
The first 9 x n bytes of the STM-N signal.

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Chapter 3: Basic Elements of STM-1
Chapter 3 Basic Elements of STM-1
Aim of study
This chapter introduces elements of an STM-1 signal.
Contents Pages
1 Elements of an STM-1 Signal 2
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Chapter 3
Basic Elements of STM-1
1 Elements of an STM-1 Signal
1.1 Terminologies
Before discussing the basic elements of an STM frame, we will look at the
terminology used.
The suffixes used throughout the SDH multiplex levels derive from the older
PDH multiplex orders.
For instance
PDH Multiplex Order SDH suffix used
First Order of Multiplexing (2 Mbit/s) XX 1x (e.g. VC 12)
Second Order of Multiplexing (6 Mbit/s) XX 2 (e.g. TU 2)
Third Order of Multiplexing (34 Mbit/s) XX 3 (e.g. TUG 3)
Fourth Order of Multiplexing (140 Mbit/s) XX 4 (e.g. VC 4)
The above terms will be described in detail later in this section. Note,
however, that the First Order of multiplexing has two sub divisions, one for 2
Mbit/s PDH signals, e.g. VC 12, and one for 1.5 Mbit/s PDH signals e.g. VC
11. The other Orders of multiplexing have only one designation.
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1.2 Container C
Prior to its transmission in the STM-1 frame, every piece of tributary

information, whether plesiochronous or synchronous, is interleaved in
containers (fig. 1).
The term container C describes a defined network-synchronized transmission

capacity. The container size is given in bytes. This byte total is provided every
125 µs as container transmission capacity. The defined container sizes are
tailored to the current plesiochronous signals.
The following containers are distinguished:
Designation Signal to be transmitted

C-11 1 544 kbit/s
C-12 2 048 kbit/s
C-2 6 312 kbit/s
C-3 44 736 kbit/s
or 34 368 kbit/s
C-4 139 264 kbit/s
The tributary information must be fitted into these containers. This is done
with bit-by-bit and byte-by-byte justification for plesiochronous signals, by
means of purely positive justification as well as negative/zero/justification.
The container includes:
1. Pure tributary information (e.g. PDH signal).
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2. Fixed justification bytes and bits (fixed stuffing) for approximate timing
alignment. These bytes (or bits) are always without information content and
are used to approximately match the bit rate of the PDH signal to the
basically higher container bit rate. The precise bit rate alignment which
follows are performed with single justification opportunity bits.
3. Justification opportunity bits for precise timing alignment. These bits can be
used as tributary bits or justification bits as required.
4. Justification control bits to notify the receiver whether the justification
opportunity bits is an information bit or a justification bit.
1.3 Virtual Container VC
A path overhead (POH) is added to each container C. Together with its

associated POH, the container C is designated a virtual container VC and
routed as a non-modified entity via a through-connected path in the network.
The POH carries supplementary information ensuring the reliable transport of

the container from signal source to destination. It is added at the start of the
path when the VC is set up and first interpreted, and at the end of the path
when the container is cleared down. The POH includes information on the
supervision and maintenance of a path switched in the network.
Depending on its size, one virtual container can either be transmitted alone in
the STM-1 frame or otherwise interleaved in a larger VC, which is directly
transported in the STM-1.
A distinction is made between higher-order virtual containers (HO) and lower-

order containers (LO).
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All containers transmitted in one „larger“container are termed LO containers.

LO VC describes VC-11, VC-12, and VC-2. VC-3 is described as a LO VC if
transmitted in a VC-4.
Those containers transmitted directly in the STM-1 frame are termed HO

containers. VC-4 is a HO VC. The same designation applies to a directly
transmitted VC-3.
1.4 Administrative Unit AU
The higher-order virtual containers VC-4 and VC-3 are transmitted directly in
the STM-1 frame.
In this case the pointers (AU-PTR block) embedded in the STM-1 frame
record the phase relationship between the frame and the respective virtual
container. That component of the STM-1 frame within which the VC is able to
„float“ is termed administrative unit (AU). The corresponding pointer,
described as AU pointer, likewise counts as part of the AU. Three 3-byte AU
pointers are included in the first 9 bytes of the 4th row of the STM-1 frame. A
distinction is made between the AU-4 and AU-3.
It is possible to transmit the following AU in the STM-1 frame:
either 1 x AU-4 or
3 x AU-3. ( This has not been implemented by ETSI)
Transmission of the VC-3 is possible either
1. Directly (AU-3) in the STM-1 (not the ETSI recommendation).

2. Indirectly via an AU-4, where 3 x VC-3 are interleaved in one VC-4 (This
is the ETSI recommendation, and it is how our equipment maps the VC
signal).
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1.5 Administrative Unit Group AUG
Several AU are byte-interleaved, i.e. multiplexed byte-by-byte, to one AU

group (AUG). The AUG is a frame-synchronized structure corresponding to
the STM-1 without SOH. If the STM-1 SOH is added to the AUG, an STM-1
is produced.
An AUG can be composed either of 1 x AU-4 or 3 x AU-3.
1.6 Tributary Unit TU
With the exception of the VC-4, all VC can be interleaved in a larger VC and
transported in the STM-1. The „smaller“VC can generally float in phase terms
inside the „larger“(higher-order) VC. For this purpose a pointer establishing
the phase relationship between the two VC must be positioned at a fixed
location in the higher order VC. Tributary unit TU is the term used to describe
the component of the higher order container inside which the embedded LO
VC can vary plus the corresponding pointer (TU pointer).
The following TU are distinguished: TU-11, TU-12, TU-2, TU-3.
1.7 Tributary Unit Group TUG
Before being interleaved in the higher-order container, the TU are combined

in one group, i.e. byte-interleaved. Such a group is termed a TUG (tributary
unit group).
The following TUG has been defined: TUG-2 and TUG-3.
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Fig. 1 Container sizes and bit rates
Fig. 2 Synchronous digital hierarchy
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Chapter 4: Mapping
Chapter 4 Mapping
Aim of study
This chapter introduces mapping of 140 Mbit/s signal, 34 Mbit/s signal, 2 Mbit/s signal &
ATM cells.
Contents Pages
1 Mapping of a 140 Mbit/s Signal into the STM-1 2

2 Mapping of a 34 Mbit/s Signal to the Container C-3 9
3 Mapping of a 2 Mbit/s Signal to STM-1 17
4 Mapping of ATM Cells into the STM-1 30
5 Concatenation of Payloads 41
6 Summary 46
7 Exercise 49
8 Solution 50
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Chapter 4
Mapping
1 Mapping of a 140 Mbit/s Signal into the STM-1
Fig. 1
1.1 "Mapping" of a 140 Mbit/s Signal to the Container C-4
Prior to its transmission in the STM-1 frame, the 140 Mbit/s PDH signal is
interleaved into a container C-4. The position of the signal bits in the container
is exactly defined. The term "mapping" describes this fixed bit arrangement.
The size of the container C-4 amounts to 2340 byte. For a better
understanding, a two-dimensional representation of the container is shown
below (9 x 260):
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A C-4 is provided as network-synchronous transmission capacity every 125

µs.
A comparison of the number of possible, usable bits per container C-4
260 byte x 9 = 2340 byte x 8 = 18720 bit
Fig. 2
And the number of bits (nominal bit rate: 139,264 Mbit) actually to be
transmitted per container
139,264 Mbit/s: 8000 Hz = 17408 bit,
Reveals an over-capacity of the C-4.
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Chapter 4: Mapping
Fig. 3
Beside the pure tributary information bits (140 Mbit/s) the following bits are
transmitted in the container C-4:
• Fixed justification bits and bytes (approximate clock alignment.

• Justification opportunity bits (positive justification for precise clock
alignment).
• Justification control bits (justification information bits).
• Overhead bits (no function specified) 140 Mbit/s in C-4.
The 140-Mbit/s
Plesiochronous signal is aligned to the C-4 container bit rate through bit-by-bit
positive justification. 1 justification opportunity bit and 5 justification control
bits are provided per container row. The exact mapping of these bits in the
container is shown in fig. 5.
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Fig. 4 Plesiochronous 139,264-kbit/s signal in VC-4 VC-4 block structure
Fig. 5 Plesiochronous 139,264 k-bit/s signal in VC-4 1 VC-4 row
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Chapter 4: Mapping
The C-4 container has a total transmission capacity of 260 x 9 x 8 bits/125 s.

A capacity of 2080 bits is available per container row.
The 140-Mbit/s signal has a nominal bit rate of 139.264 Mbit/s, corresponding
to 17408 bit/125 µs. This, results in 1934.222 bits per signal container row.
The C-4 container provides 1934 I-bits and 1 stuffable bit per row for
transmission of this useful information. Each row further contains 5 stuff
check bits as well as overhead and fixed stuff bits and bytes respectively.
1.2 Interleaving of the C-4 into the STM-1
In order to transmit the container C-4 in the STM-1, container-specific

supplementing must be effected:
1. Addition of the Path OverHead (POH)
The VC-4 includes a "Path OverHead" (POH) with a size of 9 byte.
Fig. 6
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Additional Information about Path:
The route which a container and its overhead take through the SDH network is
also called "path".
The path is defined by the operator. At the beginning of the path, every
container is assigned a trace, which can be checked at the end of the path.
The block resulting from the container C-4 and the POH is called
Virtual Container 4 = VC-4.
Fig. 7
2. Addition of the Pointer (PTR)
There is a floating embedding of the Virtual Container VC-4 into the STM-1
frame of the payload. Part of the Virtual Container VC-4 is transmitted in one
STM-1 frame, and another part in the next frame.
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Chapter 4: Mapping
Fig. 8
The Pointer (PTR) indicates the start of the Virtual Container (VC-4) in the
payload.
That component of the STM-1, inside which the

VC-4 is able to "float" and which is made up of
PTR and payload, is designated
Administrated Unit 4 = AU-4
The AU-4 Pointer is abbreviated AU-4 PTR.
3. Addition of the Section OverHead (SOH)
In order to complete the STM-1 frame, the Section OverHead (SOH) is

added to the AU-4.
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2 Mapping of a 34 Mbit/s Signal to the Container C-3
2.1 3 x 34 Mbit/s -> STM-1
Fig. 9
interleaved into a container C-3 (=Mapping).
The size of the container C-3 amounts to 756 byte. For a better understanding,
a two-dimensional representation of the container is shown below (9 x 84):
A C-3 is provided as network-synchronous transmission capacity every 125

µs.
9 byte x 84 =756 byte x 8 = 6048 bit
And the number of bits (nominal bit rate: 34,368 Mbit/s) actually to be
transmitted per container
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Chapter 4: Mapping
34,368 Mbit/s: 8000 Hz = 4296 bit
Reveals an over-capacity of the container C-3!
Fig. 10
The reason for the over-capacity is a recommendation by ITU-T specifying

that the transmission of a 44, 736 Mbit/s signal (ANSI) must also be carried
out in the container C-3.
= 44, 736 Mbit/s: 8000 Hz = 5593 bit.
Fig. 11
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When considering the number of payload bits per STM-1 frame
9 byte x 261 x 8 = 18720 bit,
it emerges that only three C-3 (3 x 6048 bit) at maximum can be transmitted
per STM-1 frame => this means only 3 x 34 Mbit/s instead of the 4 x 34
Mbit/s which can be transmitted in a 140 Mbit/s PDH signal.
Beside the pure tributary information bits (34 Mbit/s)! the following bits are
transmitted in the container C-3:
• Fixed justification bits and bytes (approximate clock alignment).

• Justification opportunity bits (positive/negative justification for precise
clock alignment).
• Justification control bits (indicate whether there is a positive, negative, or
no justification).
• Overhead bits (no function specified).
34 Mbit/s in C-3
The positive/zero/negative justification method is used for transmission of the

34 Mbit/s plesiochronous signal in the C-3 container. For this purpose 2
justification opportunity bits within 3 container rows are provided (fig. 13).
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Fig. 12 Plesiochronous 34,368 kbit/s signal in VC-3 Block structure
Fig. 13 Plesiochronous 34,368-kbit/s signal in VC-3 3 rows of the VC-3
Three C-3 container rows at a time provide 2016 bits for transmission. These
bits comprise 1431 I-bits, 2 justification opportunity bits, 2 x 5 justification
control bits as well as overhead and fixed stuff bits. The 34 Mbit/s signal has a
nominal bit rate of 34,368 Mbit/s.
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1432 bits must thus be transmitted per 3 C-3 container rows. The 1431 I-bits
in the container are used up by the incoming signal at the nominal bit rate.
One justification opportunity bit must permanently be used as an I-bit. One
justification opportunity bit is transmitted as a justification bit (without
information).
However, if the bit rate of the incoming signal is below the nominal value, the
second s-bit (an I-bit in the nominal case) must also be stuffed if necessary
(positive justification).
If the bit rate of the incoming signal exceeds the nominal value, the first S-bit
(a justification bit in the nominal case) is used as an I-bit if required (negative
justification).
2.2 Interleaving of Three C-3 into the VC-4
The transmission of three C-3 in the STM-1 requires some container-specific

supplementing to be effected for every C-3.
Fig. 14
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2.3 Creation of the Tributary Unit 3 (TU3)
Every C-3 receives a "Path OverHead" (POH) with a size of 9 byte. The block
resulting from the C-3 and POH is termed Virtual Container-3 = VC-3.
Every Virtual Container VC-3 (=LOWER ORDER VC) is assigned a 3-byte

Pointer PTR, which allows the VC-3 to float. The area in which the VC-3 can
float with the aid of the Pointer PTR is called Tributary Unit 3 = TU-3. The
3-byte pointer in the TU-3 is called TU-3 Pointer. The PTR contains an
address which indicates the start of the VC-3 in the TU-3.
Fig. 15
2.4 Creation of the Tributary Unit Group 3 (TUG-3)
A Tributary Unit TU-3 is always supplemented with six fixed justification

bytes which do not contain any information. The block resulting from the
TU-3 and the fixed justification bytes is called Tributary Unit Group 3 =
TUG-3.
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Fig. 16
2.5 Interleaving of TUG-3 into VC-4
The three resulting TUG-3 (#1, #2 and #3) are byte-interleaved into a Virtual
Container VC-4 (=HIGHER ORDER VC ).
To adjust the three byte-interleaved TUG-3 to the VC-4 it is necessary to add

two columns of fixed justification bytes.
Fig. 17
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2.6 Interleaving of the VC-4 into the STM-1
The Virtual Container VC-4 is transmitted directly in the STM-1 frame

(Payload).
In this case, the pointer (PTR) embedded in the STM-1 frame contains an
address indicating the beginning of the VC-4 in the payload.
That component of the STM-1, inside which the VC-4 can "float" and which
comprises the two blocks PTR and Payload is designated.
Administrative Unit 4 = AU-4.
In the AU-4, the pointer is abbreviated AU-4 PTR.
Fig. 18
To supplement the STM-1 frame, the Section OverHead (SOH) is added to the
AU-4.
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Fig. 19
3 Mapping of a 2 Mbit/s Signal to STM-1
Fig. 20
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3.1 "Mapping" of a 2 Mbit/s Signal to the Container C-12
interleaved into a container C-12 (=Mapping).
The size of the container C-12 amounts to 34 byte. For a better understanding,
you can find a two-dimensional representation of the container below:
Fig. 21
= 34 byte x 8 = 272 bit
And the number of bits (nominal bit rate: 2,048 Mbit/s) actually to be
transported per container
2,048 Mbit/s: 8000 Hz = 256 bit,
Reveals an over-capacity of the container C-12.
Beside the pure tributary information bits (2 Mbit/s),
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Chapter 4: Mapping
The following bits are transmitted in the container C-12:
• Fixed justification bits and bytes (approximate clock alignment).

• Justification opportunity bits (positive/negative justification for precise
clock alignment).
• Justification control bits (indicates whether there is a positive, negative or
no justification).
• Overhead bits (no function specified).
Fig. 22
3.2 Creating a VC-12 Frame
In order to transmit 63 containers C-12 (with an own 2 Mbit/s signal in each

case) in the STM-1 frame, container-specific supplementing is necessary for
every C-12.
A "Path OverHead" (POH) with the size of 1 byte is added to every C-12.
The function of these bytes will be explained in chapter 6.
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Chapter 4: Mapping
A VC-12 is provided as network-synchronous transmission capacity every 125 µs.
Fig. 23
3.3 Creating the Tributary Unit TU-12
Fig. 24
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3.4 Creation of the Tributary Unit Group TUG-2
Three TU-12 (= 3 x 2 Mbit/s signals) from different multiframe TU-12 are

multiplexed byte-by-byte to form a "Tributary Unit Group-2" (TUG-2).
For a better understanding, again a two-dimensional representation of a TU-12

partial fame will be shown.
Fig. 25
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Chapter 4: Mapping
3.5 Creation of a Tributary Unit Group TUG-3
In a next step, seven TUG-2 (=21 x 2 Mbit/s signals) are combined to form a
TUG-3, i.e. byte-interleaved.
Fig. 26
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Chapter 4: Mapping
3.6 Interleaving of TUG-3 into a Virtual Container VC-4
The three resulting TUG-3 (#1 #2 and #3) are byte-interleaved into a Virtual
Container VC-4 (=HIGHER ORDER VC).
Fig. 27
3.7 Interleaving of the VC-4 into the STM-1
The Virtual Container VC-4 is transmitted directly in the STM-1 frame

(Payload).
In this case, the pointer (PTR) embedded in the STM-1 frame contains an
address indicating the beginning of the VC-4 in the payload.
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Chapter 4: Mapping
Fig. 28
That component of the STM-1, inside which the VC-4 can "float" and which
comprises the two blocks PTR and Payload is designated.
Administrative Unit 4 = AU-4.
In the AU-4, the pointer is abbreviated AU-4 PTR.
To supplement the STM-1 frame, the Section OverHead (SOH) is added to the
AU-4.
Fig. 29
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Chapter 4: Mapping
3.8 Creation of a VC-12 Multiframe
In order to transmit 63 containers C-12 (with an own 2 Mbit/s signal in each

case) in the STM-1 frame, container-specific supplementing is necessary for
every C-12.
A "Path OverHead" (POH) with the size of 1 byte is added to every C-12.
The function of these bytes will be explained in chapter 6.
There can be four different POH bytes for one C-12:
Caution: A multiframe VC-12 is transmitted via four or five STM-1 frames!
Fig. 30
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Fig. 31 Plesiochronous 2Mbit/s mapping
When a byte-synchronous 2Mbit/s signal is transmitted, the individual 64-

kbit/s channels occupy exactly one byte for each channel in the STM 1 frame.
Hence after the interpretation of the individual pointer levels, it is possible to
access a 64-kbit/s directly, irrespective of the transmission mode. However,
two pointers must be evaluated the AU and the TU pointers.
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Fig. 32
3.9 Numbering of TU-12s in a VC 4
Each TUG-2 can comprise three TU-12s which shall be numbered #1 to #3(#K).
Thus any TU-12 can be allocated a two-figure address in the form #L, #M,
where L designates the TUG-2 number (1 to 7) and M designates the TU-12
number (1 to 3).
Thus TU-12 #1 (1, 1) resides in columns 10, 73, 136 and 199 of the VC-4, and
TU-12 #2(7, 3) resides in columns 71, 134, 197 and 260 of the VC-4. A full
listing of the location of the TU-12 columns with the VC-4 frame follows.
NOTE – The Time Slot number contained in the diagrams below should
not be interpreted as the tributary port number, as the time slots and port
numbers are independent from each other. It is only during configuration
of the equipment that port is assigned a time slot.
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An external tributary signal may be assigned to a particular payload capacity

using a connection function.
For example at the VC-12 level,
– Tributary #1 – TU-12 (1, 1, 1)

– Tributary #2 – TU-12 (1, 1, 2)
– Tributary #3 – TU-12 (1, 1, 3)
– Tributary #4 – TU-12 (1, 2, 1)
•
– Tributary #63 – TU-12 (3, 7, 3)
Fig. 33
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Fig. 34
3.10 Creating Tributary Units
That component, inside which the multiframe VC-12 can "float" with the aid
of a pointer, is termed multiframe TU-12. The four pointer bytes also count
as part of the multiframe TU-12. Every 125 µs one pointer byte is transmitted,
i.e. the transmission of the complete pointer takes 500 µs.
Three TU-12 (= 3 x 2 Mbit/s signals) from different multiframe TU-12 are

multiplexed byte-by-byte to form a "Tributary Unit Group-2" (TUG-2).
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In a next step, seven TUG-2 (=21 x 2 Mbit/s signals) are combined to form a
TUG-3, i.e. byte-interleaved.
The three resulting TUG-3 (#1 #2 and #3) are byte-interleaved into a Virtual
Container VC-4 (=HIGHER ORDER VC ) and so on (see 3.6).
Fig. 35
4 Mapping of ATM Cells into the STM-1
ATM Cells -> STM-1
Fig. 36
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Basic Structure and Contents of an ATM Cell
To account for the rapidly increasing need for broadband services and
applications (e.g. video conferences, multimedia etc.), the pieces of
information are no longer transported and switched through via channels with
a defined structure, but in the form of short packets with a constant length (=
Asynchronous Transfer Mode - cells).
Fig. 37
The tributary information, which normally comes in continuously:
• constant bit rates 64 kbit/s

2 Mbit/s
34 Mbit/s
• data packets
• variable bit rates
Is written into the PAYLOAD bit by bit and supplemented by the HEADER.
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Fig. 38
4.1 ATM Characteristics
Until now „synchronous time-division multiplex methods“ (cf. narrowband

ISDN) or packet-oriented multiplex methods (e.g. in conformity with X.25)
were used to assign band width to the connections within the framework of the
existing transmission capacity.
Although the time-division multiplex method, also known as „asynchronous

transfer mode“(ATM), used in modern telephone networks is ideally suited for
signals with constant bit rates (e.g. PCM-coded speech), but not suited at all if
a variable band width is required.
On the other hand, the conventional handshaking packet-oriented methods

(X.25) are flexible in terms of the throughput per connection, but are
unsuitable for the communication of constant bit-rate signals because of the
propagation times (e.g. speech or video signals); furthermore, the conventional
protocols are designed only for bit rates up to approx. 2 Mbit/s.
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Therefore, a new approach was made with B-ISDN known as the

„asynchronous transfer mode (ATM) “. This mode is a packet-oriented, non-
handshaking multiplex mode. The ATM principle is bit-rate-independent and
may basically be employed for any digital transmission path which is
sufficiently free of errors.
The ATM method is so simple that the user packets can be conveyed purely
by hardware (table-controlled) after a software-controlled call setup and not
by slow software as in current packet networks. This makes ATM as efficient
as the STM method and far superior to conventional packet-oriented methods
(e.g. X.25).
Current international standards envisage the transport bit rates 155 and 622
Mbit/s for ATM. Due to these high rates and the hardware-controlled
switching, the delay times (otherwise typical for packet methods) are
significantly reduced. Thus ATM seems suitable for all information types:
both for fixed and variable bit rate signals and for packet-oriented signals.
However the flexibility of ATM is balanced by increased complexity. Thanks

to advances in modern microtechnology, however, system costs do not
increase in line with module complexity (gateway total). Otherwise, ATM
would stand no chance when competing with the more inflexible and hence
less complex STM.
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Fig. 39
With ATM, fixed-length packets known as „cells“are continuously transmitted

in every transmission section.
These cells consist of 48 octets for payload and a 5-octet cell head. If no
payload is to be transmitted, specially labeled blank cells are sent.
ATM allows connections with any net bit rate. The latter is very low if almost
no information cells are being sent, but approaches the transport bit rate
(approx. 130 Mbit/s for 155-Mbit/s transport bit rate) if information cells are
being sent almost exclusively. By a label in the cell head each cell is assigned
to a specific virtual transmission path (short form: path) and to a (virtual)
channel routed in this path. This principle allows the capacity of the
transmission sections in the entire ATM network to be flexibly allocated to
narrowband and broadband connections in any desired combination.
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The ATM network functions trunk-oriented, i.e. it retains the cell sequence for
every connection. When the connection is set up the network user notifies the
network of the desired bit rate via a (virtual) signaling channel; the network
subsequently reserves the appropriate band width on all transmission paths.
Should a user exceed the agreed bit rate on a connection, the network detects
this at the network input and takes precautions against possible overload, e.g.
by ignoring excess cells.
With ATM, a very simple protocol is used. The protocol works without
acknowledgements, flow control or error correction. This results in a rapid,
service-independent basis switching service. Further performance features can
be added, if necessary, in more advanced protocol levels. Section-by-section
error correction can be omitted due to the high quality of the digital and
optical transmission techniques employed in the network.
Correspondingly, the structure of the cell head is simple fig. 1 shows the cell
structure defined by CCITT for the user-network interface. The essential
elements in the cell head are the "virtual path identifier" (VPI; 8 bits) and the
"virtual channel identifier" (VCI; 16 bits). Together VIP and VCI provide for
the unambiguous assignment of a cell to a virtual connection on a section-by-
section basis.
The field "payload type" (PLT: 3 bits) is used to differentiate useful cells and
blank cells. The field "cell loss priority" (CLP: 1 bit) is used to differentiate
the cells the loss of which is more or less acceptable. The field "header error
control" (HEC: 8 bits) is used to protect the cell head against transmission
errors. Finally, the field "generic flow control" (GFC: 4 bits) is only relevant
in the subscriber area and is discussed for flow control in the case of multiple
access of terminal equipment in the subscriber area.
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Chapter 4: Mapping
This field is not significant network-internally; its place in the cell head is
therefore used network-internally to extend the virtual path identifier (to 12
bits).
Like all packet-oriented methods ATM has several peculiarities when

compared to STM. Apart from the conventional bit errors in the information,
entire cells can be lost in ATM. However, the probability that this actually
happens is low (e.g. 10-8). Possible causes are, for example, incorrigible
errors in the cell head or overflow of network-internal queues which have to
be established at every multiplex point in the network due to the statistical
multiplex principle.
Further peculiarities relate to the runtime. The procedure used means that in
an ATM network the end-to-end runtime for cells will be lower than in a
narrowband ISDN. A considerable "packeting time" may arise for filling the
ATM cells, however, particularly with lower bit rates. This packeting time
arises whenever the information appears at the source as continuous signal (as
is the case with most computer applications) rather than in packet form. The
packeting time for PCM-coded speech (64 kbit/s) is as much as 6 ms. Thanks
to the low runtime in the ATM network, this delay hardly disturbs speech
quality as long as no additional packeting procedures arise through transitions
to STM networks. Special measures such as the use of echo suppressor
equipment, guarantee the standard high speech quality in such cases.
Finally, unlike in STM, statistical runtime fluctuations (delay jitter) arise in

ATM due to the intra-network queues. In the case of continuous signals (e.g.
speech) the receiver must balance fluctuations through an anticipated delay.
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4.2 Transmission of ATM Cells in SDH
Fig. 40
4.3 "Mapping" of ATM Cells to the Container C-4
Prior to their transmission in the STM-1 frame, the ATM cells are interleaved
into the container C-4 (= Mapping).
Fig. 41
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Fig. 42
A C-4 is provided every 125 µs as network-synchronous transmission

capacity.
A comparison between the number of possible, usable bits per container C-4
260 byte x 9 = 2340 byte
and the number of ATM cells to be transmitted per C-4
2340 byte: 53 byte = 44,15
reveals that an ATM cell can also be transmitted via two C-4.
4.4 Interleaving the C-4 into the STM-1
In order to transmit the container C-4 in the STM-1, container-specific

supplementing is necessary:
1) The C-4 receives a "Path OverHead" (POH) with a size of 9 byte.
The block resulting from the C-4 and POH is called Virtual Container-4 = VC-4.
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Fig. 43
2) There is a "floating" embedding of the Virtual Container VC-4 to the

STM-1frame of the payload. Part of the VC-4 is transmitted in one STM-1
frame, and another part in the next frame.
The pointer indicates the start of the Virtual Containers (VC-4) in the
payload.
NOTE where there is a need to carry an ATM signal greater than

140Mbit/s such as a 600Mbit/s, then it is carried in an STM 4 frame as
shown below. This signal has its 1st VC 4 with a normal AU4 pointer, and
the other 3 AU4's have concatenated pointers.
Fig. 44
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That component of the STM-1, inside which a VC-4 is able to "float" and
which consists of the blocks PTR and payload, is termed Administrative Unit
4 = AU-4.
In the AU-4 there is an AU-4 Pointer abbreviated by AU-4 PTR.
Fig. 45
3) To complete the STM-1 or STM 4 frame, the Section OverHead (SOH)

is added to the AU-4.
Fig. 46
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5 Concatenation of Payloads
5.1 Introduction
There is an increasing need to have ultra high capacity interfaces which

require several 155Mbit/s channels in today's Data applications.
Therefore if we can transmit data in one channel rather than several individual
channels, then we would have better utilization of the available channel
bandwidth. This would also prove to be a much less expensive solution for our
customers.
These large channels are called "Clear Channels". Concatenation is the merger
of multiple channels (say 155Mbit/s) into one large Clear Channel.
There are TWO distinct methods of CONCATENATION
1. CONTIGUOUS CONCATENATION.
2. VIRTUAL CONCATENATION.
An example of where this feature is used is when there is a requirement to
carry IP packets over the SDH network.
This is a detailed subject which is not covered in this course.
For further reading, an introduction, in the form of a tutorial, can be found in

the Appendix of this training manual. Please take some time later to read this
as it gives good background information on this topic.
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5.2 Contiguous Concatenation of Payloads
To illustrate the form of concatenation we will use the concatenation of VC4's

initially, then describe the TU 2's AU4's can be concatenated to form and AU4
Xc which can transport payloads requiring greater than one Container 4
capacity.
The concatenation indication is used so that the multi container VC4 Xc

payload should be kept together, and is part of the VC 4 pointer. The X
indicates the number of VC 4 concatenated, e.g. VC 4 4c means 4 VC 4
concatenated i.e. capacity of 599.040 Mbit/s.
The first AU 4 of an AU4 Xc has the normal range of pointer values. All
subsequent AU 4 within the AU4 Xc will have their pointer set to
Concatenation Indication (CI) "1001" in bits 1 to 4, with bits 5 & 6
unspecified, and the 10 bit decimal pointer values will have all 1's.
The CI indicates that the pointer processors will perform the same operations
as performed on the first AU4 of the AU4 Xc.
Recommendation G707 also describes the contiguous concatenation of TU 2

in VC3. The term VC 2mc is used where "m" indicates the number of
concatenated Tu 2's carried.
The first TU 2 of an TU 2mc has the normal range of pointer values. All
subsequent Tu 2's within the TU 2 mc will have their pointer set to
Concatenation Indication (CI) "1001" in bits 1 to 4, with bits 5 & 6
unspecified, and the 10 bit decimal pointer values will have all 1's.
The CI indicates that the pointer processors will perform the same operations
as performed on the first TU2 of the TU 2mc.
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5.3 Virtual Concatenation of Payloads
The standard G707 describes the use of Virtual Concatenation of TU 2

payloads only. The Virtual Concatenation of VC 4 payloads is understudy,
however, it is expected that the process will remain the same.
This method of concatenation has been initially developed for the transport of
a single VC 2 mc, m times TU 2 without the use of CI of the pointer bytes.
This method only requires the path termination equipment to provide
concatenation functions.
Virtual Concatenation requires that all TU signals to be concatenated at the

origin of the path are to have the same pointer value. These TU's are then
carried in one VC4. When the VC4 is then terminated, all the concatenated
TU's must be passed unaltered from one interface to another and remain
within the VC4 with their time sequence unchanged.
With Virtual Concatenation the available capacity is lower than that for a
Contiguous Concatenation, therefore, care should be taken to base the required
capacity of VC 2mc's to the lower value to allowed the interconnections of
both types of concatenation. The reasons for this is because Virtual
concatenations need a separate POH for every VC 2 whereas contiguous
concatenation only requires a POH for the first VC signal. Byte stuffing
techniques are used to fill up the spare capacity in the Contiguously
concatenated TU 2mc.
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Chapter 4: Mapping
Fig. 47 Two methods of concatenation
Fig. 48
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Chapter 4: Mapping
Fig. 49
The diagram above shows the following:
1. The normal multiplex structure that has been already introduced.

2. The STM 0 multiplex structure are used Radio Relay products, such as:
• SRT1S.
• SRA1S.
3. The concatenated multiplex structure, also it can be seen that an STM

4/16/64/256 can carry both concatenated and non-concatenated signals.
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Chapter 4: Mapping
6 Summary
In the SDH, containers with a fixed transmission capacity are provided every
125 µs.
Fig. 50
Container-Terminology (140 Mbit/s/ATM Cells)
The incorporation of the 140 Mbits/s signals/ATM cells into the STM-1 is
performed as follows:
Fig. 51
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Chapter 4: Mapping
Container-Terminology (34 Mbit/s)
The interleaving of the three 34 Mbits/s signals into the STM-1 looks like this:
Fig. 52
Container-Terminology (2 Mbit/s)
The interleaving of the 63 x 2 Mbit/s signals to the STM-1 looks like this:
Fig. 53
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Chapter 4: Mapping
The following PDH signals can be transmitted in a VC-4.
Fig. 54
Synchronous Digital Hierarchy accord. to ETSI
Fig. 55
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Chapter 4: Mapping
7 Exercise
Fill in the missing components of the STM-1 signal in order to complete the
mapping function.
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Chapter 4: Mapping
8 Solution
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Chapter 5: Pointer
Chapter 5 Pointer
Aim of study
This chapter introduces pointer functions, types and structure, pointer addressing scheme
and pointer justification.
Contents Pages
1 Pointer Functions 2
2 Pointer Types 3
3 Pointer Structure 6
4 Pointer Addressing Scheme 9
5 Pointer Justification 11
6 Exercise 15
7 Solution 16
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Chapter 5: Pointer
Chapter 5
Pointer
1 Pointer Functions
The pointer is used for synchronization of tributaries and the higher-order

frame. Packed in the virtual container, the tributary signal can be transmitted
with a phase decoupled from that of the frame. The phase relationship
between frame and virtual container is recorded in the pointer bytes. The
pointer bytes are embedded in the frame at a fixed position and contain the
address of the first byte of the VC (1st POH byte) in the frame.
The pointer technique allows the tributary signals, which are packed in VC, to
be inserted in the higher-order frame without elaborate and time-consuming
buffering. Any phase and bit rate fluctuation can be compensated through
pointer value alignment together with byte-by-byte positive, zero and negative
justification.
Access to the higher-order virtual container (HO VC) is possible immediately

after evaluation of the AU pointer. A further pointer must be interpreted
before access to LO VC is possible.
The pointer allows single user channels to be dropped from and added to the
overall signal without the signal having to be demultiplexed completely.
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Chapter 5: Pointer
2 Pointer Types
3 types of pointer can be distinguished:
a) AU pointer.
b) TU-3 pointer.
c) TU-1/TU-2 pointer.
The contents of H1 and H2 are as follow:
• Pointer value (address of container POH).

• New data flag.
• Justification opportunity digits.
• AU3/AU4/TU3-type.
H3 contains:
Pointer action byte
(for transmission of information with negative justification method)
Example of (a) and (b) type of pointers
Fig. 1 Basic structure of AU-x/TU-3 pointer

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Chapter 5: Pointer
Example of (c) type of pointer
Fig. 2 Basic structure of TU-1x/2 pointer
General pointer structure:
Fig. 3 General pointer structure
Concatenation Indication (CI):
Application: A broadband signal divided into several subsignals is

transmitted in one STM-N.
In this case the standard pointer is set in STM-1 #1, while

CI is set in STM-1 #2. Thus, the phase relationship
between both STM-1 remains locked.
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Chapter 5: Pointer
Fig. 4 Concatenation indication pointer structure
2.1 AU Pointer
The following AU pointer exists:
• AU-4 pointer.
• AU-3 pointer.
AU-x (x = 3, 4) pointer allow the phase and frequency adaptation of the VC-x
to a particular AU-x frame. This corresponds to a direct alignment of the
payload (VC) to the section overhead (SOH).
The following containers can be directly transported in the STM-1 frame:
1 x VC-4 (1 x 140 Mbit/s) by means of one AU-4 pointer.
3 x VC-3 (3 x 45 Mbit/s) by means of 3 AU-3 pointers.
2.2 TU-3 Pointer
The VC-3 containers can also be transported indirectly via a VC-4 container in
the STM-1 frame.
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Chapter 5: Pointer
For indirect transmission, the VC-3 containers are initially aligned to the VC-4
frame by means of the TU-3 pointers; the VC-4 container is subsequently
aligned to the STM-1 frame with the AU-4 pointer.
3 x VC-3 can be carried in the VC-4 with 3 TU-3 pointers.
2.3 TU-12 Pointer
TU-12 pointer allows the VC-12 to be aligned in phase and frequency to the
higher-order frame (VC-3 or VC-4).
The VC-12 is transported in a multiframe, with merely one TU-12 pointer

byte being transmitted per 125 µs subframe. After three 125 µs subframes, the
transmission of the 3 pointer bytes is completed and the fourth subframe
carries a pointer reserve byte.
For transmission of the TU-12, several TU are combined in a group (tributary

unit group TUG) and the respective TUG are subsequently transferred to a
VC-4 or VC-3 container.
3 Pointer Structure
Fig. 5 AU-4 pointer

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Chapter 5: Pointer
Fig. 6 TU-3 pointer
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Chapter 5: Pointer
Fig. 7 H1, H2, H3 bytes as used in the AU-4/TU-3 pointer structure
Fig. 8
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Chapter 5: Pointer
Fig. 9 TU-12 pointer structure
4 Pointer Addressing Scheme
Fig. 10 AU-4 pointer offset numbering
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Chapter 5: Pointer
Fig. 11 TU-3 pointer addressing scheme
Fig. 12 TU-12 pointer offset numbering
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Chapter 5: Pointer
5 Pointer Justification
When existing virtual containers are inserted into a higher-order frame, it is

possible to adjust phase and bit rate fluctuations by means of byte-by-byte
positive/zero/negative justification. This is necessary for example if several
STM-1 signals which are not network-synchronized meet at the network node.
If several STM-1 are multiplexed to a STM-N, for example, the higher-order
VC contained in the STM-1 are adapted to the STM-N frame.
Zero Justification:
If the VC to be inserted and the higher-order frame are in synchronism, no

justification is required. The phase difference (recorded in pointer value)
between frame and start of VC remains unchanged. This is termed zero
justification.
Positive Justification:
If the VC bit rate is too low compared to the frame transmission capacity, - i.e.
the available transmission capacity is higher than the one effectively required -
3 justification bytes (without information content) are, if required transmitted
instead of 3 VC information bytes at a defined position in the frame in order to
align the bit rates.
This corresponds to a positive justification operation. The start of the VC (1st

byte of POH) is consequently delayed in time by 3 bytes in relation to the
frame. This operation delays the start of the VC concerned by 3 bytes in time
and the pointer value must be incremented by 1.
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Chapter 5: Pointer
Negative Justification:
If to the VC bit rate is too high compared to the frame transmission capacity -
i.e. the transmission capacity is inadequate - supplementary capacity must be
provided in the frame if required. This is accomplished by the transfer of 3
bytes of the VC content to the pointer action bytes. The phase difference
between frame and VC is thus decreased by 3 bytes and accordingly the
pointer value must be decremented by 1.
Pointer corrections are only permitted in every fourth frame, i.e. at least 3
consecutive frames with unchanged pointers must exist between 2 pointer
corrections.
Fig. 13 AU-4 positive pointer justification

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Chapter 5: Pointer
Fig. 14 AU-4 negative pointer justification, standard case
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Chapter 5: Pointer
5.1 Pointers and Signal Labels
Fig. 15
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Chapter 5: Pointer
6 Exercise
1. What is the function of a pointer?
2. Which pointer exists in ETSI?
3. Which pointer value range exists for the AU-4 pointer and which bytes can
be addressed?
4. How is positive/zero/negative justification performed if the bit rate to be

transmitted is?
Identical with the transmission capacity?

Higher than the transmission capacity?
Lower than the transmission capacity?
5. What is the value of an AU-4 pointer originally set to 782 after positive
justification?
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Chapter 5: Pointer
7 Solution
1. What is the function of a pointer?
The pointer indicates the address of the first POH bytes of the VC and thus
the location of the VC within the frame. It therefore serves to synchronize
payload information which can be accessed directly.
2. Which pointer exists in ETSI?
Pointer of the SDH: AU-4, TU-12, TU-3.
3. Which pointer value range exists for the AU-4 pointer and which bytes
can be addressed?
Value range 0 - 782 decimal; only every third byte can be accessed.
4. How is positive/zero/negative justification performed if the bit rate to

be transmitted is?
Identical with the transmission capacity? Zero justification

Higher than the transmission capacity? Negative justification
Lower than the transmission capacity? Positive justification
5. What is the value of an AU-4 pointer originally set to 782 after positive
justification?
To 0 (zero)
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Chapter 6: Overhead
Chapter 6 Overhead
Aim of study
This chapter introduces overhead functions & Section Overhead (SOH).
Contents Pages
1 Overhead Functions 2
2 Section Overhead (SOH) 3
3 Exercise 25
4 Solution 26
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Chapter 6: Overhead
Chapter 6
Overhead
1 Overhead Functions
The functions of the overhead channels include:
• Frame formation.
• Status monitoring.
• Error monitoring.
• Error localization.
• Maintenance functions.
• Control functions.
The structure of the STM-1 or STM-N frame is such that the overhead is
always an entity separate form the useful information. The advantage of this
arrangement is that the individual overhead bytes can be interrogated, changed
or added at any time without the individual signal first having to be
demultiplexed.
A distinction is made between the section overhead (SOH) and path overhead
(POH).
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Chapter 6: Overhead
Fig. 1 Affected area of overhead function
2 Section Overhead (SOH)
2.1 Basic Information
Fig. 2 STM-1 frame structure
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Chapter 6: Overhead
The SOH block is composed of eight 9-column rows. The first 9 bytes of rows
1-3 respectively contain the RSOH (regenerator section overhead), while the
first 9 bytes of rows 5-9 contain the MSOH (multiplex section overhead). The
first 9 bytes of the 4th row are used by the AU pointers and are not a
component of the SOH.
2.2 Regenerator Section Overhead
Fig. 3 SOH structure of STM-1 highlighting the regenerator section overhead
2.2.1 Byte Description
A1 and A2 Framing bytes – These two byte types indicate the beginning of
the STM-N frame. The A1, A2 bytes are unscrambled. A1 has the binary
value 11110110, and A2 has the binary value 00101000. The frame alignment
word of an STM-N frame is composed of (3 x N) A1 bytes followed by
(3 x N) A2 bytes.
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Chapter 6: Overhead
J0 Regenerator Section (RS) Trace message – It’s used to transmit a Section

Access Point Identifier so that a section receiver can verify its continued
connection to the intended transmitter. The coding of the J0 byte is the same
as for J1 and J2 bytes in the path overheads. This byte is defined only for
STM-1 number 1 of an STM-N signal.
Z0 - These bytes, which are located at positions S[1,6N+2] to S[1,7N] of an

STM-N signal (N > 1), are reserved for future international standardization.
B1 RS bit interleaved parity code (BIP-8) byte – This is a parity code (even
parity), used to check for transmission errors over a regenerator section. Its
value is calculated over all bits of the previous STM-N frame after
scrambling, then placed in the B1 byte of STM-1 before scrambling.
Therefore, this byte is defined only for STM- 1 number 1 of an STM-N signal.
E1 RS orderwire byte – This byte is allocated to be used as a local orderwire

channel for voice communication between regenerators.
F1 RS user channel byte – This byte is set aside for the user’s purposes; it
can be read and/or written to at each section terminating equipment in that
line.
D1, D2, D3 RS Data Communications Channel (DCC) bytes – These three

bytes form a 192 kbit/s message channel providing a message-based channel
for Operations, Administration and Maintenance (OAM) between pieces of
section terminating equipment. The channel can be used from a central
location for control, monitoring, administration, and other communication
needs.
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Chapter 6: Overhead
DCC-channels
Fig. 4 Principle use of DCCM and DCCR channels
2.3 Multiplex Section Overhead
Fig. 5 Multiplex section overhead bytes
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Chapter 6: Overhead
2.3.1 Byte Description
B2 Multiplex Section (MS) bit interleaved parity code (MS BIP-24) byte –
This bit interleaved parity N x 24 code is used to determine if a transmission
error has occurred over a multiplex section. It’s even parity, and is calculated
overall bits of the MS Overhead and the STM-N frame of the previous STM-
N frame before scrambling. The value is placed in the three B2 bytes of the
MS Overhead before scrambling. These bytes are provided for all STM-1
signals in an STM-N signal.
K1 and K2 Automatic Protection Switching (APS channel) bytes – These

two bytes are used for MSP (Multiplex Section Protection) signaling between
multiplex level entities for bi-directional automatic protection switching and
for communicating Alarm Indication Signal (AIS) and Remote Defect
Indication (RDI) conditions. The Multiplex Section Remote Defect Indication
(MS-RDI) is used to return an indication to the transmit end that the received
end has detected an incoming section defect or is receiving MS-AIS. MS-RDI
is generated by inserting a “110” code in positions 6, 7, and 8 of the K2 byte
before scrambling.
See Appendix for more details of the K1 and K2 bytes.
D4 to D12 MS Data Communications Channel (DCC) bytes – These nine

bytes form a 576 kbit/s message channel from a central location for OAM
information (control, maintenance, remote provisioning, monitoring,
administration and other communication needs).
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Chapter 6: Overhead
S1 Synchronization status message byte (SSMB) – Bits 5 to 8 of this S1

byte are used to carry the synchronization messages. Following is the
assignment of bit patterns to the four synchronization levels agreed to within
ITU-T (other values are reserved):
Bits 5-8
0000 Quality unknown (existing sync. network)
0010 G.811 PRC
0100 SSU-A (G.812 transit)
1000 SSU-B (G.812 local)
1011 G.813 Option 1 Synchronous Equipment Timing Clock (SEC)
1111 Do not use for synchronization. This message may be emulated by

equipment failures and will be emulated by a Multiplex Section AIS signal.
M1 MS remote error indication – The M1 byte of an STM-1 or the first

STM-1 of an STM-N is used for a MS layer remote error indication (MS-
REI). Bits 2 to 8 of the M1 byte are used to carry the error count of the
interleaved bit blocks that the MS BIP- 24xN has detected to be in error at the
far end of the section. This value is truncated at 255 for STM-N >4.
E2 MS orderwire byte – This orderwire byte provides a 64 kbit/s channel

between multiplex entities for an express orderwire. It’s a voice channel for
use by craftspersons and can be accessed at multiplex.
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Chapter 6: Overhead
Fig. 6 STM-4 frame
Fig. 7 STM-16 frame
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Chapter 6: Overhead
2.4 Forward Error Correction FEC
Forward Error Correction (FEC) has been developed to improve the

transmission quality, by reducing the bit error rate. This is achieved by
correcting bit errors produced during optical to electrical conversion at the
receive side of the transmission path. Conversely, improvements can also be
used to reduce the necessary optical power required at the transmitter, thus
allowing a longer transmission path for the same primary bit error rate.
There are two types of FEC:
• Inband FEC.
• Outband FEC.
Inband FEC makes use of the spare bytes to be found in the Section Overhead
of the STM-4, 16, 64, 256. The previous figure of the STM-16 frame shows
the bytes reserved for this function.
Outband FEC uses an extra Overhead. This produces a higher improvement of

the Bit Error Rate; however, the signal bit rate will need to increase. This
method will probably not be used, however.
Currently FEC is not finalized by a specific standard. G707 standard has

allocated bytes and is under study (as at Jan 2001), therefore, Siemens are
currently using a proprietary version in their SLD 16 version 2.5 equipment,
until such time as the standard has been finalized.
On the transmit side the STM-4 part signal is put through an arithmetic-logic
unit which calculates the FEC Parity bytes from the 4 STM-1's signals.
These calculated parity FEC parity bytes are then inserted into the SOH of the
STM- 1 signals # 2, 3 and 4 (STM-1 # 1 is not used to carry FEC signals).
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Chapter 6: Overhead
On the receive side of the STM-4 part signal, the signal is delayed and put
through an arithmetic-logic unit which calculates the correction information
by means of the received STM-4 part signal and the received FEC parity
bytes. This correction information is then used to correct the delayed STM-4
signal. A similar process is also used for the STM-16, STM-64, and STM-256
line rates.
This feature will be described in more detail during specific product training,
in products which supports this feature.
Some examples of improvements of BER and power gains by using FEC are:
Thus you may improve your BERPRIM to BERFEC for the same distance, or
for the same BERPRIM have more power to go an increased distance.
2.5 VC-3 and VC-4 Path Overhead (POH)
Basic Information
The POH is added to the container C. Both form together the virtual container
VC which is carried as unchanged entity in the network path. The POH
contains all information required for reliable transportation of the container.
Information about the status of the entire path can be obtained by evaluating
the POH data. Fig. 1 shows the scope of validity of the POH.
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Chapter 6: Overhead
Description of VC-3/VC-4 POH bytes
VC-3, VC-4 POH
Fig. 8 VC-3, VC-4 path overhead
Byte Description
J1 Higher-Order VC-N path trace byte – This user-programmable byte

repetitively transmits a 15-byte, E.64 format string plus 1-byte CRC-7. A 64-
byte free-format string is also permitted for this Access Point Identifier. This
allows the receiving terminal in a path to verify its continued connection to the
intended transmitting terminal.
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Chapter 6: Overhead
B3 Path bit interleaved parity code (Path BIP-8) byte – This is a parity
code (even), used to determine if a transmission error has occurred over a
path. Its value is calculated over all the bits of the previous virtual container
before scrambling and placed in the B3 byte of the current frame.
C2 Path signal label byte – This byte specifies the mapping type in the VC-
N. Standard binary values for C2 are:
MSB LSB Hex Code Interpretation
Bits 1-4 Bits 5-8
0000 0000 (00) Unequipped or supervisory-unequipped
0000 0001 (01) Equipped – non-specific
0000 0010 (02) TUG structure
0000 0011 (03) Locked TU-n
0000 0100 (04) Asynchronous mapping of 34,368 kbit/s or 44,736 kbit/s into
the Container-3
0001 0010 (12) Asynchronous mapping of 139,264 kbit/s into the Container-4
0001 0011 (13) ATM mapping
0001 0100 (14) MAN DQDB (IEEE Standard 802.6) mapping
0001 0101 (15) FDDI (ISO Standard 9314) mapping
0001 0110 (16) Mapping of HDLC/PPP (Internet Standard 51) framed signal
0001 0111 (17) Mapping of Simple Data Link (SDL) with SDH self
synchronizing scrambler
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Chapter 6: Overhead
0001 1000 (18) Mapping of HDLC/LAP-S framed signals
0001 1001 (19) Mapping of Simple Data Link (SDL) with set-reset scrambler
0001 1010 (1A) Mapping of 10 Gbit/s Ethernet frames (IEEE 802.3)
1100 1111 (CF) Obsolete mapping of HDLC/PPP framed signal
1110 0001 (E1) Reserved for national use
1111 1100 (FC) Reserved for national use
1111 1110 (FE) Test signal, O.181 specific mapping
1111 1111 (FF) VC-AIS
G1 Path status byte – This byte is used to convey the path terminating status
and performance back to the originating path terminating equipment.
Therefore the bidirectional path in its entirety can be monitored, from either
end of the path. Byte G1 is allocated to convey back to a VC-4-Xc/VC-4/VC-
3 trail termination source the status and performance of the complete trail. Bits
5 to 7 may be used to provide an enhanced remote defect indication with
additional differentiation between the payload defect (PLM), server defects
(AIS, LOP) and connectivity defects (TIM, UNEQ). The following codes are
used:
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Chapter 6: Overhead
Fig. 9 G1 byte "Path Status"
F2 Path user channel byte – This byte is used for user communication
between path elements.
H4 Position and Sequence Indicator byte – This byte provides a multi frame
and sequence indicator for virtual VC-3/4 concatenation and a generalized
position indicator for payloads. In the latter case, the content is payload
specific (e.g., H4 can be used as a multiframe indicator for VC-2/1 payload).
For mapping of DQDB in VC- 4, the H4 byte carries the slot boundary
information and the Link Status Signal (LSS). Bits 1-2 are used for the LSS
code as described in IEEE Standard 802.6. Bits 3-8 form the slot offset
indicator. The slot offset indicator contains a binary number indicating the
offset in octets between the H4 octet and the first slot boundary following the
H4 octet. The valid range of the slot offset indicator value is 0 to 52. A
received value of 53 to 63 corresponds to an error condition.
F3 Path user channel byte – This byte is allocated for communication

purposes between path elements and is payload dependent.
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Chapter 6: Overhead
K3 APS signaling is provided in K3 bits 1-4, allocated for protection at the

VC-4/3 path levels. K3 bits 5-8 are allocated for future use. These bits have no
defined value. The receiver is required to ignore their content.
N1 Network operator byte – This byte is allocated to provide a Higher-Order

Tandem Connection Monitoring (HO-TCM) function. N1 is allocated for
Tandem Connection Monitoring for contiguous concatenated VC-4, the VC-4
and VC-3 levels. Bits 1-4 Incoming Error Count (IEC).
1001 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1110 Incoming AIS
NOTE: To guarantee a non all-zeroes N1 byte independent of the incoming
signal status, it is required that the IEC code field contains at least one “1”.
When zero errors in the BIP-8 of the incoming signal are detected, an IEC
code is inserted with “1”s in it. In this manner, it is possible for the Tandem
Connection sink at the tail end of the Tandem Connection link to use the IEC
code field to distinguish between unequipped conditions started within or
before the Tandem Connection. Bit 5 Operates as the TC-REI of the Tandem
Connection to indicate errored blocks caused within the Tandem Connection.
Bit 6 Operates as the OEI to indicate errored blocks of the egression VC-n.
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Bits 7-8 Operate in a 76 multiframe as:
• Access point identifier of the Tandem Connection (TC-APId); it complies

with the generic 16-byte string format.
• TC-RDI, indicating to the far end that defects have been detected within
the Tandem Connection at the near end Tandem Connection sink.
• ODI, indicating to the far end that AU/TU-AIS has been inserted into the
egression AU-n/TU-n at the TC-sink due to defects before
or within the Tandem Connection.
• Reserved capacity (for future standardization).
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2.6 Low Order Path Multiframe
Fig. 10 Example for 500-_s multiframe of a TU-1/2 multiframe indicator using H4 bytes
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2.7 VC-12 Path Overhead (POH)
Basic Information
In floating mode transmission of VC-12 four bytes (V5, J2, Z6, Z7) per 500 _s
are provided as POH.
Fig. 11 Path overhead of the VC-12
Description of the V5 byte
The V5 byte fulfills the following functions:
• Bit error monitoring.

• Signal labeling.
• VC-12 path status indication.
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Fig. 12 V5 byte of VC-12
Byte Description
V5 VT path overhead byte.
Bits 1-2
Allocated for error performance monitoring. A Bit Interleaved Parity (BIP-2)

scheme is specified. Includes POH bytes, but excludes V1, V2, V3, and V4.
Bit 3
A VC-2/VC-1 path Remote Error Indication (LP-REI) that is set to one and
sent back towards a VC-2/VC-1 path originator if one or more errors were
detected by the BIP- 2; otherwise set to zero.
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Bit 4
A VC-2/VC-1 path Remote Failure Indication (LP-RFI). This bit is set to one
if a failure is declared, otherwise it is set to zero. A failure is a defect that
persists beyond the maximum time allocated to the transmission system
protection mechanisms.
Bits 5-7
Provide a VC-2/VC-1 signal label. The Virtual Container path Signal Label
coding is:
000 Unequipped or supervisory-unequipped
001 Equipped – non-specific
010 Asynchronous
011 Bit synchronous
100 Byte synchronous
101 Reserved for future use
110 Test signal, O.181 specific mapping
111 VC-AIS
Bit 8
Set to 1 to indicate a VC-2/VC-1 path Remote Defect Indication (LP-RDI);

otherwise set to zero.
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Path Trace J2
Byte J2 is used to transmit repetitively a Low Order Path Access Point

Identifier so that a path receiving terminal can verify its continued connection
to the intended transmitter. This Path Access Point Identifier uses the format
defined in clause 3/G831. A 16-byte frame is defined for the transmission of
Path Access Point Identifiers.
Network Operator Byte: N2
This byte is allocated to provide a Tandem Connection Monitoring (TCM)

function.
Fig. 13 N2 byte of a VC-12
Bits 1-2 Used as an even BIP-2 for the Tandem Connection.
Bit 3 Fixed to “1”. This guarantees that the contents of N2 is not all zeroes at
the TCsource. This enables the detection of an unequipped or supervisory
unequipped signal at the Tandem Connection sink without the need of
monitoring further OHbytes.
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Bit 4 Operates as an “incoming AIS” indicator.
Bit 5 Operates as the TC-REI of the Tandem Connection to indicate errored

blocks caused within the Tandem Connection.
Bit 6 Operates as the OEI to indicate errored blocks of the egression VC-n.
Bits 7-8 Operate in a 76 multiframe as:
• The access point identifier of the Tandem Connection (TC-APId); it

complies with the generic 16-byte string format.
• The TC-RDI, indicating to the far end that defects have been detected
within the Tandem Connection at the near end Tandem Connection sink.
• The ODI, indicating to the far end that TU-AIS has been inserted at the
TC-sink into the egression TU-n due to defects before or within the
Tandem Connection.
• Reserved capacity (for future standardization).
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Chapter 6: Overhead
Automatic Protection Switching (APS) channel: K4 (b1-b4)
These bits are allocated for APS signaling for protection at the lower order
path level.
Reserved: K4 (b5-b7)
Bit 5 to 7 of K4 are reserved for an optional use. If this option is not used,
these bits shall be set to "000" or "111". A receiver is required to be able to
ignore the contents. The use of the optional function is at the discretion of the
owner of the trail termination source generating the K4-byte.
Spare: K4 (b8)
This bit is allocated for future use. This bit has no defined value. The receiver
is required.
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Chapter 6: Overhead
3 Exercises
1. What is the function of the bytes A1, A2?
2. What is the function of the byte B1 and in which type of network elements
(multiplexer, regenerator) is it evaluated?
3. What is the function of the bytes B2 and in which type of network elements
(multiplexer, regenerator) is it evaluated?
4. Which byte and bits are used to transmit the signal multiplex section remote
defect indication?
5. Which byte is used for path trace?
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Chapter 6: Overhead
4 Solution
1. What is the function of the bytes A1, A2?
Framing
2. What is the function of the byte B1 and in which type of network

elements (multiplexer, regenerator) is it evaluated?
Error monitoring on regenerator sections
Multiplexer
Regenerator
3. What is the function of the bytes B2 and in which type of network

elements (multiplexer, regenerator) is it evaluated?
Error monitoring on multiplexer sections
Only multiplexer
4. Which byte and bits are used to transmit the signal multiplex section
remote defect indication?
Byte K2, bit 6, 7, 8
5. Which byte is used for path trace?
J1
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Chapter 7: Monitoring, Maintenance and Control in the SDH
Chapter 7 Monitoring, Maintenance and Control

in the SDH
Aim of study
This chapter introduces alarm interactions overview, bit error monitoring and AIS.
Contents Pages
1 Alarm Interactions Overview 2

2 Bit Error Monitoring 5
3 Error Reports REI, RDI 16
4 AIS 18
5 Examples 19
6 Exercises 32
7 Solution 33
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Chapter 7
Monitoring, Maintenance and Control in the SDH
1 Alarm Interactions Overview
With the help of the overhead data bytes, we can send forward and backward
from the reporting network element certain alarm conditions. This information
helps to localize the fault as quickly as possible.
Using a process of prioritization, and elimination, we can determine where the

fault is, what is possibly causing it and what needs to be done to fix it.
The following diagram attempts to show the Alarms raised, their subsequent
actions, destinations in the forward and backward directions.
The following description should help to read the diagram:
(J0), (C2), (H4) etc are bytes to be found in the RSOH, MSOH, POH High
and low order.
Description
• The line shows the direction the Alarm is sent, with a description of the
alarm event for example Loss of Signal, or Loss of frame.
• The following show all the alarms that cause the forwarding onwards or
backwards of the next alarm indication as required.
• The alarm names indicate the alarms that all cause the subsequent alarm
indication and the "1" indicates the contents of the STM frame contains all
"1"s in the AU4.
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Fig. 1
Fig. 2
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1.1 Abbreviations
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2 Bit Error Monitoring
Specific bytes in the individual overheads are provided for bit error
monitoring and fault localization. These bytes contain information indicating
the bit error rate and thus the quality of the transmission sections concerned.
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Fig. 3
2.1 Operational Principle
Fig. 4 Bit error monitoring
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On the transmit side, an n-bit code word is generated over a bit stream of
specific length in conformity with a fixed code protocol. This code word is
carried supplementary to the useful information in the overhead.
The bit stream is coded according to the same rules on the receive side and a
code word is regenerated. The new code word is compared with the
transmitted one. Any discrepancy between the code words indicates bit errors
in transmission. The precise number of bit errors is not determined with this
audit. However, a statistical evaluation of the incorrect code words allows
conclusion to be drawn about the transmission bit error rate.
2.2 BIP-n Code
Fig. 5 Bit-interleaved parity (BIP-n)
A special parity code known as the BIP-n code is provided for bit error
monitoring in the synchronous hierarchy.
BIP-n: bit interleaved parity n

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BIP-n code generation:
Here the bit stream of the multiplex unit under test (e.g. STM-N, VC) must be
envisaged as divided into sequences n bits in length.
Parity is now generated over the first bit of each sequence respectively and
even parity is produced at the end of the multiplex unit being tested. The even-
parity bit corresponds to the 1st bit of the n-bit long code word.
To „produce even parity“means that there must be an even total (including the
parity bits in the code word) of „1s“in the particular bit stream must exist.
The same procedure is applied to the 2nd bit in each sequence with the result
that the 2nd bit of the code word is generated. This continues in the same
manner until all n-bits are generated. The n-bit long code word is then inserted
and carried in the appropriate overhead.
2.3 Monitoring Sections
Fig. 6 Monitoring sections
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Different BIP-N code words are used to monitor individual route sections in
the synchronous hierarchy:
Regenerator Section: B1 in RSOH
One BIP-8 code word (1 byte) is provided for bit error monitoring. This code
word is generated over all bits in the STM-N frame after scrambling. The BIP-
8 byte is subsequently inserted in the allocated position B1 of the RSOH in the
next frame before scrambling starts. This byte is evaluated and regenerated in
every multiplexer and regenerator.
Fig. 7 B1, B2 generation
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Multiplexer Section: B2 in the MSOH
A BIP-N x 24 code word (N x 3 bytes) is provided for error monitoring on the

individual multiplexer sections. This BIP-N x 24 code cord is generated prior
to scrambling over the entire STM-N frame, but not on the first 3 rows of the
SOH. The N x 3-byte BIP-N24 x 24 code word is inserted prior to scrambling
in the N x 3 bytes B2 provided for this purpose in the MSOH of the next
frame. These B2 bytes are not modified in the regenerator.
VC-4 and VC-3 Path: B3 in the POH
A B3 byte is provided for error monitoring of the individual VC-3 and VC-4
transmission paths. One BIP-989 (1 byte) code word is generated over the
entire bit stream of the virtual container and inserted in the appropriate byte
B3 of the POH of the follow-on VC. The B3 code word is generated over the
entire VC bit stream including the POH but without pointers. In the case of
negative justification it must be noted that the pointer action byte contains
useful information of the VC and is therefore incorporated in the B3
generation.
VC-2 and VC-1 Path: Bit 1 and 2 in the V5 POH
The first 2 bits in the POH byte V5 of the respective VC are provided for bit
error monitoring of the individual VC-1 and VC-2 transmission paths. A BIP-
2 (2 bits) code word is generated over the entire VC block in the 500 _s
multiframe and inserted in the first two bit positions of the POH (V5) of the
next VC.
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2.4 Tandem Connection Monitoring
2.4.1 Where do the Errors come from?
End-to-end quality is monitored by checking BIP parity. This gives an

indication of whether errors have been generated somewhere in the entire
path.
It is not possible to determine in which part of the path the error occurred.
If a sub-network provider is present (provider 2), there will always be disputes

over who produced the errors on the way through the network.
An additional possibility allowing sub-network providers to demonstrate the

quality of their networks from the point of receiving to the point of
transmitting the signal from their network limits was therefore looked for.
Fig. 8
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2.4.2 Principle of Tandem Connection Monitoring
"Tandem Connection Monitoring" was introduced for this reason.
The principle is very simple:
The incoming and outgoing data streams (SINK and SOURCE) are each
monitored at the network limits.
This allows network provider 2 to monitor own errors in the path layer
independently of any received errors.
Fig. 9
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2.4.3 Check TCM Sub-Layer
Path parity errors are checked at the input to the sub-network. If errors are
present, they are copied into N1/N2 bytes in the POH. The data now passes
through the sub-network.
At the far end of the sub-network a check is made again: Path parity errors are
checked and compared with the extracted N1/N2 bytes.
If there is a difference, the sub-network produced additional errors. Otherwise,

provider 1 is responsible for the errors.
Fig. 10
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2.4.4 Alarm and Error Handling with TCM
In addition to error monitoring, alarms are also signaled in the backward

direction in the same way as in the VCn layer. This allows monitoring of the
entire TCM systems in the forward and backward directions.
The following events are used to signal alarms:
SOURCE:
• Invalid VC-n? --> Insert AIS

• BIP errors detected? --> Insert errors in IEC (incoming error count)
• Alarms received from SINK --> TC-RDI : Remote Defect Indication
--> TC-REI: Remote Error Indication
--> ODI: Outgoing Defect Indication
--> OEI: Outgoing Error Indication
SINK:
• TC alarms detected? --> TC-RDI

• AIS detected? --> ODI
• BIP errors detected? --> Insert errors in OEI
• BIP = IEC? --> Insert difference in TC-REI
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Fig. 11
2.4.5 Interaction between Generation and Analysis of N1/N2
Detected B3 or BIP-2 errors are indicated in bytes N1/N2 of the sub-network.
In the USA, only N1 (Z5) is taken into consideration.
The right-hand figure shows the TCM sink and source functions. There is an
exchange of errors and alarms in the incoming and outgoing data signals.
N1/N2 produces a multiframe with 76 frames which allows transportation of

different alarms. N1 also transports the number of B3 errors counted, and N2
transports the value of BIP-2 errors.
Recommendations G.707 and G.783 cover SDH.
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T1.105 and T1.105.05 apply to SONET (Bellcore GR-253 only refers to the
ANSI recommendation).
Fig. 12
3 Error Reports REI, RDI
3.1 REI Remote Error Indication
a) Path REI
The POH of the individual virtual containers contain one byte (VC-3 and
VC-4) or 2 bits (VC-1 and VC-2) for bit error monitoring. As mentioned
previously the BIP-8 or BIP-2 codes are used respectively. If bit errors are
detected at the path end when the BIP end words are evaluated, a REI code is
inserted in the opposite direction (to the path start) in order to notify the
source of the detected failure.
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Bits 1-4 in POH byte G1 are used for REI transmission by VC-3 and VC-4.
The parity of 8 bit sequences is checked with the BIP-8 code employed.
Maximum 8 parity violations can thus be detected. The REI code contains the
total number of parity violations, with the values 0 to 8 being transmitted.
Should a different value appear in the REI code, however, it must be
interpreted as 0.
Bit 3 in POH byte V5 is used for REI transmission by VC-1 and VC-2. The bit
is set to 0 if no parity violation is detected with the BIP-2. A parity error is
indicated by the value 1.
b) Section REI
The M1 byte in the MSOH is used for relaying the number of parity violations
occurred in the B2 bytes to the far end side.
Depending on the multiplex signal (STM-N), the M1 REI code can have
values between 0 and N x 24.
3.2 RDI Remote Defect Indication
a) Path-RDI
If no valid signal or an AIS is present when the individual VCs are received,
the distant end is notified through the remote alarm.
This remote alarm is set to „1“in the event of a fault; in normal operation its
value is „0“.
The remote alarm is carried in POH byte G1 (bit 5) for VC-3 and VC-4.
For VC-1 and VC-2, the remote alarm is carried in POH byte V5 (bit 8).
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b) Section-RDI
If the STM-N multiplexer receives an AIS or no valid signal, it inserts the RDI
code in the opposite direction.
The RDI code (110) is inserted in byte K2 at bit positions 6-8.
4 AIS
AIS = alarm indication signal
a) Definition
If a device detects an error, e. g. no valid signal or loss of frame alignment, it

sends an alarm indication signal (AIS) in the ongoing direction in the same
manner as a normal signal is relayed by the follow-on equipment. The purpose
of this signal is to prevent the activation of alarms in the follow-on equipment.
The reception of an AIS signal triggers direct functions (such as channel
blocking) only in specific terminal equipment.
The AIS signal is an all-one-signal in the plesiochronous hierarchy. The frame

alignment signal and service word are likewise set to „1“, so that the frame
alignment signal is no longer detectable as such.
In the synchronous hierarchy, the STM-1 frame is fully retained even in the
event of an AIS. A distinction is made between the section AIS and the path
AIS.
b) Path AIS
Path AIS is set if a virtual container fails.
The entire TU-n (n = 1, 2, 3) including pointer is set to „1“ in the case of

a TU-path AIS.
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The entire AU-n (n = 3, 4) including pointer is set to „1“ in the case of

a AU-path AIS.
These permanent one signals are carried in the STM-1 as valid tributaries.
c) Section AIS
Section AIS is set if the entire STM-1 or STM-N has failed. It is indicated in
byte K2, of which bits 6, 7 and 8 are set to „1“.
5 Examples
Fig. 13
The three B1 are generated in the Regenerator Section, and monitor the STM –N
frame after scrambling. This B1, BIP 8 code is subsequently inserted in the B1
position of the RSOH in the next frame, before scrambling. this byte is then
evaluated and regenerated along the route at each Multiplexer and Regenerator.
Fig. 14
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The three B2 are generated prior to scrambling over the entire STM-1 in the
STM-N signal, but not on the first three rows of the SOH (=RSOH). The B2
monitor individual STM-1 signals on the multiplex section; they are only
generated (TRANSMITTER) and evaluated (RECEIVER) in MUX systems.
Fig. 15
The B3 is provided over the entire VC-4 / VC-3. It is generated at the

beginning of the path and evaluated at the end of the path.
5.1 Bit Error Monitoring Concept (Examples)
B1 - code errors are only indicated in those MUX/REG systems which are
contained in the faulty regenerator section.
B2 - code errors are only indicated in those MUX systems which are
contained in the faulty multiplex section.
B3 - code errors are indicated in those MUX systems, in which a VC-4/VC-3

is evaluated (access to PDH signals).
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Fig. 16
Example 1
Fig. 17
Example 2
Fig. 18
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Example 3
Fig. 19
Example 4
Fig. 20
Example 5
Fig. 21
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5.2 Error and Failure Reports
Error report "REI" (Remote Error Indication):
REI is sent in the backward direction, if there are code errors (bit errors) in
the incoming signal of the local receiver (MUX).
Fig. 22
There are two types of REI:
Path REI
Path REI if a code error was determined in the B3 byte.
Fig. 23
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Section REI
Section REI if a code error was determined in the B2 byte.
Fig. 24
Example REI
Fig. 25
Since MUX 2 detects a bit error rate SD in bytes B2 and B3, there is an error
report due to which Path REI and Section REI is indicated in MUX1.
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Failure Report "RDI" (Remote Defect Indication
RDI is reported in the backward direction in the case of urgent line alarms.
Fig. 26
A distinction is made between:
PATH RDI SECTION RDI
Bit 5 of the G1 byte in VC4 POH is Bits 6, 7 and 8 of the K2 byte in

set to "1". MSOH are set to "110".
B3 SD B2 LOS
AIS in VC-4 SECTION AIS
no signal in the VC-4 loss of STM-N signal
wrong path trace in the J1 byte loss of frame alignment
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Example RDI
Fig. 27
Since MUX 2 detected a LOS or SD in the B2 byte and, implicitly in the B3

byte, a RDI (Section + Path) report is sent to the MUX 1.
5.3 Alarm Indication Signal "AIS"
AIS is sent to the forward direction, if urgent line alarms were detected in the
MUX/REG.
Fig. 28
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There are two types of AIS:
Path AIS
e.g. with VC-4 the entire AU-4 including the pointer is set to "1".
Section AIS
Fig. 29 Path AIS
Fig. 30 Section AIS
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Bits 6, 7 and 8 of the K2 in the MSOH are set to "111".
AIS is sent in the forward direction if the following conditions were detected
in the MUX/REG:
PATH AIS SECTION AIS
B3 SD section AIS already received

(in regenerators)
NO signal in the VC – 4 NO signal in the STM – N

(in regenerators)
Wrong path trace J1 byte loss of STM-N signal

(in regenerators)
Path AIS already received internal functional disturbances

in the MUX/REG systems
Example Path AIS
A cable break in the regenerator by the alarm "Loss of Signal" (LOS).
The regenerator cannot re-generate the STM-4 signal and sends

"Section AIS".
The MUX 2 transmits all-one-signals in channels 1, 2 and 3. The PDH

devices interpret these signals as AIS.
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Fig. 31
MUX 2 sends Path AIS (Pointer + VC-4 = "1") in channel #4.
The last SDH MUX (MUX 3) also sends AIS to the PDH device.
Error reports are issued in the backward direction, too, of course.
MUX 2 sends Section RDI and Path RDI for paths #1, #2 and #3 to MUX 1.
MUX 3 sends Path FERF for channel #4 , which is switched through until the
end of the path (MUX1).
5.4 Summary
Bit Error Monitoring
In order to monitor an STM-N signal, the "Bit Interleaved Parity" (BIP)

procedure is used.
• B1 (BIP8) = monitoring of the entire STM - N signals on

regenerator sections.
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• B2 (BIP N x 24) = monitoring of an STM - 1 signal in an

STM - N on multiplex sections.
• B3 (BIP 8) = monitoring VC-4/VC-3 on path sections.
Error Report REI Remote Error Indication (previously called FEBE Far
End Block Error)
• Section REI is sent in the backward direction of the STM-N

signal, if a code error was detected via the B2
bytes.
• Path REI is sent in the backward direction of the path

if a code error was detected via the B3 byte.
Failure Report RDI Remote Defect Indication (previously called FERF

Far End Receive Fail)
• Section RDI is sent in the backward direction of the respective STM-N in

the following cases:
- -> Section AIS was received

- -> no signal (loss of STM-N)
- -> loss of frame alignment
• Path RDI is sent in the backward direction of the respective path in the
following cases:
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- -> Path AIS in the VC

- -> no signal in the VC
- -> wrong path trace in the VC POH
AIS Alarm Indication Signal
• Section AIS is sent by the regenerators in the on-going direction in the

following cases:
- -> Section AIS was received

- -> no signal (loss of STM-N)
- -> loss of frame alignment
- -> internal functional disturbances (of the MUX, too)
• Path AIS is sent by MUX in the on-going direction of a path in the

following cases:
- -> SD
- -> no signal in the VC
- -> wrong path trace in the VC POH
- -> Path AIS already received in the path
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6 Exercises
1. Which method is used for bit error monitoring?
2. Which byte is used to monitor the regenerator section with BIP?
3. Which byte is used to monitor the multiplex section with BIP?
4. Which byte is used to monitor the VC4 and VC3 path with BIP?
5. Which byte and bits are used to monitor the VC12 path with BIP?
6. List the indications for remote alarms.
7. List the types of AIS in the synchronous hierarchy.
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7 Solution
1. Which method is used for bit error monitoring?
Bit-interleaved parity
2. Which byte is used to monitor the regenerator section with BIP?
B1
3. Which byte is used to monitor the multiplex section with BIP?
B2
4. Which byte is used to monitor the VC4 and VC3 path with BIP?
B3
5. Which byte and bits are used to monitor the VC12 path with BIP?
V5, bits 1 and 2
6. List the indications for remote alarms.
Remote error indication REI
Remote defect indication RDI
7. List the types of AIS in the synchronous hierarchy.
Path AIS
Section AIS
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Chapter 8: Appendix
Chapter 8 Appendix
Aim of study
This chapter introduces ITU-T Recommendation list, multiplex section overhead bytes K1
& K2, SONET and IP over SDH.
Contents Pages
1 ITU-T Recommendation List 2

2 Multiplex Section Overhead bytes K1 & K2 6
3 SONET 7
4 IP over SDH 10
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Chapter 8: Appendix
Chapter 8
Appendix
1 ITU-T Recommendation List
A Selection of ITU-T Recommendations has been given below as a guide for

further reading:
• Recommendation G.652 (10/00) - Characteristics of a single-mode optical

fiber cable - To be published
• Recommendation G.653 (10/00) - Characteristics of a dispersion-shifted
single-mode optical fiber cable- To be published
• Recommendation G.654 (10/00) - Characteristics of a cut-off shifted
single-mode optical fiber cable - To be published
• Recommendation G.655 (10/96) - Characteristics of a non-zero dispersion
shifted single-mode optical fiber cable - To be published
• Recommendation G.662 (10/98) - Generic characteristics of optical fibre
amplifier devices and subsystems
• Recommendation G.663 (04/00) - Application related aspects of optical
amplifier devices and subsystems - To be published
• Recommendation G.664 (06/99) - Optical safety procedures and
requirements for optical transport systems
• Recommendation G.671 (11/96) - Transmission characteristics of passive
optical components
• Recommendation G.681 (10/96) - Functional characteristics of interoffice
and long-haul line systems using optical amplifiers, including optical
multiplexing
• Recommendation G.691 (10/00) - Optical interfaces for single channel
STM-64, STM-256 systems and other SDH systems with optical
amplifiers - To be published
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Chapter 8: Appendix
• Recommendation G.692 (10/98) - Optical interfaces for multichannel

systems with optical amplifiers
• Recommendation G.701 (03/93) - Vocabulary of digital transmission and
multiplexing, and pulse code modulation (PCM) terms
• Recommendation G.702 (11/88) - Digital hierarchy bit rates
• Recommendation G.703 (10/98) - Physical/electrical characteristics of
hierarchical digital interfaces
• Recommendation G.704 (10/98) - Synchronous frame structures used at
1544, 6312, 2048, 8448 and 44 736 kbit/s hierarchical levels
• Recommendation G.705 (10/00) - Characteristics of Plesiochronous
Digital Hierarchy (PDH) equipment functional blocks - To be published
• Recommendation G.706 (04/91) - Frame alignment and cyclic
redundancy check (CRC) procedures relating to basic frame structures
defined in G 704
• Recommendation G.707/Y.1322 (10/00) - Network node interface for the
synchronous digital hierarchy (SDH) - To be published
• Recommendation G.708 (06/99) - Sub STM-0 network node interface for
the synchronous digital hierarchy (SDH)
• Recommendation G.711 (11/88) - Pulse code modulation (PCM) of voice
frequencies
• Recommendation G.732 (11/88) - Characteristics of primary PCM
multiplex equipment operating at 2048 kbit/s
• Recommendation G.736 (03/93) - Characteristics of a synchronous
digital multiplex equipment operating at 2048 kbit/s
• Recommendation G.773 (03/93) - Protocol suites for Q-interfaces for
management of transmission systems
• Recommendation G.774 (09/92) - Synchronous digital hierarchy (SDH)
management information model for the network element view
• Recommendation G.780 (06/99) - Vocabulary of terms for synchronous
digital hierarchy (SDH) networks and equipment
• Recommendation G.781 (06/99) - Synchronization layer functions
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Chapter 8: Appendix
• Recommendation G.783 (10/00) - Characteristics of synchronous digital

hierarchy (SDH) equipment functional blocks - To be published
• Recommendation G.784 (06/99) - Synchronous digital hierarchy (SDH)
management
• Recommendation G.801 (11/88) - Digital transmission models
• Recommendation G.803 (03/00) - Architecture of transport networks
based on the synchronous digital hierarchy (SDH) - To be published
• Recommendation G.804 (02/98) - ATM cell mapping into
plesiochronous digital hierarchy (PDH)
• Recommendation G.805 (03/00) - Generic functional architecture of
transport network To be published
• Recommendation G.806 (10/00) - Characteristics of transport equipment
- Description methodology and generic functionality - To be published
• Recommendation G.810 (08/96) - Definitions and terminology for
synchronization networks
• Recommendation G.811 (09/97) - Timing characteristics of primary
reference clocks
• Recommendation G.812 (06/98) - Timing requirements of slave clocks
suitable for use as node clocks in synchronization networks
• Recommendation G.813 (08/96) - Timing characteristics of SDH
equipment slave clocks (SEC)
• Recommendation G.821 (08/96) - Error performance of an international
digital connection operating at a bit rate below the primary rate and
forming part of an integrated services digital network
• Recommendation G.822 (11/88) - Controlled slip rate objectives on an
international digital connection
• Recommendation G.823 (03/00) - The control of jitter and wander within
digital networks which are based on the 2048 kbit/s hierarchy - To be
published
digital networks which are based on the 1544 kbit/s hierarchy - To be
published
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Chapter 8: Appendix

digital networks which are based on the synchronous digital hierarchy
(SDH) - To be published
• Recommendation G.826 (02/99) - Error performance parameters and
objectives for international, constant bit rate digital paths at or above the
primary rate
• Recommendation G.831 (03/00) - Management capabilities of transport
networks based on the synchronous digital hierarchy (SDH) - To be
published
• Recommendation G.832 (10/98) - Transport of SDH elements on PDH
networks - Frame and multiplexing structures
• Recommendation G.841 (10/98) - Types and characteristics of SDH
network protection architectures
• Recommendation G.842 (04/97) - Interworking of SDH network
protection architectures
• Recommendation G.852.1 (11/96) - Management of the transport
network - Enterprise viewpoint for simple sub network connection
management
• Recommendation G.853.1 (03/99) - Common elements of the
information viewpoint for the management of a transport network
• Recommendation G.853.2 (11/96) - Sub network connection
management information viewpoint
• Recommendation G.950 (11/88) - General considerations on digital line
systems
• Recommendation G.957 (06/99) - Optical interfaces for equipments and
systems relating to the synchronous digital hierarchy
• Recommendation G.958 (11/94) - Digital line systems based on the
synchronous digital hierarchy for use on optical fiber cables
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Chapter 8: Appendix
2 Multiplex Section Overhead bytes K1 & K2
2.1 K1 Byte
Bits 1-4 Type of request
1111 Lock out of Protection

1110 Forced Switch
1101 Signal Fail – High Priority
1100 Signal Fail – Low Priority
1011 Signal Degrade – High Priority
1010 Signal Degrade – Low Priority
1001 (not used)
1000 Manual Switch
0111 (not used)
0110 Wait-to-Restore
0101 (not used)
0100 Exercise
0011 (not used)
0010 Reverse Request
0001 Do Not Revert
0000 No Request
Bits 5-8 indicate the number of the channel requested
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Chapter 8: Appendix
2.2 K2 Byte
Bits 1-4 Selects channel number
Bit 5 Indication of architecture
0 1+1
1 1: n
Bits 6-8 Indicate mode of operation
111 MS-AIS
110 MS-RDI
101 Provisioned mode is bi-directional
100 Provisioned mode is unidirectional
011 Future use
010 Future use
001 Future use
000 Future use
3 SONET
3.1 Introduction
SONET (Synchronous Optical NETwork) is a standard for optical

telecommunications transport. It was formulated by the Exchange Carriers
Standards Association (ECSA) for the American National Standards Institute
(ANSI), which sets industry standards in the U.S. for telecommunications and
other industries.
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Chapter 8: Appendix
3.2 Background
Before SONET, the first generations of fiber optic systems in the public
telephone network used proprietary architectures, equipment, line codes,
multiplexing formats, and maintenance procedures. The users of this
equipment – Regional Bell Operating Companies and inter-exchange carriers
(IXCs) in the U.S., Canada, Korea, Taiwan, and Hong Kong – wanted
standards so they could mix and match equipment from different suppliers.
The task of creating such a standard was taken up in 1984 by the Exchange
Carriers Standards Association (ECSA) to establish a standard for connecting
one fiber system to another. This standard is called SONET for Synchronous
Optical NETwork.
3.3 Basic SONET Signal
SONET defines a technology for carrying many signals of different capacities

through a synchronous, flexible, optical hierarchy. This is accomplished by
means of a byte-interleaved multiplexing scheme. Byte-interleaving simplifies
multiplexing, and offers end-to-end network management. The first step in the
SONET multiplexing process involves the generation of the lowest level or
base signal. In SONET, this base signal is referred to as Synchronous
Transport Signal level-1, or simply STS-1, which operates at 51.84 Mb/s.
Higher-level signals are integer multiples of STS-1, creating the family of
STS-N signals. An STS-N signal is composed of N byte-interleaved STS-1
signals. The table includes the optical counter (carrier)-part for each STS-N
signal, designated OC-N (Optical Carrier level-N).
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Chapter 8: Appendix
3.3.1 SONET HIERARCHY
3.3.2 NON-SYNCHRONOUS HIERARCHY
3.4 STS Frame Structure
STS-1 is a specific sequence of 810 bytes (6480 bits), which includes various
overhead bytes and an envelope capacity for transporting payloads. It can be
depicted as a 90 column by 9 row structure. With a frame length of 125 µs
(8000 frames per second), STS-1 has a bit rate of 51.840 Mb/s. The order of
transmission of bytes is row-by-row from top to bottom, left to right (most
significant bit first). The first three columns of the STS-1 frame are for the
Transport Overhead. The three columns each contain nine bytes. Of these,
nine bytes are overhead for the Section layer (for example, Section Overhead),
and 18 bytes are overhead for the Line layer (for example, Line Overhead).
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Chapter 8: Appendix
The remaining 87 columns constitute the STS-1 Envelope Capacity (payload

and path overhead).
Fig. 1
4 IP over SDH
4.1 Overview
The objective is quite clear. Service Providers require a mechanism that lets
them deliver the proper services where and when their customers need them.
Data traffic is increasing dramatically whilst carriers will enjoy to use the
existing circuit-switched equipment. Although the combination of data and
voice sounds to be incompatible, the reality of both networks is changing.
New services like voice and video over IP on the one hand and the rapidly
increasing bandwidth supply on the other suggest this combination.
The existence of a widespread, commonly used and highly reliable network

well proven over years is in store for the carriers that tread new paths towards
IP. Standardization ensures a large degree of interoperability. Bandwidth
demand is no longer a real obstacle, but low transit-delay (latency) is. Lowest
latency however is the favorite domain of SDH and Sonet.
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Chapter 8: Appendix
Starting with point to point connectivity solutions and ending up with an

entirely new generation of SDH-integrated IP-Routers, Siemens presents the
way how to combine SDH/Sonet and IP in the most efficient manner.
To understand how this can be achieved requires knowledge of both, basics of

data traffic as well as SDH precautions taken for it.
4.2 Data Traffic in Short
4.2.1 Local Area Networks
LANs (Local Area Networks) are mostly based on CSMA/CD (carrier sense
multiple access/collision detect) generally referred to as Ethernet. Ethernet
speed has been increased from 10Mbps to 100Mbps (Fast Ethernet).
Most of today’s equipment automatically adjusts to the right data rate (auto-
sensing) and is designed to work with twisted pair (UTP) and fiber media
(100BaseT-FS).
Gigabit Ethernet builds on top of the Ethernet protocol but increases speed
tenfold over Fast Ethernet to 1000Mbps. All participants of a network are
grouped into so called LAN segments or Collision Domains. Physically all
stations within a LAN segment are connected to one common Hub.
Thus each station contends with all others for access to the network. If
multiple stations send out packets simultaneously, a collision occurs, which
corrupts the data. The more participants in a collision domain are, the more
collisions occur and the lower the data throughput of a LAN segment is.
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Chapter 8: Appendix
4.2.2 Bridges
Fig. 2
Bridges keep local traffic within a particular LAN segment while allowing
packets destined for other segments to pass through. This process is called
filtering. To increase the throughput within a dedicated LAN segment, the
segment can be subdivided into two sub segments combined via bridges,
creating two separated collision domains and thus minimizing the probability
of collisions.
Ethernet specifies the data link (layer 2) (with the MAC sublayer) of the ISO
protocol model, while IP (Internet Protocol) and TCP (Transfer Control
Protocol) in turn specify the network (layer 3) and transport (layer 4) portions
and allow communication services between applications.
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Chapter 8: Appendix
4.2.3 Switches
Fig. 3
Switches are based on traditional bridges’ capabilities to segment busy

networks by providing multiple dedicated connections. After decoding the
address, the switch sends the packet directly toward its destination. In Ethernet
switching, the MAC address (Media Access Control) defined in Layer 2
determines the switch port to which the packet has to go. Two nodes
connected via a full-duplex, switched path can simultaneously send and
receive packets.
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Chapter 8: Appendix
4.2.4 Router
Fig. 4
In traditional IP networks, each router working at layer 3 calculates the

appropriate hop to the next router for each destination. Packets are forwarded
“hop-by-hop” rather than travelling along a set-up end-to-end connection. IP
delivers a “connectionless” service contrary to a transport network. When the
network is congested, packets are stored inside the router, referred to as
queuing, and forwarded according to special rules e.g. FIFO or priority. Thus
bursty sources can cause high delays in delivering time-sensitive application
traffic.
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Chapter 8: Appendix
4.2.5 Latency
The characteristic that is most harmful to the performance of multimedia

applications is latency. This is the amount of delay that affects all types of
communications links, including those used for the public Internet and private
Intranets. Demand for immediate backbone bandwidth will inevitably force
some traffic to be queued in routers independent of the provided bandwidth.
Most increases in latency occur because network devices (mainly routers) get
overloaded and to make things even worse, large data packets are occasionally
queued ahead of shorter packets, thus introducing longer-than-average delays
and creating jitter.
Such delays as the result of queuing are variable because of the bursty nature
of IP traffic. The higher those bursts are, the longer the delays.
In fact, studies of IP networks show that traffic patterns are “self linear”, like a
fractal. Traffic still has the same burstiness, no matter how large or how small
the aggregate channel is. There is no smoothing of traffic peaks and valleys as
with the combination of large numbers of voice phone calls.
Increases in latency cause packets to arrive at their destination out of their

sequential order, especially during peak traffic periods. The packets are stored
in a buffer at the receiving device until all packets arrive to be put in the right
order. Although these delays do not affect e-mail and file transfers, which are
no real-time applications, excess latency does affect multimedia applications
arriving out of voice and video synchronization like a badly dubbed movie.
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Chapter 8: Appendix
Fig. 5
4.3 To Overcome the IP Corset ...
The bandwidth limitations of the Internet, as well as its high latency and slow
response time, have to be overcome. Network managers have to employ
appropriate routing protocols that conserve bandwidth and/or reserve network
resources and implement flow control.
4.3.1 Tunneling
Tunneling is a method of using an inter-network (e.g. SDH backbone network

or another IP network) to transfer data e.g. frames of another protocol (i.e. IP
packets) as payloads from one network over another network. The payload is
encapsulated in a PPP (Point to Point Protocol) frame to be sent across the
inter-network.
POS (Packet over SDH/SONET) is a high speed WAN transport, that leaves
LAN traffic in its native format. It is a serial link between two access points
like any other - only much more reliable and a whole lot faster.
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Chapter 8: Appendix
With POS, IP Traffic runs over PPP with the resulting frame embedded into
HDLC-like framing (High-level Data Link Control), just it would like any
other type of WAN- circuits-like leased lines. These link layer protocols in
turn run directly over SDH.
Fig. 6
4.3.2 Multi Link PPP
Fig. 7
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Chapter 8: Appendix
Or “all roads lead to Rome”. MLPPP (Multi-Link PPP) co-ordinates multiple

independent links between a fixed pair of participants, providing a virtual link
with greater bandwidth than each had by itself. In order to establish
communications over a point to point link, each end of the PPP link must first
send Link Control Protocol packets to configure the data link. Once the link is
established, the source is free to send the payload encapsulated with the multi
link header.
4.3.3 Multiprotocol Label Switching
MPLS (Multiprotocol Label Switching) is a technique that brings many of the

qualities and attributes of switched networks to IP networks. It introduces the
concept of paths to the routed network. MPLS works by building engineered
paths across the core of a network. Like trains go along predefined railway
tracks from one switch/point to the next, the IP packets go along predefined
paths from one router to the next. An Ingress Router forms the starting point
of a path. Then the packets are sent encapsulated and labeled along those
predefined LSP (label switched paths) hopping from one Label Switch Router
to the next.
Fig. 8
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Chapter 8: Appendix
The termination of the LSP is built by an Egress Router. At the Ingress

Router, the IP-packets are packed into MPLS Layer 2 frames. A so called
Shim-Header is added and the resulting packet is sent to the next Transit
Router on the LSP. At the end of the LSP the Egress Router takes the MPLS
encapsulation away and directs the packet to the next destination in the IP
network. Thus a network will seamlessly use native IP packet forwarding at
the edge, and LSP switching in the core. Labels can be used to identify traffic
that should receive special treatment to meet QoS (quality of service)
requirements.
Fig. 9
4.4 ... and Pep it up with SDH
Most carriers have made very substantial investments to build SDH/Sonet

networks, and they attract more customers and implicitly new as profitable as
possible services. IP market is the highest increasing one and after all, carriers
know that it is better to customize their network than to leave fibre buried in
the ground unused. Obviously a combination of both SDH and IP would be
the most desirable solution.
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Chapter 8: Appendix
With the increasing rate of data streams Gigabit Ethernet comes along with,
coping with the biggest SDH containers, which only offer 155 Mbit/s,
problems are encountered, which need to be resolved. Standard SDH-
Interfaces for IP use multiple independent Virtual Containers which allow the
transport of data via established SDH-networks. Those solutions are offered
by any important IP-vendor.
Fig. 10
The biggest advantage is, that the transport of data is supported by any
established SDH-network even via third party networks (Cross Domain).
Because of the independence of the different transport channels, transport
planning remains highly flexible. Unfortunately additional processing effort in
the appropriate data machines comes along, which reduces data throughput
and subsequently leads to loss of performance on the one hand and to highly
priced equipment on the other.
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Chapter 8: Appendix
Also SDH specification bodies acknowledged these arising problems and

directed their specification work to make SDH more convenient to data traffic.
Concatenation provides a mechanism for transporting payloads greater than

the capacity of a VC-4. Under normal circumstances the “float” of containers
within the supporting higher order virtual container is controlled by the
respective pointer mechanisms. The VC-4s are linked together by setting the
concatenation indicator at each container but the first, which takes the
respective pointer. A set of “n” in this way contiguously concatenated VC-4s
is designated as VC-4-nc. The whole structure looks like one coherent
container.
Fig. 11
The advantages are lower pricing and better performance due to higher
throughput. But contiguous concatenation requires support in each
intermediate network element, which is less supported in established SDH
networks and nearly impossible to maintain in multi carrier topologies.
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Chapter 8: Appendix
Fig. 12
The solution to overcome these problems is virtual concatenation. The

appropriate concatenated payload is designated as VC-4-nv. According ITU-T
G.707 the virtual concatenation is identical to the contiguous concatenation
but breaks the contiguous bandwidth in individual VCs for transportation. As
a consequence the Cross Domain transport of data is ensured, and the
advantages of contiguous concatenation (lower pricing and better
performance) still remain.
Current IP routers often demand contiguous concatenation for the transport of

high bandwidth signals through SDH. Virtual Concatenation can cope with
this problem by easy conversion of VC-4-nc to individual VC-4-nv and vice
versa.
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Chapter 8: Appendix
Fig. 13
With all these features SDH is the ideal transport network for IP wide
area connectivity.
4.5 How it should be
A successful strategy to support IP with the reliable and powerful SDH

backbone network must be aimed at the augmentation of carriers’ profit. The
flexibility to offer different services at any time to their customers under
highly optimized exploitation of the available resources will be the most
sophisticated criteria.
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Chapter 8: Appendix
The solution to maximize network utilization and flexibility is Traffic

Engineering. Obviously, this is the basis which offers the required varied
services. It allows control of traffic streams to avoid congested data paths and
to switch it to sparsely used ones.
Thus it increases the degree of network utilization allocating transport

channels specifically after the demands of the services asked for. MPLS as
described above is a powerful aid to support Traffic Engineering. Mainly
developed for core networks, it meets all the necessary features, e.g. path
switching and QoS indication.
Fig. 14
But to become effective this needs label switch routers entirely integrated in
the network elements, working directly on the switched circuit paths (VC-n).
This enables Traffic Engineering to use the knowledge of path utilization
within the network to divert traffic avoiding congestion and overload of paths.
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Chapter 8: Appendix
Normal router cores suffer from the lack of scalability and bad exploitation of
the network capacity. IP-over-ATM topologies are expensive and complex
caused by the additional cell tax and the co-ordination and management of two
separate networks. Scalability should be proven up to STM-16 and higher.
Traffic Engineering as a basis for offering varied services should be possible.
All these features and more are gained by an SDH backbone network with
integrated label switch routers.
So don’t plug away at IP, plug it to SDH.
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Department of: technology programs and customer service

3 Basic Elements of STM-1 Pages (1-7)

4 Mapping Pages (1-50)

5 Pointer Pages (1-16)

6 Overhead Pages (1-26)

Monitoring, Maintenance and

8 Appendix Pages (1-25)

This document consists of 185 pages.

Chapter 1 PDH Multiplexing

In the early 1970s, digital transmission systems began to appear, utilizing a

In Europe, and subsequently in many other parts of the world, a standard

2 Principles of PDH Multiplexing

PDH signals with a higher transmission rate are obtained by multiplexing

3 ANSI / CEPT Bit Rates

The multiplexing hierarchy described above appears simple enough in

The same problems with synchronization, as described above, occur at every

The use of plesiochronous operation throughout the hierarchy has led to

Another Explanation to help define PDH is:

It may be useful to explain the term Asynchronous at this stage:

In Asynchronous signals, the transitions of the signals don’t necessarily occur

Standardized Bit Rates in the "Plesiochronous Digital Hierarchy" (PDH)

Traditionally, digital transmission systems and hierarchies have been based on

Comparison of the ANSI and CEPT Hierarchies

• PDH in accordance with ANSI (American National Standards Institute);

Fig. 3 Plesiochronous digital hierarchy

4 Frame Structure of a PDH Signal

Fig. 4 Frame structure of a PDH signal

5 Multiplexing / Demultiplexing of PDH Signals

Principles of PDH Multiplexing:

1. What are the bit rates of the CEPT Hierarchy?

3. How many different FAS do exist in a 140 Mbit frame?

1. What are the bit rates of the CEPT Hierarchy?

FAS Frame Alignment Signal

D+N bit Service bits

CB Control bits for justification

JB Justification opportunity bit

3. How many different FAS do exist in a 140 Mbit frame?

Chapter 2 Principles and Characteristics of the

1 Introduction to the Synchronous Digital Hierarchy SDH 2

1 Introduction to the Synchronous Digital Hierarchy SDH

Why use SDH instead of PDH?

The problem of flexibility in a plesiochronous network is illustrated by

Another problem associated with the huge amount of multiplexing equipment

Another limitation of the PDH is its lack of performance monitoring

Operators are coming under increasing pressure to provide business customers

Hence the development of the SDH technology.

What do we mean by Synchronous Digital Signals in an SDH network?

In a plesiochronous network, the individual link sections are not synchronous

2 ITU-T and SDH, an Introduction

Before SDH, the first generations of fiber-optic systems in the public

This ability is referred to as multivendor interworking and allows one SDH-

The comprehensive SDH standard is expected to provide the transport

• A reduction in the amount of equipment and an increase in network

• The availability of a set of generic standards, which enable multi vendor

3 ITU-T Recommendations for SDH Bit Rates

The ITU-T (International Telecommunication Union -Telecommunication

4 Structure of an STM-1 Frame

The two-dimensional representation of an STM-1 frame includes 9 rows with

The sequence of transmission is: top left to bottom right.

The STM-1 frame consists of three blocks:

• Pointer (PTR): indicates the start address of the tributary information.

The frames are transmitted in intervals of 125 µs.

Thus, every byte in an STM-1 frame has a transmission capacity of 64 kbit/s.

5 Byte-by-Byte Multiplexing of SDH Signals