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Ultra-low-latency, High-fidelity Analog-to-
digital-compression Radio-over-fiber (ADX-
RoF) for MIMO Fronthaul in 5G and Beyond
Paikun Zhu, Yuki Yoshida, Member, IEEE, and Ken-ichi Kitayama, Life Fellow, IEEE
Abstract— Wired-wireless convergence technology such as
radio-over-fiber (RoF) is regarded as a promising candidate to
deliver broadband wireless data from/to edge cloud to/from
antenna sites, a notable example being the fronthaul (FH) in
centralized/cloud radio access network (C-RAN). In 5G and
beyond, the latency, bandwidth and fidelity requirements on FH
pose great challenges to the RoF schemes. In this paper, we focus
on analog-to-digital-compression RoF (ADX-RoF) scheme based
on low-latency MIMO data compression, which has the potential
to reduce FH data rate by ~90% compared with traditional digital
RoF (CPRI) while still maintaining signal fidelity for high-order
radio modulation. To verify the practicality of ADX-RoF in the
latency-sensitive FH scenario, real-time hardware demonstration
with latency evaluation is indispensable. We propose and design a
real-time ADX, which achieves low-latency and high-throughput
together with high-fidelity. Enabled by the ADX prototyped on a
single-chip field-programmable radio platform (i.e., Xilinx
RFSoC), we experimentally demonstrate 16-channel MIMO radio
reception, real-time ADX processing and RoF transport. With
<500ns one-way ADX latency, less than 1.5% average EVM is
achieved for 1024QAM, 61.44MHz NR-class signals at a
compression ratio of 13.3%. Negligible fiber-induced performance
penalty is observed after 40km transport. The results highlight the
attractiveness of ADX-RoF for future FH.
Index Terms— Radio access network (RAN), fronthaul, MIMO,
radio-over-fiber (RoF), compression, 5G new radio (NR), real-
time, FPGA
I. INTRODUCTION
D RIVEN by the continuing need for higher speed, higher
connection density and lower end-to-end latency from
human and/or machines, the development of next-generation
wireless system including radio access network (RAN) has
attracted much attention in recent years [1]. Small cell is still
promising for upgrading speed and density, as it enhances
capacity by dividing a macro cell into smaller zones and
spatially reusing the radio resource. From 3G to the 5G, the site
density is anticipated to increase from 4~5 per km2 to 40~50 per
km2 [2] and even 12 per 0.006km2 (indoor hotspot) [3]. But with
Manuscript submitted XX, XX. This work was supported in part by the R&D
contract (FY2017~2020) “Wired-and-Wireless Converged Radio Access
Network for Massive IoT Traffic” for radio resource enhancement (JPJ000254)
by the Ministry of Internal Affairs and Communications (MIC), Japan.
P. Zhu is with The Graduate School for the Creation of New Photonics
Industries (GPI), Hamamatsu, Japan (e-mail: zpk@ gpi.ac.jp).
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1
the dense deployment, cell-site cost becomes a threat, as cell
sites typically consume most cost and power consumption of a
mobile operator [1]. Centralization and fronthauling (e.g.,
centralized/cloud RAN, C-RAN [4]) is a key solution to this
issue. With C-RAN, cell sites are simplified, while baseband
units (BBU) of the base stations are pooled and cloudified. In
this way, cost and energy consumption can be effectively
reduced, and inter-cell coordination can also be facilitated.
To deliver wireless data from/to cloudified BBU to/from cell
sites, radio-over-fiber (RoF) technology has been regarded as a
promising candidate for FH. It aims to transport radio
waveform “as it is” without touching the information inside,
which retains the benefits of fully centralized RAN architecture
and is also compliant with Option 8 in the 3GPP specification
of functional split [5]. In conventional fronthaul (FH) in 4G,
digitized RoF (D-RoF) with Common Public Radio Interface
(CPRI) [6] has been primarily used. To alleviate the FH
bandwidth issue of CPRI, data compression approaches [7-12,
23] have been actively investigated. On the other hand, the
spectrally-efficient analog RoF (A-RoF) schemes such as
intermediate-frequency-over-fiber (IFoF) have also been
widely discussed [13-18].
This work focuses on RoF FH based on data compression, or
“analog-to-digital compression RoF (ADX-RoF)” referred
hereafter (term “ADX” from [19]). In 5G and beyond, the
requirement on FH bandwidth and signal fidelity would be
more stringent, due to the use of more multiple-input-multiple-
output (MIMO) antennas, new radio (NR) with wider
bandwidth, and high-order radio modulation such as 1024QAM
[20]. Conventional ADX approaches [7-12] only compress in
time domain with moderate compression ratios (CR, FH data
rate after compression divided by that before compression) of
1/3~1/2, which still needs further improvement.
Furthermore, a major challenge for FH in 5G and beyond is
the tight latency requirement. For example, 3GPP stipulated
that one-way transport network latency, including the essential
fiber propagation delay and latency overhead of all signal
processing like ADX, should be within 250µs [5]. However,
Y. Yoshida is with Network System Research Institute, National Institute of
Information and Communications Technology (NICT), Koganei, Japan (e-mail:
yuki@nict.go.jp).
K. Kitayama is with GPI, Japan, and also with Network System Research
Institute, NICT, Japan (e-mail: kitayama@gpi.ac.jp).
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TABLE I
SUMMARY OF A-ROF, ADX-ROF, AND D-ROF/CPRI
RoF-based FH scheme A-RoF ADX-RoF (this work) D-RoF/CPRI
1 2
Req. FH bandwidth Down to 1M∙R 1.5M∙R ~ 3M∙R 30M∙R
Fidelity of radio waveform lowest medium highest
WDM A-RoF: 0
DSP latency <500ns + framing latency 3 framing latency
FDM A-RoF [16]: <1µs
WDM A-RoF: WDM TRx array TRx array
Source of FH cost ADX DSP block, 1 TRx
FDM A-RoF: high-speed DAC & ADC, 1 TRx (or 1 ultra-broadband TRx)
1
Here only payload is calculated.
2
Assume PAM4 is used as optical interface.
3
framing latency is different from CPRI case, since data has been significantly compressed.

most existing ADX techniques are still verified by simulation Moreover, such conversion and line (i.e., optical channel)
or offline experiment, in which the processing delay of coding/modulation are jointly optimized, forming a converged
compressor/decompressor is difficult to evaluate. Real-time wired-wireless link [25].
hardware demonstration is of particular importance to quantify RRU

processing
Baseband
…

decode
ADX latency.

ADX
RF front end
O/E
UE1
In a previous work [25], we introduced spatial-domain

ADX
FH network

A/D
M×

compression in the multi-user and/or massive MIMO scenarios,
and showed the potential CR of 1/10 with EVM<1% by the
space-time ADX concept. Recently, a preliminary field-
programmable gate array (FPGA) based ADX was reported yet
with only 5.5MHz throughput [21]. Note that if circuit
throughput is not sufficient, large buffering latency would be
induced when handling large wireless signal bandwidth (e.g.,
5G NR) and/or heavy traffic load. Therefore, both low latency
and high throughput has to be realized for a future-proof ADX-
RoF based FH.
In this paper, we present the first real-time ADX enabled
40km RoF transport, with verified low latency and high
throughput. We provide detailed ADX hardware design
targeting low-latency, high-throughput and high-fidelity, which
leads to a real-time ADX supporting 16-channel MIMO with
61.44MHz per-channel throughput. Based on the ADX
prototyped on a single-chip field-programmable radio platform
(i.e., Xilinx RFSoC), we experimentally demonstrate 16-
channel MIMO analog reception of 5G NR-bandwidth signals,
real-time ADX processing, and RoF transport over 40km in the
1.55µm band. With <500ns ADX latency overhead, <1.5%
average EVM is achieved for 16-channel MIMO 5G NR-class
radio signals.
The rest of the paper is organized as follows. In Section II,
we describe the concept of fronthaul based on ADX-RoF.
Section III presents in detail the key approaches of hardware
design to realize low-latency, high-throughput and high-fidelity
…
E/O
BBU (CU)
UEP
Fig. 1. Schematic of FH based on ADX-RoF.
The radio waveforms encapsulated in digital optical signals
are then transported over FH network. To efficiently
accommodate many cell sites, next-generation FH might be an
Ethernet-like network, e.g., a layer-2 network [4, 22]. The
ADX-RoF concept with digital optical format is highly
compatible with packetization, multiplexing and switching. The
signal received at baseband unit (BBU) is processed by ADX
decoding for MIMO waveform reconstruction, followed by
physical-layer DSP.
Table I shows a summary of A-RoF, ADX-RoF and D-
RoF/CPRI based FH schemes. We assume the RRU is equipped
with M antennas, while M/4 radio signal streams each with
sampling rate of R are received; single-mode fiber is used for
FH. ADX-RoF can be regarded as an intermediate of A-RoF
and CPRI. It can significantly ease optical FH due to bandwidth
efficiency close to A-RoF, while having higher signal fidelity
thanks to the high-fidelity ADX DSP and reliable digital optical
format. Moreover, in 5G and beyond, ADX-RoF instead of
CPRI could provide a more practical performance reference for
designing A-RoF schemes.
Figs. 2(a) and (b) show 2 possible ADX architectures: since
MIMO data can be represented by a 2-dimensional (space and
Ch. 1

ADX. In Section IV, real-time experimental results are reported Ch. 1

2-D
with discussions. Section V concludes the work.
MUX
…

compress.
…

II. FRONTHAUL BASED ON ADX-ROF Ch. M Ch. K

(a)
Fig. 1 shows a schematic of ADX-RoF based FH, where Ch. 1
uplink is depicted as an example. At remote radio unit (RRU), Ch. 1 Ch. 1
P signal streams from user equipment (UE) received by M
Spatial Temporal
antennas are down-converted by radio frontend and digitized by
MUX
…

…
…

compress. compress.
analog-to-digital converters (ADC). Subsequently, baseband
MIMO data are converted to digital stream by the ADX, with Ch. M Ch. K Ch. K

complexity lower than that for MIMO demodulation. In the (b)

Fig. 2. ADX architectures based on (a) simultaneous compressing the space
conversion process, data amount is significantly reduced while and time dimension; (b) 2-stage sequential processing.
satisfying the latency and signal fidelity requirements.

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time) matrix, ADX may compress the 2 dimensions either Spatial

x1
simultaneously (like Wyner-Ziv compression [23] or image Ch 1
x2
y = WHx
codec [24]) or sequentially. The former approach may be x3 Spatial y1 Ch 1
Filter

…
optimal from the information theoretic point of view. However, x4 …

…
… WM×K
yK
in this work, we mainly discuss the latter architecture from Ch M xM
Ch K

practical hardware implementation point of view. In Fig. 2(b),

MIMO dimensionality is reduced from M to K by spatial Filter update (a)
compressor, then each channel is bit-reduced and/or sample-
reduced by temporal compressor; the two part are jointly
optimized [25]. In addition, the last stage after MUX (not
Spatial
Ch 1 x1 y = W Hx
x2 Spatial y1 Ch 1
depicted) is the optional spectrum efficiency (SE) enhancement Filter
x3

…
…
of optical link (e.g., by multi-level PAM), which completes the

…
x4 WM×K yK Ch K
concept and makes joint optimization of compression and …
optical link feasible. Ch M xM FIFO

Update
III. HARDWARE DESIGN OF LOW-LATENCY, HIGH- (b)
THROUGHPUT, HIGH-FIDELITY ADX
As discussed in Section I, it is crucial to quantify processing (auxiliary)
Spatial
latency and throughput of FH ADX by real-time hardware Filter

demonstration. In the following, we present key enabling

approaches to design low-latency, high-throughput, high- Filter update

fidelity ADX for real-time ADX-RoF based on FPGA hardware Fig. 3. (a) Schematic of FH spatial compressor based on subspace tracking SF.
platform. (b) Schematic of designed high-throughput spatial compressor hardware.

A. Spatial compressor design

𝑾 = 𝑎𝑟𝑔 min𝑊 ′ 𝐸{‖𝒙 − 𝑾′ 𝑾′𝑯 𝒙‖2 } (1)
Spatial compression aims to remove redundant spatial For example, the update procedure of W in projection
channels when the number of independent MIMO streams P is approximation subspace tracking (PAST) [28] is:
smaller than the number of RRU antennas M, which is the 𝒚(𝑡) = 𝑾(𝑡 − 1)𝑯 𝒙(𝑡) (2)
typical case in multi-user MIMO and/or massive MIMO 𝑷(𝑡−1)𝒚(𝑡)
scenario [26]. Fundamentally, it can be regarded as a problem 𝒈(𝒕) = (3)
𝛽+𝒚(𝑡)𝑯 𝑷(𝑡−1)𝒚(𝑡)
of Karhunen-Loeve (K-L) transform of the input L-by-M signal −1
𝑷(𝑡) = 𝛽 ∙ 𝑇𝑟𝑖{𝑷(𝑡 − 1) − 𝒈(𝑡)𝒚(𝑡) 𝑷(𝑡 − 1) (4) 𝑯 𝑯}

matrix X, L being the number of signal samples in each
compression operation. The best-known solution (in the least
square sense) is to perform singular value decomposition
(SVD) of X such as by principal component analysis (PCA)
algorithm [27], but its feasibility for FH is hindered by the high
complexity and latency due to batch-type processing.
We point out that it is possible to achieve low-complexity,
even real-time implementable K-L transform for FH spatial
compression, owing to the feature of this task: it’s not necessary
to obtain individual principal components; instead, extracting
the signal subspace as a whole suffices (i.e., only a part of
eigen-structure is needed [28]). Based on this idea, we have
proposed adaptive FH spatial compression (or “spatial filter”,
SF) with complexity of O(MK) per iteration base on fast
subspace tracking (FST) [25].
Fig. 3(a) shows the schematic of FST-based SF, which
consists of a filtering/compression part and a feedback filter
update part. The input MIMO signal at each time index is
modeled as an M-by-1 vector x, while the SF is a M-by-K matrix
W. The SF outputs the compressed K-by-1 (P≤K<M) vector
𝒚 = 𝑾𝑯 𝒙. Larger K corresponds to more spatial diversity gain
(thus improved fidelity), but also increased complexity of SF
and CR [25]. Coefficients of SF W are updated by different FST
algorithms, such as by iteratively solving a certain minimization
problem, e.g., Eq. (1) [28, 31], where E(*) and ||*|| denote
expectation and 2-norm respectively.
𝑾(𝑡) = 𝑾(𝑡 − 1) + [𝒙(𝑡) − 𝑾(𝑡 − 1)𝒚(𝑡)]𝒈(𝑡)𝑯 (5)
Although a lot of theoretical efforts have been made on FST
techniques [28-36], to the authors’ knowledge, few works have
investigated the latency or throughput of FST techniques from
a hardware perspective. In the following, we present the design
procedure of FST-based SF circuit.
First, in order to select a suitable algorithm for hardware
implementation, we investigate computation details of
candidate FST algorithms. In particular, we focus on the latency
and multiplier consumption of filter update part, since the
former largely impacts on the throughput of SF while the latter
is the dominant measure of complexity.
The summary of analysis is given in Table II. For the latency
of filter update (column 5), the number of division (column 3)
and square root (column 4) operations have the most significant
impact. This is because to achieve high computation accuracy
and fidelity of SF, division is usually implemented by Radix-2
algorithm [37] and square root is usually implemented by
CORDIC algorithm [38]. As a result, their latencies can be >10
times higher than that of other arithmetic operations like
multiplication and addition. On the other hand, the number of
multipliers used in filter update are given in column 7.
Conventionally, the complexity of FST was evaluated by the
order of the number of (complex) multiplications. However, for
hardware implementation, more accurate analysis is needed.
Our estimation indicates that although all FST algorithms have

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TABLE II
SUMMARY OF COMPUTATION DETAILS OF STATE-OF-THE-ART FAST SUBSPACE TRACKING (FST) ALGORITHMS
Num. of sequential Num. of Estimated latency of filter Num. of complex multipliers for Estimated num. of DSP48
Algorithm Ref.
division square root update (unit: clock cycle) filter update** consumed (M=16, K=4)
PAST [28] 1 0 18* 2MK+2.5K2+K 688
OPAST [29] 2 1 40 3MK+2K2+1.5M+2.5K 1032
CPAST [30] 1 0 26 3MK+5.5K2+2K 1152
FAPI [31] 3 1 66 2MK+1.5M+5K2+6.5K 1032
NIC [32] 1 0 19 2MK+3.5K2+K 752
FDPM [33] 2 1 58 5.5MK+M+2K 1504
FSDPM [34] 2 2 63 2MK+3M+1.5K 728
FOOJA [35] 1 1 58 6MK+2.5K 1576
SOOJA [36] 2 1 63 2MK+3M+1.5K 728
Assuming 1 division needs 10 clock cycles [34]; 1 square root needs 16 clock cycles [35]; 1 complex multiplier equals 4 real multipliers.
*Experimental value. **Excluding “forward filtering” block which consumes the same complex multipliers (MK) for all algorithms.

Input: x(t) (M×1) 𝑯 in Fig. 3(b). The forward filtering part (i.e., matrix-vector
Forward 𝒚 𝑡 = 𝑾(𝑡 − 1) 𝒙 𝑡
(a) Filtering multiplication) operates at a latency of 2 clock cycles (CC) or
Z-2 (2 clk
cycles) 𝑡 = 𝑷(𝑡 − 1)𝒚(𝑡) Z-2
≈17ns with a throughput of FPGA clock rate. PAST-based filter
𝑡 = 𝒙 𝑡 −𝑾 𝑡−1 𝒚 𝑡
(2 clk cycles) update part works at a throughput of 6.144MHz. SF is updated
(2 clk cycles) every T input sample period. T is positively correlated with
𝑡 = 𝛽 + 𝒚(𝑡)𝑯 𝑡
Z-13 (2 clk cycles)
throughput of the spatial compressor, and negatively correlated
Z-2 with converging speed of the filter update part. We selected
𝑾 𝑡 = 𝑾 𝑡 − 1 + 𝑡 𝒈(𝑡)𝑯
(3 clk cycles) T=10 for the throughput of 61.44MHz. The filter update part
Z-11
1
converges within ≈102T samples, or ≈20µs in our
𝑷 𝑡 = 𝑇𝑟𝑖 𝑷 𝑡 − 1 − 𝒈 𝑡 (𝑡)𝑯
𝛽 𝒈 𝑡 = 𝑡 (𝑡) implementation, which is still much faster than the variation
(3 clk cycles) (10+1 clk cycles)
speed of MIMO channel (typically, ms-level [40]). Thus, the SF
(b) circuit can deal with dynamic cases.
6.4 P=4
P=4 (w/o SF) Next, the internal precision of the SF circuit is designed.
3.2 P=2 There is a trade-off between computation precision and FPGA
P=2 (w/o SF) resource consumption. Also, it is found that the precision
1.6
P=1
EVM (%)

P=1 (w/o SF) requirement of matrices W and P is higher than other internal
0.8
variables. In this work, 25-digit precision is designed for
0.4 matrices W and P, and 18-digit precision is used for other
0.2 internal variables.
Based on the discussions above, we designed a 16-by-4 SF
0.1
20 25 30 35 40 45 50 circuit with processing latency of 17ns and per-channel
Wireless SNR (dB) throughput of 61.44MHz at 122.88MHz clock. The detailed
Fig. 4. (a) Block diagram of designed PAST-based filter update circuit of the block diagram of designed filter update part is shown in Fig.
spatial compressor (or SF). Matrices, vectors and scalars are marked by bold 4(a). Before hardware prototyping, we assess the performance
upper-case letters, bold lower-case letters and regular letters. Operator Tri{*}
indicates that only the lower triangular part of the matrix is calculated, and its
of the designed SF circuit by Xilinx Vivado 2018.3 FPGA
Hermitian transposed version is copied to the upper triangular part [25]. Simulator. The 16-channel inputs of the SF circuit are generated
β=0.9999. (b) Simulation results of EVM versus wireless SNR of the designed in Matlab through P OFDM signal generation, P×16 MIMO
SF circuit. Wireless SNR: ratio of the total power of 16-channel signals to the
total power of added noise. Dashed lines: demodulated EVM without SF
channel propagation, noise adding, and 12-bit digitizing.
compression. Spatial multiplexing MIMO technology without precoding is
assumed. Independent and identically distributed (i.i.d.)
the same order of complexity O(MK), the difference in Rayleigh fading is assumed for MIMO channel, emulating a
consumed FPGA multipliers (i.e., DSP48) can be >800. As TABLE III
reference, medium-class FPGAs may have only about NUMEROLOGY OF THE TEST 5G-NR-LIKE OFDM SIGNAL
600~2000 DSP48s in total. Parameter Value / description
Based on the analysis, we select PAST as the basic FST Num. of independent streams (P) 1~4
algorithm for SF hardware implementation, which has the Modulation format 1024QAM
lowest latency of filter update and lowest complexity. IFFT size 4096
However, the direct implementation of PAST (based on Fig. Num. of data subcarriers 3300
Cyclic prefix length (samples) 512
3(a)) results in a throughput of only 5.5 MHz [21], which is still
Subcarrier spacing (kHz) 15
much smaller than 5G NR bandwidth [39]. It thus requires Signal bandwidth (MHz) 50
buffers (e.g., FIFO) at ADX inputs with high latency Payload length 2 OFDM symbols
proportional to the wireless packet size. In practice, high circuit MIMO training symbol (TS) QPSK-OFDM [39], space-time
format block coding (STBC) structure [41]
throughput is crucial to eliminate such buffering latency. To
achieve 5G NR-class throughput, we propose to decouple the
forward filtering part and feedback filter update part, as shown

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In d(k) I(k) Out In Out

+ Q + Q
- -
Q-1 Δ Q-1
Δ
Se(k)
dq (k) P
Predictor (P)
(a) (b) Reg.
Fig. 5. Schematic of ADPCM encoder. d(k): difference signal. I(k): quantized
codeword of d(k). dq(k): signal after de-quantization. Se(k): predicted signal.
Predictor is usually implemented by FIR filter network. Δ: gain adaptation
circuit.
ADPCM
rich scattering environment [40, 50]. Noise is added by firstly i-th output SBF
Re/ ADPCM
of SF

…
measuring the total power of 16-channel signals, calculating the Im ADPCM
SBF
noise power based on the wireless SNR value, and then (c) ADPCM
generating and adding white Gaussian noise component to each
Fig. 6. (a) Magnitude response of low-pass (solid) and high-pass (dotted) filter
sample of each channel. decompression and demodulation are of 2-band 16-tap Johnston type-B QMF. (b) Schematic of ADPCM encoder
based on Matlab. The numerology of test signals is given in with halved-rate prediction. Reg.: register. (c) Schematic of the entire temporal
Table III. 768-sample preamble (copy of a portion of payload) compressor.
is added in front of TS to assist the convergence of SF. The high-pass SBFs.
result of EVM versus wireless SNR is shown in Fig. 4(b). The The second approach is to improve the throughput of single
EVM curves without any compression are also plotted as ADPCM circuit. As shown in Fig. 5, the throughput of ADPCM
reference. The SF circuit shows negligible compression penalty is limited by the latency in 2 loops: (i) (inner) loop of
until the EVM region of <0.4%, which nevertheless has an quantization--gain adaptation and (ii) (outer) loop of
insignificant impact regarding the EVM target of 2.5% for quantization--prediction. To reduce latency in loop (i), a
1024QAM. simplified gain-adaptive quantizer (compared with standard
B. Temporal compressor design 16

Temporal compression is a task of representing each signal 8

sample with less bits and/or reducing the number of samples to
EVM (%)

be transported over FH [7-12]. Due to the similarity between 4

digital audio transmission (e.g., handset to wireless headphone) 2

[44] (7.69MHz)
and FH transport, FH temporal compression can be inspired by New (61.44MHz)
1
low-delay audio coding techniques [1]. Based on this idea, we 1024QAM
New (FPGA Sim.)
proposed concept of FH temporal compression based on 0.5
adaptive quantizer, e.g., the well-known adaptive differential (a)
3 4 5
Quantization Bit
6 7 8

pulse code modulation (ADPCM, such as audio standard G.726

16
[42]). We showed its good adaptivity against variations of input FPGA Simulation
8
radio signal power and bandwidth [25]. The schematic of 1024QAM
EVM (%)

4
ADPCM is shown in Fig. 5. However, existing ADPCM
2
hardware has throughput of only <1MHz (commercial) [43] or
1
~7MHz (home-made) [44]. This would induce severe buffering
latency for wideband 5G NR-class radio signals. 0.5
-27 -21 -15 -9 -3 0 3 9 15 21
To achieve high-throughput temporal compressor, 2
(b) Relat. power of input signal (dB)
approaches are proposed. The first is to use a bank of
40
subbanding filters (SBF) before quantizer. In audio field, SBF
Largest power diff. (dB)

has been used to enable per-subband bit allocation based on 30

audio spectral characteristics [45]. Here, SBF is utilized as an 20
efficient way of parallelization. At compression side, SBF
analysis filter decomposes the input signal into N subbands each 10

having 1/N of original bandwidth, which can then be processed 0

by N compressors with limited throughput. Thus, N-band SBF
can increase the throughput of the temporal compression by a
factor of N. At the decompression side, signal is reconstructed
by the corresponding synthesis filter. A hardware-efficient
example of SBF is the quadrature mirror filter (QMF) with
polyphase implementation [46]. In this work, considering the
tradeoff between throughput, SBF latency and in-band SNR, 2-
band 16-tap Johnston type-B QMF is employed. Figure 6(a)
shows the frequency response of the employed low-pass and
1 2 3 4
(c) Num. of streams (d)
Fig. 7. (a) FPGA simulation result of NR-like signal compression by using
the designed 61.44MHz 8-bit temporal compressor. Matlab floating-point
simulation results are also plotted. 12bit ADC is emulated before
compression. (b) FPGA simulation result of EVM versus input signal power
of the temporal compressor. The rapid EVM increase (rightmost) is due to
the overflow of internal circuit. (c) Largest power difference among 4 output
channels of 16-by-4 SF (in 500 MIMO channel realizations). The cases of
1~4 signal streams are simulated. (d) FPGA simulation result of EVM versus
signal bandwidth.

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Px16 MIMO BBU

RRU

processing
DAC ADC

Baseband
ADX dec.
Line dec.
1 DAC ADC

VOA PD

IF interface

IF interface
DAC
cable
ADC ≈4Gb/s
SMF

Line coding
OOK

RAM
2
ADX

GTY
MZM
x16 GTY cable
…

(i)
P
DAC ADC
laser
DAC ADC DAC→ADC
cables
(ii)
RFSoC
Emulated offline RFSoC (real-time)

Fig. 8. Experimental setup. IF: intermediate frequency. RAM: random access memory. Inset (i): photo of RFSoC-based prototype; (ii): Measured spectra of 3 IF
channels among 16.

G.726 audio ADPCM) is designed [47], in which exponential
and logarithm operations on the signal are removed. The
quantization latency is reduced from 5 CC [44] to 2 CC. To
reduce latency in loop (ii), we halve the rate of prediction from
once a sample to once 2 samples (Fig. 6(b)). Overall, 30.72MHz
ADPCM throughput can be achieved at fClk=122.88MHz.
Combined with 2-band SBF, 61.44MHz throughput is
achieved. In addition, the temporal compressor circuit has μs-
level convergence time, which is also much shorter than the
MIMO channel coherence time.
In addition, after the simplification described above, we
design higher-resolution compressor to support 5G format like
1024QAM. We use Matlab model to seek suitable quantizer
resolution for 1024QAM. Fig. 7(a) shows Matlab simulation
results of single-channel NR-like OFDM signal compression by
using the designed 61.44MHz-throughput temporal
compressor. Performance of low-throughput ADPCM [44] with
FIFO are also plotted. It is seen that 1024QAM cannot be
supported by conventional 5 or 6-bit ADPCM [42, 44]. This
highlights the importance of our high-resolution design.
Considering proper EVM margin, 8-bit resolution is selected.
Based on the discussions above, we designed the 61.44MHz
temporal compressor circuit under the clock rate of
122.88MHz. Its schematic is shown in Fig. 6(c). The internal
precisions are 18-digit and 20-digit. FPGA simulation result of
8bit temporal compressor is also plotted in Fig. 7(a). The
performance compromise appeared in 6-bit quantization case is
due to the techniques used to achieve NR-class throughput
(reduced prediction rate of ADPCM and reduced effectiveness
of differential operation after SBF).
The performance of the temporal compressor circuit is
evaluated by Vivado FPGA simulator. Fig. 7(b) shows EVM
versus input signal power of the 8-bit temporal compressor,
where 0-dB relative power of input signal corresponds to the
lowest EVM. Input power variation of >36dB can be tolerated
TABLE IV
RESOURCE CONSUMPTION OF THE REAL-TIME ADX
LUT
Spatial compressor 21027
Temporal compressor 72741
Total 93768
Available 425280
Utilization 22%
without exceeding 1024QAM threshold. Such a wide dynamic
range is important for our ADX architecture, since the temporal
compressor processes SF outputs, which have different power
among channels. Fig. 7(c) depicts the largest power difference
among 4 output channels of 16-by-4 SF. Specifically, 500
MIMO channel realizations were simulated to obtain
500×4=2000 power values and the “largest power difference”
is the difference between the largest value and the smallest
value. The largest power differences of cases of 1~4 signal
streams are 33.1dB, 21dB, 15.4dB and 7.4dB respectively,
which can all be handled by the >36dB dynamic range of the
temporal compressor. In Figs. 7(a)-7(c), the signal bandwidth is
50MHz as in Table III. In addition, Fig. 7(d) shows the EVM
performance versus signal bandwidth, varied by changing the
number of data subcarriers and maintaining 15kHz subcarrier
spacing. Although the current temporal compressor architecture
becomes quite different from conventional ADPCM, certain
bandwidth adaptivity can still be enjoyed as EVM is improved
when the signal bandwidth is less than 30MHz.
IV. EXPERIMENTAL SETUP, RESULTS AND DISCUSSION
By cascading the designed SF and temporal compressor, a
16-channel ADX with 61.44MHz per-channel throughput is
designed. The ADX is then prototyped on the real-time
hardware. The resource consumption is given in Table IV. The
hardware selected in this work is Xilinx RFSoC (XCZU29DR-
2FFVF1760E), which is a single-chip field-programmable
radio platform that integrates 16-channel, GHz-bandwidth
digital-to-analog converter (DAC) and analog-to-digital
converter (ADC) arrays, digital radio frequency (RF) chain and
FPGA. By leveraging this platform, we were able to
demonstrate in real time not only the ADX but also the 16-
channel analog radio reception with real effects of DAC and
ADC [55]. Moreover, the on-chip integrated DACs and ADCs
are tightly synchronized with good guarantee, which largely
resolves the synchronization, timing offset and jitter issues
usually existed in prototypes using discrete
Block RAM DSP48
components/devices [49].
We conducted ADX-RoF-based FH transport experiment
15 1164
0 288 based on the real-time ADX prototype. The setup is depicted in
15 1452 Fig. 8. In offline emulation, P independent 5G NR-like OFDM
1080 4272 streams were transmitted over P×16 MIMO i.i.d. Rayleigh
1.4% 34% fading channel, resulting in 16-channel signals. The signal

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-20
P=4, Exp. Stream 1 Stream 2 2.6E-05
BtB
BtB
1.3E-05 40km 8 -22
8 P=4, Sim. 40km

20*log10(EVM) (dB)
BtB (BER<1e-7) -24
P=2, Exp. 6.4E-06 1024QAM
40km (BER<1e-7) -26
P=2, Sim.

EVM (%)
3.2E-06 4 -28
4
1024QAM

BER
1.6E-06 -30
EVM (%)

-32
8.0E-07
2 2 -34
4.0E-07
Stream 3 Stream 4 -36
2.0E-07 -38
1 1.0E-07 1 -40
-19 -18.5 -18 -17.5 -17 -19 -18.5 -18 -17.5 -17
(a) Rx Optical Power (dB) (b) Rx Optical Power (dB)
0.5
20 30 40 50
(a) Wireless SNR (dB) (b)
Fig. 9. Experimental results. (a) EVM vs. wireless SNR. Matlab floating-point
simulation results are also plotted. (b) Constellations of 4 signal streams
(wireless SNR=50dB).

numerology is given in Table III. After MIMO channel, noise (c)

was added by firstly measuring the total power of 16-channel
signals, calculating the noise power based on the wireless SNR
value, and then adding noise component to each sample of each
channel. Subsequently, the 16 channels were loaded in the
memory of RFSoC. The 16-channel signals in the RAM were
up-converted to an intermediate frequency (IF) of 100MHz and
emitted by the on-chip 14bit DAC array operating at
983.04MSa/s. The measured spectra of 3 analog IF-OFDM
channels among 16 are depicted in inset (ii) of Fig. 8. The
5~10dB power difference among the 3 channels is due to the
MIMO channel fading.
At remote radio unit (RRU), the on-chip 12bit ADC array
digitized these 16 IF channels at 983.04MSa/s, followed by
real-time down-conversion to baseband and resampling to
61.44MHz. The ADX performed real-time compression at
61.44MHz throughput, including a 16-by-4 spatial compressor
(i.e., M=16, K=4; with PAST-based filter update) and a group
of 8-bit temporal compressors. No FIFO was used before ADX,
as the throughput is sufficient for the 61.44MHz signals. The
compressed bitstream after ADX was 64b/66b line coded [6]
and output by the GTY serial transceiver with a resulting bit
rate of 4.05504Gb/s. Considering the control word overhead of
16/15 and line coding overhead of 66/64, the CPRI-equivalent
rate in this case is 32.4Gb/s = 61.44(MHz)×(15×2)
×16(ch)×overhead. The compression ratio of ADX compared
with CPRI is (4/16)×(8/15)≈13.3%. The electrical OOK stream
output by GTY was amplified and modulated onto an optical
carrier at 1552.5nm via a LiNbO3 Mach-Zehnder modulator.
The optical OOK signal (~2dBm power) encapsulating radio
waveforms was then transmitted over 40km single-mode fiber
(SMF) to the baseband unit (BBU). A variable optical
attenuator (VOA) was used to vary the received optical power.
At BBU, the OOK signal was received by a 12.5Gb/s
photodetector (PD) and captured by a Tektronix oscilloscope
operating at 12.5GSa/s. Offline processing includes down-
sampling, OOK bit decision, line decoding, ADX
decompression, MIMO demodulation, and EVM evaluation. In
the available setup, the received OOK waveform contains a
lifted part (about 1e5 bits) at the beginning of frame. In the
offline processing, block DC removal was applied for this
beginning part before OOK decision. Neither link forward error
Fig. 10. Experimental results. (a) Optical link BER vs. Rx optical power. (b)
EVM vs. Rx optical power. EVM(dB)= 20log10(EVM). (c) Complementary
cumulative distribution function (CCDF) of measured EVM (40km FH, Rx
power=-17dBm). Floating-point simulated ADX result (assuming error-free
FH) is also plotted.
correction (FEC) nor electrical equalizer was used.
First, the performance of real-time ADX with different
wireless SNR was measured. The FH link was assumed to be
error-free. The measured EVM versus wireless SNR is shown
in Fig. 9(a), where each point is an average of P streams and 28
different MIMO channel realizations. The ADX supported
cases of P=1 to 4, and here we show the cases of P=4 and P=2.
In P=4 case, EVM was less than 2.5% when wireless SNR was
larger than 30dB. The EVM floor, mainly caused by the
temporal ADX, was around 1.4%. Fig. 9(b) shows
constellations of 4 streams at wireless SNR=50dB. In P=2 case,
since the ADX provided more spatial diversity gain [25], lower
EVM was observed at all SNR values. Note that throughout this
work, TS were also compressed by ADX without being
processed separately from payload, which in fact affected the
accuracy of MIMO channel estimation. Nevertheless, such high
EVM performance was still achieved, highlighting the fidelity
of our real-time ADX. Real-time experimental results agree
well with Matlab floating-point simulation results.
Next, we fixed P=4 and wireless SNR at 50dB, and
investigated the impact of FH link error. Fig. 10(a) shows link
BER vs. received optical power of both back-to-back (BtB)
case and after 40km SMF transmission. After ADX, the line
rate became only about 4Gb/s, which led to negligible
dispersion-induced penalty. The simple OOK format allows the
use of cost-effective optical transceivers in practice. Fig. 10(b)
shows measured EVM vs. received optical power. When the
received optical power was -17.5dBm or larger, all 4 uplink
streams had EVM of less than 1.55%. The averaged EVM was
around 1.45%. This equals more than 4.5dB EVM margin with
respect to 1024QAM threshold (-32.04dB). Note that it would
be very challenging for A-RoF to support 40km transport of
NR-bandwidth radio signals meanwhile maintaining EVM
better than 1024QAM threshold. By comparing Fig. 10(a) and
11(b), it was observed that the real-time ADX can tolerate 1.4e-

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RF chain delay from RAM to
ADX (1.98µs)
Fig. 11. Experimental results: latency break-down of the demonstrated ADX-RoF link.
6 link BER without exceeding 1024QAM EVM threshold.
Thus, one can adopt simple link FEC or even omit FEC as a
joint design of wireless part (compression) and wired part
(channel coding). In addition, Fig. 10(c) shows complementary
cumulative distribution function (CCDF) of EVM when
received optical power is -17dBm after 40km ADX-RoF
transport. Although the impact of MIMO fading channel has
been included in this demonstration, EVM distribution was
reasonably concentrated. All measured EVMs met 1024QAM
requirement.
Finally, the ADX latency experimentally measured by
Vivado Integrated Logic Analyzer (ILA) is shown on the left
side of Fig. 11. The ADX had a latency of 131ns (i.e., 16 CC),
including 16ns from spatial ADX, 74ns from SBF, 33ns from
ADPCM, and 8ns register. Moreover, according to Vivado
FPGA simulation, the latency of ADX decompression at BBU
is 359ns (i.e., 44 CC). In total, the ADX-induced one-way
latency overhead is (131+359)ns<500ns. Fig. 11 also shows
latency break-down of the ADX-RoF link (except the offline
BBU part), including measured RF chain delay (1.98µs), line
coding latency (16ns), GTY latency (~260ns), and fiber
propagation delay of ~196.15µs as shown by the captured
waveforms in optical BtB and 40km transmission cases. It is
clear that our real-time ADX has negligible latency overhead
compared with either fiber propagation delay or 3GPP one-way
transport network latency budget of 250µs [5].
In the experiments, we demonstrated that even for the most
challenging case of 1024QAM (highest modulation order in 5G
NR), the real-time ADX can support its fronthauling with a CR
of only 13.3% and ultra-low processing latency of <500ns. To
support this challenging scenario, not only high-fidelity ADX
was needed, but also high-performance DACs and ADCs were
used [51, 52]. If the DACs/ADCs with lower effective number
of bits (ENoB) are employed, it would be beneficial for the cost
and power consumption of the wireless system. Meanwhile, the
received signal quality prior to FH transport would be degraded.
In this case, the wireless system may adopt lower-order
modulation format, also allowing more tolerance to ADX
compression error. Thus, simpler ADX with smaller CR can be
used such as the 7-bit or 6-bit temporal compressor shown in
Fig. 7(a), which further relaxes FH bandwidth requirement. On
the other hand, an extreme scenario toward ENoB reduction is
MIMO systems with few-bit (e.g., 1~3-bit) data converters [53,
54]. The ADX design for such scenario is an interesting
research direction.
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Lightwave Technology
8
RF chain Fiber delay
ADX (one-way) =196.15µs
line coding+GTY
Fiber BtB
40km
ADX latency
(131ns) (T rigger pulse)
Line coding (16ns)
In this work, we focus on ADX-RoF in uplink fronthaul,
considering fading, noise, and DAC/ADC effects. For the
downlink on the other hand, if BBU-side digital precoding and
Option 8 split are assumed, in principle MIMO data
compression can be modelled as a problem of multivariate
compression [23]. In this case, similar ADX technique is also
applicable for downlink, and the achievable CR depends on the
number of MIMO layers, specific precoding technique and
modulation order. Compared with the uplink, the spatial
compression in the downlink may not be done blindly, since
BBU already possesses MIMO channel information via
reference signals. Detailed investigation of downlink ADX-
RoF will be a subject of future work.
V. CONCLUSION
RoF technologies have been actively investigated in the
application of FH in C-RAN. Targeting 5G and beyond FH, this
paper focuses on an ADX-RoF solution based on low-latency
MIMO data compression, from a hardware design perspective.
We have proposed and discussed in detail the ADX hardware
design, which targets low-latency, high-throughput, high-
fidelity, and large-scale MIMO support. With the newly-
designed ADX prototyped on a single-chip field-programmable
radio platform, we have succeeded in real-time 16-channel
MIMO radio reception, ADX processing and RoF transport,
where the ≈4Gb/s OOK signal encapsulates 1024QAM radio
signals with 5G-NR-class bandwidth at a compression ratio of
13.3%. The decompressed EVM after 40km transport is well
below 3GPP 1024QAM threshold, while one-way ADX latency
overhead (including compression and decompression latency)
was <500ns. The real-time demonstration results have shown a
good potential of ADX-RoF for next-generation FH, as well as
other applications such as dedicated indoor access network
based on distributed antenna system (DAS) [48].
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