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EECS150 - Digital Design: Lecture 28 - More Flip-Flops
EECS150 - Digital Design: Lecture 28 - More Flip-Flops
Spring 2003
EECS150 Lec28-FFs
Page 1
If both R=0 & S=0, then cross-couped NORs equivalent to a stable latch:
00 01 10 11
NOR 1 0 0 0
0 R
Q 0 1 Q' 1 0
S 0 1 0
Spring 2003 EECS150 Lec28-FFs
QQ' 01
QQ' 10
SR Latch:
SR 00 01 10 11 Q hold 0 1 indeterminate
SR=01
QQ' 00
SR=00
SR=10
Spring 2003
EECS150 Lec28-FFs
Page 4
Level-sensitive SR Latch
The input C works as an enable signal, latch only changes output when C is high. usually connected to clock. Generally, it is not a good idea to use a clock as a logic signal (into gates etc.). This is a special case.
Spring 2003 EECS150 Lec28-FFs Page 5
D-latch
Spring 2003
EECS150 Lec28-FFs
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Flip-flops
Spring 2003
EECS150 Lec28-FFs
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J-K FF
Add logic to eliminate indeterminate action of RS FF. New action is toggle J = jam clk K = kill
J K Q
JK 00 00 01 01 10 10 11 11
Spring 2003
EECS150 Lec28-FFs
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Spring 2003
EECS150 Lec28-FFs
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Spring 2003
EECS150 Lec28-FFs
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A B
reset FF FA c s
Spring 2003 EECS150 Lec28-FFs
R
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S Q R
Spring 2003
EECS150 Lec28-FFs
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