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C 7
C 7
=>sai số = 10%
b.
.EQU P_OUT=0
.ORG 0
RJMP MAIN
.ORG 0X40
MAIN: LDI R16,HIGH(RAMEND)
OUT SPH,R16
LDI R16,LOW(RAMEND)
OUT SPL,R16
LDI R16,(1<<P_OUT)
OUT DDRA,R16
LDI R17,24
OUT OCR0A,R17
LDI R17,0X02
OUT TCCR0A,R17
LDI R17,0X02
OUT TCCR0B,R17
START:
SBIS TIFR0,OCF0A
RJMP START
SBI TIFR0,OCF0A
OUT TIFR0,R17
IN R17,PORTA
EOR R17,R16
OUT PORTA,R17
RJMP START
=>SAI SỐ=0%
2C.
=>sai số 0%
2d.
.EQU P_OUT=0
.ORG 0
RJMP MAIN
.ORG 0X40
MAIN: LDI R16,HIGH(RAMEND)
OUT SPH,R16
LDI R16,LOW(RAMEND)
OUT SPL,R16
LDI R16,(1<<P_OUT)
OUT DDRA,R16
LDI R17,249
OUT OCR0A,R17
LDI R17,0X02
OUT TCCR0A,R17
LDI R17,0X02
OUT TCCR0B,R17
LOOP:LDI R19,20
START:
SBIS TIFR0,OCF0A
RJMP START
SBI TIFR0,OCF0A
DEC R19
CPI R19,0
BRNE START
OUT TIFR0,R17
IN R17,PORTA
EOR R17,R16
OUT PORTA,R17
RJMP LOOP
SAI SỐ =0%
5A.
.ORG 0
OUT SPH,R16
LDI R16,LOW(RAMEND)
OUT SPL,R16
LDI R16,(1<<P_OUT)
OUT DDRA,R16
LDI R17,0X00
OUT TCCR0A,R17
LDI R17,0X00
OUT TCCR0B,R17
START:
SBI PORTA,0
RCALL DELAY1
CBI PORTA,0
RCALL DELAY2
RJMP START
DELAY1:
LDI R17,-109
OUT TCNT0,R17
LDI R17,0X03
OUT TCCR0B,R17
WAIT1:
IN R17,TIFR0
SBRS R17,TOV0
RJMP WAIT1
OUT TIFR0,R17
LDI R17,0X00
OUT TCCR0B,R17
RET
DELAY2:
LDI R17,-203
OUT TCNT0,R17
LDI R17,0X03
OUT TCCR0B,R17
WAIT2:
IN R17,TIFR0
SBRS R17,TOV0
RJMP WAIT2
OUT TIFR0,R17
LDI R17,0X00
OUT TCCR0B,R17
RET
5B.
.EQU P_OUT=0
.ORG 0
OUT SPH,R16
LDI R16,LOW(RAMEND)
OUT SPL,R16
LDI R16,(1<<P_OUT)
OUT DDRA,R16
LDI R17,0X00
OUT TCCR0A,R17
LDI R17,0X00
OUT TCCR0B,R17
START:
SBI PORTA,0
RCALL DELAY1
CBI PORTA,0
RCALL DELAY2
RJMP START
DELAY1:
LDI R17,0
OUT TCNT0,R17
LDI R17,108
OUT OCR0A,R17
LDI R17,0X02
OUT TCCR0A,R17
LDI R17,0X03
OUT TCCR0B,R17
LOOP1:
SBIS TIFR0,OCF0A
RJMP LOOP1
SBI TIFR0,OCF0A
LDI R17,0
OUT TCCR0B,R17
RET
DELAY2:
LDI R17,0
OUT TCNT0,R17
LDI R17,202
OUT OCR0A,R17
LDI R17,0X02
OUT TCCR0A,R17
LDI R17,0X03
OUT TCCR0B,R17
LOOP2:
SBIS TIFR0,OCF0A
RJMP LOOP2
SBI TIFR0,OCF0A
LDI R17,0
OUT TCCR0B,R17
RET
8a.
8B.
.EQU P_OUT=0
.EQU TF=-15625
.ORG 0X00
MAIN: LDI R16,HIGH(RAMEND)
OUT SPH,R16
LDI R16,LOW(RAMEND)
OUT SPL,R16
LDI R16,(1<<P_OUT)
OUT DDRC,R16
SBI PORTC,1
CBI DDRB,0
SBI PINB,0
SBI PORTB,0
LDI R17,0X00
STS TCCR1A,R17
LDI R17,0X00
STS TCCR1B,R17
LOOP:
SBIC PINB, 0
RJMP LOOP
SBI PORTC,0
RCALL DELAY
CBI PORTC,0
RJMP LOOP
DELAY:
LDI R17,HIGH(TF)
STS TCNT1H,R17
LDI R17,LOW(TF)
STS TCNT1L,R17
LDI R17,0X05
STS TCCR1B,R17
WAIT: IN R17,TIFR1
SBRS R17,TOV1
RJMP WAIT
OUT TIFR1,R17
LDI R17,0X00
STS TCCR1B,R17
RET
Chọn chia tần :(clkI/O)/8
=>CS[2:0]=010
clkTimer=1Mhz
=>1 count =1us
=>tdelay1=40us=40 counts
=>tdelay2=55us=55 counts
=>tdelay3=70us=70 counts
=>tdelay4=85us=85 counts
=>tdelay5=100us=100 counts
.EQU P_OUT=0
.ORG 0
OUT SPH,R16
LDI R16,LOW(RAMEND)
OUT SPL,R16
LDI R16,(1<<P_OUT)
OUT DDRA,R16
LDI R17,0X00
OUT TCCR0A,R17
LDI R17,0X00
OUT TCCR0B,R17
START:
SBI PORTA,0
RCALL DELAY1
CBI PORTA,0
RCALL DELAY2
SBI PORTA,0
RCALL DELAY3
CBI PORTA,0
RCALL DELAY4
SBI PORTA,0
RCALL DELAY5
CBI PORTA,0
RCALL DELAY2
RJMP START
DELAY1:
LDI R17,0
OUT TCNT0,R17
LDI R17,39
OUT OCR0A,R17
LDI R17,0X02
OUT TCCR0A,R17
LDI R17,0X02
OUT TCCR0B,R17
LOOP1:
SBIS TIFR0,OCF0A
RJMP LOOP1
SBI TIFR0,OCF0A
LDI R17,0
OUT TCCR0B,R17
RET
DELAY2:
LDI R17,0
OUT TCNT0,R17
LDI R17,54
OUT OCR0A,R17
LDI R17,0X02
OUT TCCR0A,R17
LDI R17,0X02
OUT TCCR0B,R17
LOOP2:
SBIS TIFR0,OCF0A
RJMP LOOP2
SBI TIFR0,OCF0A
LDI R17,0
OUT TCCR0B,R17
RET
DELAY3:
LDI R17,0
OUT TCNT0,R17
LDI R17,79
OUT OCR0A,R17
LDI R17,0X02
OUT TCCR0A,R17
LDI R17,0X02
OUT TCCR0B,R17
LOOP3:
SBIS TIFR0,OCF0A
RJMP LOOP3
SBI TIFR0,OCF0A
LDI R17,0
OUT TCCR0B,R17
RET
DELAY4:
LDI R17,0
OUT TCNT0,R17
LDI R17,84
OUT OCR0A,R17
LDI R17,0X02
OUT TCCR0A,R17
LDI R17,0X02
OUT TCCR0B,R17
LOOP4:
SBIS TIFR0,OCF0A
RJMP LOOP4
SBI TIFR0,OCF0A
LDI R17,0
OUT TCCR0B,R17
RET
DELAY5:
LDI R17,0
OUT TCNT0,R17
LDI R17,99
OUT OCR0A,R17
LDI R17,0X02
OUT TCCR0A,R17
LDI R17,0X02
OUT TCCR0B,R17
LOOP5:
SBIS TIFR0,OCF0A
RJMP LOOP5
SBI TIFR0,OCF0A
LDI R17,0
OUT TCCR0B,R17
RET