PWM Programming

and DC Motor
Control
Part 2
LECTURE# 23

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 1

Last Lecture
Stepper Motor Interfacing and Programming
◦ Clockwise and Counter-clockwise rotation control

DC Motor Interfacing – Direction Control

◦ Using H-Bridge Circuit, assembly program example
◦ Using H-Bridge IC (L298N), assembly program example

DC Motor Interfacing – Speed Control – Pulse Width Modulation (PWM)

◦ Circuit using BJT or FET and Opto-isolator
◦ PWM example using CPU (assembly)
◦ PWM using Timers – Fast PWM mode
◦ Non-inverted PWM – 0% duty cycle is not possible
◦ Inverted PWM – 100% duty cycle is not possible

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 2

PWM using AVR (revise)
Timer0 and Timer2
TCNT0 Bottom
FOC0
TCNT0 Top
PORTB.3 0
OC0
TCNT0 (PB3)
1
=
Wave Generator
Comparator
OCR0 DDRB.3

OCF0

WGM01 WGM00 COM01 COM00

TCNT2 Bottom
FOC2
TCNT2 Top
PORTD.7 0
OC2
TCNT2 (PD7)
1
=
Wave Generator
Comparator
OCR2 DDRD.7

OCF2

WGM21 WGM20 COM21 COM20

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 3

 Fast Mode Timer0 (revise)
Timer counts like in Normal Mode WGM00 WGM01 Mode
0 0 Normal
◦ From 0 to 255 0 1 CTC
◦ When 255 (sets TOV0 flag) and rolls over to 0 1 0 Phase Correct PWM
1 1 Fast PWM
TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00

COM01 COM00 Mode Description CS02:00 Clock Selected

0 0 Disconnected Normal port operation, OC0 disconnected 000 Stopped
0 1 Reserved Reserved 001 Clk
1 0 Non-inverted PWM Clear OC0 on compare match, set OC0 at TOP 010 Clk/8
1 1 Inverted PWM Set OC0 on compare math, clear OC0 at TOP 011 Clk/64
100 Clk/256
101 Clk/1024
110 External, Falling edge
111 External, Rising Edge

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 4

Fast PWM Timer0 cont. (revise)
Non-inverted and
inverted PWM output
◦ For various values of
OCR0
𝐹
◦ 𝐹𝑃𝑊𝑀 = 256 ×𝑜𝑠𝑐𝑖𝑙𝑙𝑎𝑡𝑜𝑟
𝑝𝑟𝑒𝑠𝑐𝑎𝑙𝑎𝑟

Limitations??
◦ Non-inverted
◦ 0% duty not possible
◦ inverted
◦ 100% duty not possible

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 5

Fast PWM Timer0 cont. (revise)
The following figure
◦ Shows inverted mode
◦ The output is zero up till
◦ OCR0 +1 cycles
◦ The output is high
◦ 255-OCR0 cycles

So Duty cycle (non inverted)

𝑂𝐶𝑅0+1
◦ = 256
× 100% ;Cannot achieve 0% duty cycle

And Duty cycle (inverted)

255−𝑂𝐶𝑅0
◦ = 256
× 100% ;Cannot achieve 100% duty cycle

Assume 𝐹𝑜𝑠𝑐 = 8 𝑀𝐻𝑧, generate

◦ non-inverted PWM of 3906.25 Hz with duty cycle of 37.5%
◦ Do again for inverted PWM

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 6

Loading Value in OCRn
In CTC and Normal mode
◦ Values are loaded directly into OCRn

But in Fast or Phase-Correct PWM mode

◦ There is a buffer in which new value is
loaded
◦ The buffer is loaded into OCRn, when
TCNTn reaches maximum value

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 7

Example 11
Draw the waveform generated by the following code
RJMP MAIN
.ORG 0x16
NEG R20
OUT OCR0,R20
RETI

MAIN:
LDI R16,HIGH(RAMEND)
OUT SPH,R16
LDI R16,LOW(RAMEND)
OUT SPL,R16
SBI DDRB,3
LDI R20,99
OUT OCR0,R20
LDI R16,0x69
OUT TCCR0,R16
OUT OCR0,R20
LDI R16,(1<<TOIE0)
OUT TIMSK,R16
SEI
HERE: RJMP HERE

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 8

Example 11
Draw the waveform generated by the following code
RJMP MAIN
.ORG 0x16 ;Timer0 overflow interrupt vector
NEG R20 ;Negative R20
OUT OCR0,R20 ;OCR0 = R20
RETI ;return interrupt

MAIN:
LDI R16,HIGH(RAMEND)
OUT SPH,R16
LDI R16,LOW(RAMEND)
OUT SPL,R16 ;initialize stack
SBI DDRB,3 ;OC0 as output
LDI R20,99 ;R20 = 99
OUT OCR0,R20 ;OCR0 = 99
LDI R16,0x69 ;Fast PWM mode, non-inverted, no prescaler
OUT TCCR0,R16
OUT OCR0,R20 ;OCR0 buffer = 99
LDI R16,(1<<TOIE0) ;enable overflow interrupt non-inverted Fast PWM mode
OUT TIMSK,R16 • On compare match OC0 -> High
SEI ;enable global interrupt • On overflow OC0-> Low
HERE: RJMP HERE ;wait here
NEG(99) = 157
NEG(157) = 99

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 9

Phase Correct PWM
Goes Up and down
◦ TOV is set when reached 0

Counts
◦ 0, 1, 2, …, 254,
◦ 255,
◦ 254, … , 2, 1, 0
◦ (total 510 cycles)

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 10

Phase Correct (non-inverted)
𝐹𝑜𝑠𝑐
𝐹𝑃𝑊𝑀 =
510×𝑝𝑟𝑒𝑠𝑐𝑎𝑙𝑎𝑟

2×𝑂𝐶𝑅0 𝑂𝐶𝑅0
Duty Cycle = × 100 ⇒ Duty cycle = × 100
510 255

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 11

Phase Correct (inverted)
510−2×𝑂𝐶𝑅0 255−𝑂𝐶𝑅0
Duty Cycle = × 100 ⇒ Duty cycle = × 100
510 255

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 12

Phase Correct cont.
This is slower, than Fast PWM mode. But provide 0% to 100% duty cycle

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 13

Timer2 and Timer1 PWM
Timer2 usage is similar when generating PWM
◦ On OC2 (PD7) pin

Timer1 however can generate two PWMs

◦ On pins OC1A (PD5) and OC1B (PD4)
◦ As two comparator registers are available OCR1A and OCR1B

On Atmega328
◦ All timers can generate two PWMs
◦ As all timers have two different OCRnA and OCRnB registers
◦ Generating PWMs on OCnA and OCnB

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 14

Testing your knowledge
Write an assembly program that generates Fast PWM
◦ Controlled by two switches
◦ SW1 (increase duty cycle) connected to PC0 (when switch is pressed PC0=0)
◦ SW2 (decrease duty cycle) connected to PC1 (when switch is pressed PC1=0)

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 15

Serial Peripheral
Interfacing (SPI)

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 16

Introduction
Wire Name Alternate Pin Names
A synchronous serial
communication protocol Master Slave
MOSI (Master Out Slave In) SDO (Serial Data Out) SDI
Singe master multiple slaves
MISO (Master In Slave Out) SDI (Serial Data In) SDO
◦ Master controls the clock
SCL (Serial Clock) SCLK SCLK
Four-wire interface SS (Slave Select) CE (Chip Enable)/SS CE/SS
◦ May also be three
◦ When not using SS pin MASTER
SDO
MOSI
SDI
MISO
SDI SDO
SCL
Number of pins increase with SS3 SS2 SS1
SCLK SCLK

slaves SS SLAVE1

◦ One SS pin for each slave (SS1, SS2 SDI

SDO
,,, SSn) SCLK

SLAVE2
At a time, the master SS

communicates with only one slave SDI

SDO
SCLK

SS SLAVE3

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 17

SPI Protocol
Master and Slaves have shift registers
◦ Usually 8-bit shift registers
In each transaction
◦ !SS is brought to zero (active low)
◦ Master and a Slave exchange data in the
shift registers
◦ Eight clock pulses required
When Master wants to write a byte
◦ It places data it in its shift register
◦ Gives 8 clock pulses and the data goes to
slave
When Master wants the read a byte
◦ Master provides 8 clock cycles
◦ Master reads its shift register

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 18

SPI Communication
In addition to the shift register, each slave has multiple data registers
◦ The master can write or read each of these registers
◦ Each of these data registers have unique address
When Reading a data register
◦ The Master sends the address of the data register (along with R/W bit)
◦ The slave places the data in its shift register
◦ Master shift the data into its own shift register
When Master wants to write data
◦ The Master sends the address of the data register (along with R/W bit)
◦ The Master sends the data to be written
◦ The slave copies the receive data from shift register to data register
SPI allows reading or writing multiple consecutive data registers of slave
◦ Using Burst Read or write mode

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 19

SPI Clock Phase and Polarity
The data in the shift registers is
◦ Sampled, and,
◦ Changed on different edges

These edges can be defined

◦ As four modes of SPI
◦ Configured by CPOL and CPHA

CPOL defines that

◦ The leading edge is
◦ Rising (0) or falling (1)
CPOL CPHA SPI Mode
CPHA defines 0 0 0
◦ The data is sampled on 0 1 1
◦ Leading(0) or trailing (1) edge 1 0 2
1 1 3

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 20

Single Byte Write
The Steps in writing a byte
1. Make CE = 0 (SS=0), to begin writing
2. 8-bit address is sent by the Master (one bit at a time in each clock cycle)
a. 1-bit R/W = 1 for writing
b. 7-bit address of the data register of the slave
3. Slave now expects the data (to be written to the data register) from master
4. 8-bits of data is sent by the master (one bit at a time in each clock cycle)
5. Make CE=1 (SS=1), indicating end of write cycle

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 21

Multibyte Burst write
Allows to write multiple registers (at consecutive locations)
1) Address of the first register is the sent by the master
2) Master sends data to write, for following registers (total 𝑛)
◦ Addr
◦ Addr + 1
◦ Addr + 2, to
◦ Addr + (𝑛 − 1)

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 22

Single Byte Read
1. Make CE = 0 (SS=0), to begin reading
2. 8-bit address is sent by the Master (one bit at a time in each clock cycle)
a. 1-bit R/W = 0 for reading
b. 7-bit address of the data register of the slave
3. Slave now copies the data from the data register to the shift register
a. Waits for the master the read the data
4. 8-bits of data is received by the master (one bit at a time in each clock cycle)
5. Make CE=1 (SS=1), indicating end of read cycle

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 23

Multibyte Burst Read
Allows to read multiple registers (at consecutive locations)
1) Address of the first register is the sent by the master
2) Slave sends data to master, of following registers (total 𝑛)
◦ Addr
◦ Addr + 1
◦ Addr + 2, to End of Lecture
◦ Addr + (𝑛 − 1)

Saad Arslan COMSATS UNIVERSITY ISLAMABAD 24