Serial Peripheral

Interfacing (SPI)
Programming in
AVR
LECTURE# 24
MICROPROCESSOR SYSTEMS AND INTERFACING

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 Quiz 3 UCSR0A

UCSR0B
RXC0

RXCIE0
TXC0

TXCIE0
UDRE0

UDRIE0 RXEN0
FE0 DOR0

TXEN0
UPE0

UCSZ02
U2X0

RXB80
MPCM0

TXB80

UART UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0

UCSZ0[2:0] Character Size UMSEL0[1:0] Mode Vector Program

Source Interrupt Definition
No. Address
000 5-bit 00 Asynchronous USART
19 0x0024 USART_RX USART Rx Complete
001 6-bit 01 Synchronous USART 20 0x0026 USART_UDRE USART, Data Register Empty
010 7-bit 10 (Reserved) 21 0x0028 USART_TX USART, Tx Complete
011 8-bit 11 Master SPI (MSPIM)
111 9-bit
𝐵𝑎𝑢𝑑𝑅𝑎𝑡𝑒 = 𝐹𝑜𝑠𝑐 / 16 ∗ 𝑋 + 1 , when U2X0 = 0

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 Quiz 3 UCSR0A

UCSR0B
RXC0

RXCIE0
TXC0

TXCIE0
UDRE0

UDRIE0 RXEN0
FE0 DOR0

TXEN0
UPE0

UCSZ02
U2X0

RXB80
MPCM0

TXB80

UART UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0

You have an AVR ATmega328p running at 11.0592 MHz. Configure the USART
module for receiving asynchronous mode at 57600 baud rate, 6-bit data, 1-stop bit,
no parity and receive interrupts enable.
1. Write the values in binary for UCSR0A,UCSR0B, UCSR0C, UBRR0H and UBRR0L
2. Role of Flags
a) Which flag will be set when a data is received.
b) Which flag is set when invalid frame is received
c) Which flag is set when data is received repeatedly, but UDR is not read in the code.
3. Write an assembly program which receives data and stores to SRAM location 0x300

UCSZ0[2:0] Character Size UMSEL0[1:0] Mode Vector Program

Source Interrupt Definition
No. Address
000 5-bit 00 Asynchronous USART
19 0x0024 USART_RX USART Rx Complete
001 6-bit 01 Synchronous USART 20 0x0026 USART_UDRE USART, Data Register Empty
010 7-bit 10 (Reserved) 21 0x0028 USART_TX USART, Tx Complete
011 8-bit 11 Master SPI (MSPIM)
111 9-bit
𝐵𝑎𝑢𝑑𝑅𝑎𝑡𝑒 = 𝐹𝑜𝑠𝑐 / 16 ∗ 𝑋 + 1 , when U2X0 = 0

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Last Lecture
Fast PWM revision
Fast PWM AVR examples
Phase correct PWM

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Introduction
Wire Name Alternate Pin Names
A synchronous serial
communication protocol Master Slave
MOSI (Master Out Slave In) SDO (Serial Data Out) SDI
Singe master multiple slaves
MISO (Master In Slave Out) SDI (Serial Data In) SDO
◦ Master controls the clock
SCL (Serial Clock) SCLK SCLK
Four-wire interface SS (Slave Select) CE (Chip Enable)/SS CE/SS
◦ May also be three
◦ When not using SS pin MASTER
SDO
MOSI
SDI
MISO
SDI SDO
SCL
Number of pins increase with SS3 SS2 SS1
SCLK SCLK

slaves SS SLAVE1

◦ One SS pin for each slave (SS1, SS2 SDI

SDO
,,, SSn) SCLK

SLAVE2
At a time, the master SS

communicates with only one slave SDI

SDO
SCLK

SS SLAVE3

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SPI Protocol
Master and Slaves have shift registers
◦ Usually 8-bit shift registers
In each transaction
◦ !SS is brought to zero (active low)
◦ Master and a Slave exchange data in the
shift registers
◦ Eight clock pulses required
When Master wants to write a byte
◦ It places data it in its shift register
◦ Gives 8 clock pulses and the data goes to
slave
When Master wants the read a byte
◦ Master provides 8 clock cycles
◦ Master reads its shift register

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SPI Communication
In addition to the shift register, each slave has multiple data registers
◦ The master can write or read each of these registers
◦ Each of these data registers have unique address
When Reading a data register
◦ The Master sends the address of the data register (along with R/W bit)
◦ The slave places the data in its shift register
◦ Master shift the data into its own shift register
When Master wants to write data
◦ The Master sends the address of the data register (along with R/W bit)
◦ The Master sends the data to be written
◦ The slave copies the receive data from shift register to data register
SPI allows reading or writing multiple consecutive data registers of slave
◦ Using Burst Read or write mode

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SPI Clock Phase and Polarity

The data in the shift registers is
◦ Sampled, and,
◦ Changed on different edges

These edges can be defined

◦ As four modes of SPI
◦ Configured by CPOL and CPHA

CPOL defines that

◦ The leading edge is
◦ Rising (0) or falling (1)
CPOL CPHA SPI Mode
CPHA defines 0 0 0
◦ The data is sampled on 0 1 1
◦ Leading(0) or trailing (1) edge 1 0 2
1 1 3

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Single Byte Write

The Steps in writing a byte
1. Make CE = 0 (SS=0), to begin writing
2. 8-bit address is sent by the Master (one bit at a time in each clock cycle)
a. 1-bit R/W = 1 for writing
b. 7-bit address of the data register of the slave
3. Slave now expects the data (to be written to the data register) from master
4. 8-bits of data is sent by the master (one bit at a time in each clock cycle)
5. Make CE=1 (SS=1), indicating end of write cycle

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Multibyte Burst write

Allows to write multiple registers (at consecutive locations)
1) Address of the first register is the sent by the master
2) Master sends data to write, for following registers (total 𝑛)
◦ Addr
◦ Addr + 1
◦ Addr + 2, to
◦ Addr + (𝑛 − 1)

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Single Byte Read

1. Make CE = 0 (SS=0), to begin reading
2. 8-bit address is sent by the Master (one bit at a time in each clock cycle)
a. 1-bit R/W = 0 for reading
b. 7-bit address of the data register of the slave
3. Slave now copies the data from the data register to the shift register
a. Waits for the master the read the data
4. 8-bits of data is received by the master (one bit at a time in each clock cycle)
5. Make CE=1 (SS=1), indicating end of read cycle

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End of Last Lecture

Multibyte Burst Read

Allows to read multiple registers (at consecutive locations)
1) Address of the first register is the sent by the master
2) Slave sends data to master, of following registers (total 𝑛)
◦ Addr
◦ Addr + 1
◦ Addr + 2, to
◦ Addr + (𝑛 − 1)

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 SPI Programming in AVR
On ATmega328p
Atmega16 along with most of its family WCOL is bit6 of instead of bit1 of SPSR
members support SPI
Three registers of ATmega16 are used for SPI
interfacing
1. SPSR (SPI Status Register)
2. SPCR (SPI Control Register)
3. SPDR (SPI Data Register)
1. Contains data to be transmitted or received data
2. Consider it the shift register (however it is the buffer)
SPSR SPIF - - - - - WCOL SPI2X
SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0
SPDR D7 D6 D5 D4 D3 D2 D1 D0

WCOL Write Collision flag (SPDR is overwritten) SPR1 SPR0

SPI2X Double clock rate 0 0 Fosc/4
DORD Data Order (MSB first (0) or LSB first(1)) 0 1 Fosc/16
CPOL Clock Polarity 1 0 Fosc/64
CPHA Clock Phase 1 1 Fosc/128

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 PD2
PD1
PD0
PC6
PC5
PC4
PC3
PC2
SPI Programming

32
31
30
29
28
27
26
25
PD3 1 24 PC1

ATmega328p PD4
GND
VCC
GND
2
3
4
5 32 TQFP
23
22
21
20
PC0
ADC7
GND
AREF
VCC 6 19 ADC6
Try to find the SPI pins on SPDIP package PB6 7 18 AVCC
PB7 8 17 PB5

10
11
12
13
14
15
16
9

PD7

PB2
PD5
PD6

PB0

PB3
PB4
PB1
28 SPDIP
(PCINT14/RESET) PC6 1 28 PC5 (ADC5/SCL/PCINT13)
(PCINT16/RXD) PD0 2 27 PC4 (ADC4/SDA/PCINT12)
(PCINT17/TXD) PD1 3 26 PC3 (ADC3/PCINT11)
(PCINT18/INT0) PD2 4 25 PC2 (ADC2/PCINT10)
(PCINT19/OC2B/INT1) PD3 5 24 PC1 (ADC1/PCINT9)
(PCINT20/XCK/T0) PD4 6 23 PC0 (ADC0/PCINT8)
VCC 7 22 GND
GND 8 21 AREF
(PCINT6/XTAL1/TOSC1) PB6 9 20 AVCC
(PCINT7/XTAL2/TOSC2) PB7 10 19 PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5 11 18 PB4 (MISO/PCINT4)
(PCINT22/OC0A/AIN0) PD6 12 17 PB3 (MOSI/OC2A/PCINT3)
(PCINT23/AIN1) PD7 13 16 PB2 (SS/OC1B/PCINT2)
(PCINT0/CLKO/ICP1) PB0 14 15 PB1 (OC1A/PCINT1)

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SPI Programming in AVR cont.
The AVR can be used as SPI master or slave
◦ By setting or clearing the MSTR bit of SPCR (SPI Control Register), respectively

The direction of the pins (SCK and SS) is configure accordingly

◦ When SS pin is output in Master Mode
◦ The Hardware circuitry automatically controls it to communicate with slaves
◦ If SS is input in Master mode
◦ And external circuitry makes it low
◦ The AVR will go into SPI slave mode (clearing the MSTR bit)
◦ Upon SS going high again will not make the AVR SPI master

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Example 17-1 (SPI Master)
Write an AVR Program to initialize the SPI for master mode 0 with SCLK frequency
=Fosc/16 and then transmit ‘G’ via SPI repeatedly. The received data should be displayed
on Port A.

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Example 17-2 (SPI Slave)
Write and AVR Program to initialize the SPI for slave mode 0 with SCLK frequency =Fosc/16
and then transmit ‘G’ via SPI repeatedly. The received data should be displayed on Port A.

The slave will not initiate the transfer, it will transmit ‘G’ only when the Master wants to read.
Also the clock will be controlled by the Master, so no need to configure the clock source

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Example 17-1 in C

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Example 17-2 in C

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An Application of SPI
MAX7221 for driving Multiple 7segments

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An Application of SPI
MAX7221 – Packet Format
MAX7221 for driving Multiple 7segments

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An Application of SPI
MAX7221 – Packet Format
MAX7221 for driving Multiple 7segments

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An Application of SPI
MAX7221 – List of Commands
MAX7221 for driving Multiple 7segments

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