Interrupts

LECTURE# 13
MICROPROCESSOR SYSTEMS AND INTERFACING

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Last Lecture
AVR Timers
◦ Timer0 Normal and CTC mode
◦ Timer2
◦ Timer1 theory only
◦ Using timers as counters

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What are interrupts
Is a signal (generated by hardware or software) to processor telling
◦ That an event needs attention
Allows μC/μP to effectively service multiple devices
There are two methods of servicing multiple devices
◦ Polling
◦ Keep polling/checking all the devices if any needs service
◦ Interrupts
◦ CPU performs normal routine
◦ if a device needs service, the control automatically transfers to service

Consider the timers

◦ TOV or OCF flag is polled continuously
◦ Keeps the CPU busy and CPU cannot perform any other task

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Interrupt Service Routine (ISR)
ISR is the service perform by the CPU
◦ in response to an interrupt call
◦ The service required by the device
◦ Example, what happens when timer overflow?

In our case
◦ ISR is a subroutine, executed only when particular interrupt occurs

Required by every interrupt that will be serviced

ISR is pointed by Interrupt Vector Table

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ATmega328
Interrupt Vector Table
Vector Program
Source Interrupt Definition
There can be multiple No. Address
External Pin, Power-on Reset, Brown-out Reset and
possible interrupts, like 1 0x0000 RESET
Watchdog System Reset
2 0x0002 INT0 External Interrupt Request 0
◦ Timer overflow or compare 3 0x0004 INT1 External Interrupt Request 1
4 0x0006 PCINT0 Pin Change Interrupt Request 0
match 5 0x0008 PCINT1 Pin Change Interrupt Request 1
6 0x000A PCINT2 Pin Change Interrupt Request 2
◦ Serial data received or 7 0x000C WDT Watchdog Time-out Interrupt
transmitted 8 0x000E TIMER2_COMPA Timer/Counter2 Compare Match A
9 0x0010 TIMER2_COMPB Timer/Counter2 Compare Match B
◦ Some pin changed on a port 10
11
0x0012
0x0014
TIMER2_OVF
TIMER1_CAPT
Timer/Counter2 Overflow
Timer/Counter1 Capture Event
◦ ADC conversion completed 12
13
0x0016
0x0018
TIMER1_COMPA
TIMER1_COMPB
Timer/Counter1 Compare Match A
Timer/Counter1 Compare Match B

◦ SPI, I2C 14
15
0x001A
0x001C
TIMER1_OVF
TIMER0_COMPA
Timer/Counter1 Overflow
Timer/Counter0 Compare Match A
16 0x001E TIMER0_COMPB Timer/Counter0 Compare Match B

Interrupt Vector Table points 17

18
0x0020
0x0022
TIMER0_OVF
SPI_STC
Timer/Counter0 Overflow
SPI Serial Transfer Complete
to specific ISR for a particular 19
20
0x0024
0x0026
USART_RX
USART_UDRE
USART Rx Complete
USART, Data Register Empty
interrupt 21 0x0028 USART_TX USART, Tx Complete
22 0x002A ADC ADC Conversion Complete
23 0x002C EE_READY EEPROM Ready
24 0x002E ANALOG_COMP Analog Comparator
25 0x0030 TWI 2-wire Serial Interface
26 0x0032 SPM_Ready Store Program Memory Ready

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 Servicing an Interrupt
1. It finishes executing current instruction, and stores address of the next
instruction in stack (Like CALL)
2. It jumps to a fixed location in memory called the Interrupt Vector Table
a. Interrupt Vector Table points to the address of ISR
3. Microcontroller starts to execute ISR
a. until it reaches end, which is RETI (Return from Interrupt) instruction
4. Upon executing RETI, the microcontroller returns to the place where it was
interrupted
• POPs the address from stack and updates Program Counter (PC).
5. The microcontroller resumes the execution of Normal routine
(1)
Interrupt Signal (2)
Received
(3)

Main code Resume main Interrupt Service

execution code execution Routine Execution
(5)
(4)

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Enabling Interrupts
Bit 7 6 5 4 3 2 1 0

First Global Interrupt is enabled 0x3F (0x5F) I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
◦ Using I bit in SREG Initial Value 0 0 0 0 0 0 0 0

C – Carry flag S – Sign flag

◦ Enable using SEI, Z – Zero flag H – Half carry
◦ disable using CLI instruction N – Negative Flag T – Bit copy storage
V – Overflow flag I – Global interrupt enable
Then Particular Interrupt is enabled
◦ Some register contains bits for enabling particular interrupts
◦ Like TIMSKn shown here Bit 7 6 5 4 3 2 1 0

(0x6E) – – – – – OCIE0B OCIE0A TOIE0 TIMSK0

◦ Used for Timer 0, 1 & 2 Interrupts
(0x6F) – – ICIE1 – – OCIE1B OCIE1A TOIE1 TIMSK1

(0x70) – – – – – OCIE2B OCIE2A TOIE2 TIMSK2

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Programming Interrupts
Write Assembly program to use Timer0 Overflow interrupt
What happens when timer overflows?
◦ How is it utilized? Interrupt Vector Table?

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 ATmega328 Timer0 Normal Mode
using Polling and Interrupt (cont.)
.ORG 0x00; location for reset
LDI R16, 1<<5 ;R16 = 0b0010 0000 RJMP MAIN
SBI DDRB, 5 ;PB5 as an output .ORG 0x20; location of Timer0 overflow TIMER0_OVF
LDI R17, 0 RJMP TOV0_ISR
OUT PORTB, R17 ;clear PORTB polling MAIN:
Interrupts
BEGIN:RCALL DELAY ;call timer delay LDI R16, 1<<5 ;R16 = 0b0010 0000
EOR R17, R16 ;toggle D5 of R1 SBI DDRB, 5 ;PB5 as an output
OUT PORTB, R17 ;toggle PB5 LDI R17, 0
RJMP BEGIN OUT PORTB, R17 ;clear PORTB
;-------------------------------Timer0 delay LDI R20, 0xF2 ;R20 = 0xF2
DELAY:LDI R20, 0xF2 ;R20 = 0xF2 OUT TCNT0, R20 ;load timer0
OUT TCNT0, R20 ;load timer0 LDI R20, 0x00
LDI R20, 0x00 OUT TCCR0A, R20 ;Tim0 Normal mode
OUT TCCR0A, R20 ;Tim0 Normal mode LDI R20, 0x01
LDI R20, 0x01 OUT TCCR0B, R20 ;Tim0 Normal mode, int clk
OUT TCCR0B, R20 ;Tim0 Normal mode, int clk LDI R18, 0x01
AGAIN:IN R20, TIFR0 ;read TIFR STS TIMSK0, R18 ; enable tim0 OVF interrupt
SBRS R20, TOV0 ;if TOV0=1,skip nxt inst. SEI ;enable global interrupt
RJMP AGAIN HERE: RJMP HERE
LDI R20, 0x0 .ORG 0x200
OUT TCCR0B, R20 ;stop Timer0 TOV0_ISR:
LDI R20, (1<<TOV0) EOR R17, R16 ;toggle D5 of R1
OUT TIFR0, R20 ;clear TOV0 flag OUT PORTB, R17 ;toggle PB5
RET LDI R20, 0xF2;R20 = 0xF2
OUT TCNT0, R20 ;load timer0
RETI

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 ATmega328 Timer0 CTC mode
Using Polling and Interrupt
LDI R16, 0x08 .ORG 0x00; location for reset
SBI DDRB, 3 ;PB3 as an output RJMP MAIN
LDI R17, 0 polling .ORG 0x1C ; loc. of Timer0 Comp. Match A - OCF0A
BEGIN: OUT PORTB, R17 ;PORTB = R17
RCALLDELAY MAIN:
RJMP OCF0A_ISR Interrupts
EOR R17, R16 ;toggle D3 of R17 LDI R16, 1<<5 ;R16 = 0b0010 0000
RJMPBEGIN SBI DDRB, 5 ;PB5 as an output
;------------------- Timer0 Delay LDI R17, 0
DELAY: LDI R20, 0 OUT PORTB, R17 ;clear PORTB
OUT TCNT0, R20 LDI R20, 0;R20 = 0xF2
LDI R20, 9 OUT TCNT0, R20 ;load timer0
OUT OCR0A, R20 ;load OCR0 LDI R20, 9
LDI R20, 0x02 OUT OCR0A, R20 ;load OCR0A
OUT TCCR0A, R20 ;Timer0, CTC mode LDI R20, 0x02
LDI R20, 0x01 OUT TCCR0A, R20 ;Timer0, CTC mode
OUT TCCR0B, R20 ;Timer0, CTC mode,int clk LDI R20, 0x01
AGAIN: IN R20, TIFR0 ;read TIFR OUT TCCR0B, R20 ;Timer0, CTC mode,int clk
SBRS R20, OCF0A ; skip nxt inst. If OCF=1 LDI R18, 0x02
RJMP AGAIN STS TIMSK0, R18 ;Enable Tim0 OCF0A interrupt
LDI R20, 0x0 SEI ;enable global interrupt
OUT TCCR0B, R20 ;stop Timer0 HERE: RJMP HERE
LDI R20, 1<<OCF0A .ORG 0x200
OUT TIFR0, R20 ;clear OCF0 flag OCF0A_ISR:
HERE: RJMP HERE EOR R17, R16 ;toggle D5 of R1
OUT PORTB, R17 ;toggle PB5
RETI

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RETI and RET
Whenever the CPU starts to execute an ISR
◦ It disables global interrupt (clears I flag in SREG)
◦ But, why?
◦ So that no other source interrupts the CPU

Both (RET and RETI) return to address popped from stack

RETI performs an additional task of setting I flag
◦ I flag is cleared when interrupt occurs
◦ To block new interrupts while servicing one

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External Interrupts
ATmega328
ATmega328p has two dedicated external hardware interrupts
◦ External Interrupt 0 and 1 (INT0 & INT1)
For polling flags, use
◦ Generate interrupt INT0 or INT1, when • EIFR register for INT0 to INT1
◦ Low-level (ISCnx = 00) • PCIFR register for PCINT[23:0]
◦ Falling and rising edge (ISCnx = 01)
◦ Falling edge (ISCnx = 10)
(PCINT14/RESET) PC6 1 28 PC5 (ADC5/SCL/PCINT13)
◦ Rising edge (ISCnx = 11) (PCINT16/RXD) PD0 2 27 PC4 (ADC4/SDA/PCINT12)
◦ Using EICRA register (PCINT17/TXD) PD1 3 26 PC3 (ADC3/PCINT11)
(PCINT18/INT0) PD2 4 25 PC2 (ADC2/PCINT10)
◦ Enable INT1 and/or INT2 in EIMSK register (PCINT19/OC2B/INT1) PD3 5 24 PC1 (ADC1/PCINT9)
(PCINT20/XCK/T0) PD4 6 23 PC0 (ADC0/PCINT8)
◦ Also have three shared interrupts VCC 7 22 GND
GND 8 21 AREF
◦ PCINT[23:16], PCINT[14:8], & PCINT[7:0] (PCINT6/XTAL1/TOSC1) PB6 9 20 AVCC
(PCINT7/XTAL2/TOSC2) PB7 10 19 PB5 (SCK/PCINT5)
◦ Enable through PCICR register (PCINT21/OC0B/T1) PD5 11 18 PB4 (MISO/PCINT4)
◦ Containing PCIE2:0 bits for each interrupt (PCINT22/OC0A/AIN0) PD6 12 17 PB3 (MOSI/OC2A/PCINT3)
(PCINT23/AIN1) PD7 13 16 PB2 (SS/OC1B/PCINT2)
◦ Enable interrupt pins (PCINT0/CLKO/ICP1) PB0 14 15 PB1 (OC1A/PCINT1)

◦ using PCMSK0,1,2 registers

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External Interrupts cont.
INT0 and 1 are enabled by respective bits in EIMSK
◦ EIMSK

INT0 and 1 are configured using

◦ EICRA ISC11 ISC10 ISC01 ISC00

Like TOV0, OCF0 flags, there are INTF0 and INTF1 in EIFR
◦ EIFR
◦ When an external interrupt is generated
◦ The corresponding flag is set
◦ If polling, the flag is manual cleared by writing 1 to it
◦ Means either no external interrupt is enable in EICR or global interrupt is disabled
◦ When using interrupts, the flag is automatically cleared

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External Interrupts cont.
Pin Change Interrupt
◦ Enable using
◦ Flag Register

◦ Interrupt enable on individual pins using

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Interrupt Priority
If two or more interrupts are activated at the same time
◦ The interrupt with higher priority is served first
The address in the Interrupt Vector Table define priorities
◦ Lower addresses have higher priority compared to higher addresses
When an interrupt is being served (ISR being executed)
◦ Any other interrupt activated at that time will not be served
◦ Even if the new interrupt activated has higher priority
◦ The new interrupt will be served after the current ISR is completed
◦ This is because global interrupt is disabled while executing an interrupt
You can manually enable global interrupt in an ISR
◦ To serve new interrupts, but may cause infinite loop
◦ For example, when low-level triggered interrupt is used

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Context saving in multitasking
.INCLUDE "M32DEF.INC"
When multi-tasking, like interrupts .ORG 0x00
JMP MAIN
;location for reset

◦ Resources (registers and status flags) .ORG 0x14 ;location for TimerO compare match
should be managed carefully .ORG 0x100
JMP T0_CM_ISR
;-main program for initialization and keeping CPU busy
MAIN: LDI R20, HIGH(RAMEND)
Resource conflicts can occur OUT
LDI
SPH, R20
R20, LOW(RAMEND)
◦ When main program and ISR uses OUT
SBI
SPL, R20
DDRB, 5
;set up stack
;PB5 as an output
◦ Same registers or status flags LDI R20, (1<<OCIE0)
OUT TIMSK, R20 ;enable Timer0 compare match interrupt
SEI ;set I (enable interrupts globally)
Consider Program 10-4 LDI R20, 160
OUT OCR0, R20 ;load Timer0 with 160
◦ Main program increments R20 LDI R20, 0x09
OUT TCCR0, R20 ;CTC mode, int clk, no prescaler
◦ And write it to PORTC LDI R20, 0xFF
OUT DDRC, R20 ;make PORTC output
◦ ISR copies PIND To R20 increments it OUT DDRD, R20 ;make PORTD output
and writes it to PORTD LDI R20, 0
HERE: OUT PORTC, R20 ;PORTC = R20
◦ Do you see an issue here? INC R20
JMP HERE ;keeping CPU busy waiting for interrupt
.ORG 0x200
So, conflicting resources are copied T0_CM_ISR:
IN R20, PIND
ISR for Timer0 Compare Match

and restored INC R20

OUT PORTD, R20 ;PORTD = R20
RETI ;return from interrupt

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