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IC Interfacing
LECTURE# 25
MICROPROCESSOR SYSTEMS AND INTERFACING

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IC Introduction
A synchronous serial communication protocol
Allows low-speed devices to be inter-connected
Multi-master, multi-slave protocol
◦ One master is active at a time Wire Name Description

◦ Master controls the clock SDA Serial Data/Address

SCL Serial Clock
Two-wire interface (TWI)
◦ Both wires are bi-directional
◦ Number of wires does not increase by increasing the nodes (slaves)

At a time one master communicates with one slave

What if two Masters want to communicate at the same time
◦ Arbitration – will discuss on later slides

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I2C Protocol
I2C lines are pull-up using 4.7 kΩ resistors
◦ Implements a wired-AND
◦ Each Line is HIGH when not driven
VCC

Device 4
Each device has its unique 7-bit address

Device 1

Device 2

Device 3
◦ Some addresses are reserved
◦ Up to 120 devices can share an I2C bus Device Device
Master controls the clock SDA
◦ Starts and ends a transaction SCL

A devices becomes Master at run-time by driving the lines

◦ An arbitration process resolves clashes

It is convenient to add more devices

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I2C Protocol cont.
A device (node) on an I2C bus can have one of the following modes at a
time
◦ Master Transmitter
◦ Master Receiver
◦ Slave Transmitter (when a master is receiving)
◦ Slave Receiver (when a master is transmitting)

A low clock line indicates that data (1-bit) is changing

◦ High clock line indicates that data (1-bit) is stable and can be read (sampled)

Data Data Data

Stable Change Stable

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I2C Protocol
START and STOP conditions
Aside from bits being transmitted and received
Each I2C transaction is
◦ Initiated with a START condition
◦ Ends with STOP condition

When a new transaction is started with end of one, by the same master
◦ A combined STOP-START condition (called RESTART) is used.

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I2C Protocol
Data Transfer
A typical data transfer between a master and a slave has following steps
1. The master initiates a START condition
2. The master sends address packet (specifying the target slave)
3. The master sends or reads data packet to/from slave
4. The master initiates STOP condition

Address packet Data packet

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I2C Protocol
Packet Format
The address or data packet is 9-bits long, whether send or received
◦ Example uses address packet

Transmitter writes the SDA line during the first 8 cycles

◦ Receiver writes acknowledgement, during the 9th cycle

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I2C Protocol
Address Packets
Address packet is transmitted after the start condition
◦ To address the target slave (each slave has its own unique address on the bus)
◦ The 8th bit of the address packet specifies read (1) or write (0) operation

When a slave receives its address, it acknowledges during the 9th bit of
the packet
◦ ACK – Acknowledge – if 9th bit is low (slave drives the line low)
◦ NACK – Not Acknowledge – if 9th bit is high (slave did not drive the line low)

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I2C Protocol
Data Packets
There can be multiple data packets after an address packet
Data packets are also 9-bits wide
◦ First 8-bits from transmitter to receiver
◦ 9-bit acknowledgement bit from receiver to transmitter
◦ If ACK, then transmission continues,
◦ If NACK, either unsuccessful transmission or end of transmission

Address packet Data packet

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I2C Protocol
Clock Stretching
The master controls the clock, however,
◦ The addressed slave can slow down the clock
◦ If the slave is not ready (needs more time to process a request)

A rising edge on SCL occurs when Master releases the line

◦ If the slave is not ready, it will keep the line pulled down
◦ The master will wait for the line to go high
Slave stretches the line Master waits for SCL line to
by pulling SCL low become high

SCL from
Master

SCL from
Slave

SCL Line
Clock line is stretched

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I2C Protocol
Arbitration
I2C supports a multi-master bus system
◦ Only one device is master at a time
Each master waits for current transmission to end
◦ Then, it tries to become Master
If two devices try to become master at the same time, then?
◦ Let's call these devices candidates (for the moment)
◦ A process called arbitration decides which candidate will be MASTER
Each candidate writes and monitors the line
◦ If the value on the line matches the value it wrote,
◦ it continues (to assumes Master role)
◦ If does not match, it loses -> backs off – there is another master which won
During arbitration, no data is lost

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I2C Protocol
Arbitration Example
Assume a scenario where two candidates A and B try to become Master
◦ ‘A’ and ‘B’ wants the access slave at address 0010 000 and 0001 111, respectively

They both will assume they are master

◦ Initiate start condition
◦ Write address on the SDA
First two cycles are same
on SDA
◦ During third cycle
◦ ‘A’ writes 1
◦ ‘B’ writes 0
◦ What will happen to
wired-AND?
◦ SDA will have 0
**Candidate B wins and becomes MASTER
◦ matches ‘B’

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 I2C Example
Master writing a Byte
Master wants to write a byte to slave at address 0110111
◦ The byte to be written is 10101001

START Slave Address R/W ACK Data ACK STOP

0 1 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

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 I2C Example
Master Reading a Byte
Master wants to read a byte from slave at address 0110111
◦ The byte to be read has data 01101101

START Slave Address R/W ACK Data NACK STOP

0 1 1 0 1 1 1 10 0 0 1 1 0 1 1 0 1 1

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

Exception: Master sends NACK

• Before stop condition, during read
• To indicate end of transfer
• (as per I2C specifications)
• Does not mean error in transmission

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 Burst Write
There may be multiple registers inside a slave
◦ More that one bytes may be written
◦ An effective way of doing it is burst write
◦ To registers at consecutive locations
First
Write

Slave location Data Data Data

Start

Stop
ACK

ACK

ACK

ACK

ACK
Address address byte #1 byte #2 byte #3
Master S 1111000 0 00001111 00000001 00000010 00000011 P
Slave A A A A A

First location address is the address of the register inside the slave
device

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 Burst Read
Multiple bytes may be read from a slave, which has multiple registers

First

NACK
Write

Slave location Slave Data Data Data

Read
Start

Start

Stop
ACK

ACK
ACK

ACK

ACK
Address address Address byte #1 byte #2 byte #3
Master S 1111000 0 00001111 S 1111000 1 A A N P
Slave A A A abcdefgh ijklmnop qrstuvwx

Exception: Master sends NACK

• Before stop condition, during read
• To indicate end of transfer
• (as per I2C specifications)
• Does not mean error in transmission

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I2C (TWI) in AVR
Can be configured as I2C Master or Slave

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I2C (TWI) in AVR
Register Description (TWSR)
Contains information on the status of TWI logic and bus
Moreover, contains pre-scalar bits
𝑓𝑂𝑠𝑐
◦ 𝑓𝑆𝐶𝐿 = 16+2 TWBR ×4 TWPS
◦ TWBR is a Register, whose 8-bits can be used to change frequency as well

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I2C (TWI) in AVR
Register Description (TWCR)
Two-Wire Control Register (TWCR)
◦ Bit 7 – TWINT: TWI Interrupt
◦ Bit 6 – TWEA: TWI Enable Acknowledge
◦ Bit 5 – TWSTA: TWI START condition Bit
◦ Bit 4 – TWSTO: TWI STOP condition bit
◦ Bit 3 – TWWC: TWI Write Collision Flag
◦ Bit 2 – TWEN: TWI Enable
◦ Bit 0 – TWIE: TWI Interrupt Enable

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I2C (TWI) in AVR
Register Description (others
TWI Data Register (TWDR)
◦ Read received data, write data to be transmitted

TWI Address Register (TWAR)

◦ Contains 7-bit slave address, to which AVR responds as slave on the bus

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