8A : Inter-Integrated Circuit

(I C) Protocol
2

Rajesh Panicker

[T]EE2028

Some slides courtesy :

© A/Prof. Tham Chen Khong, ECE, NUS
 I2C Introduction

◼ Inter-Integrated Circuit (I2C, also written as I2C) is

characterised by
◼ bus-based
◼ multi-master
◼ low-bandwidth
◼ short distance
◼ synchronous
◼ serial
◼ uses in-band addressing
◼ uses just two wires (plus ground)
◼ half duplex

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 I2C Introduction

◼ Only a master device can initiate and terminate the data

transfer
◼ True multi-master bus including collision detection and
arbitration to prevent data corruption if two or more masters
simultaneously initiate data transfer
◼ We only consider the single master case here, i.e., STM32 chip is
always the only master. Hence, we will not discuss arbitration
◼ The master generates the clock irrespective of the stage and
direction of transfer
◼ During transfer, any device addressed by the master is
considered a slave, recognized by a unique 7-bit address (a
10-bit variant exists)
◼ The number of ICs that can be connected to the same bus is
limited only by the maximum bus capacitance (400 pF)

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 I2C Introduction
◼ Originally developed by Philips, became an industry
standard
◼ Motivation - lower pin count and hence lower
◼ IC manufacturing / packaging costs
◼ PCB complexity and cost
◼ Power and size
◼ Maximal bi-directional data bit rate:
◼ Standard-mode: 100 kbit/s
◼ Fast-mode: 400 kbit/s
◼ Fast-mode Plus: 1 Mbit/s
◼ High-speed mode: 3.4 Mbit/s
◼ Not all devices are capable of all the modes
◼ Many low-speed devices support only standard-mode
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 Common I2C Peripherals

◼ Real Time Clocks

◼ Converters: ADC and DAC
◼ Memory cards / modules: EEPROM and FLASH
◼ Sensors: i.e. light, temperature, pressure sensor,
accelerometer etc.
◼ Signal-mixer, Amplifier, Potentiometer
◼ LCD/OLED displays
◼ UART, CAN and USB controller
◼ SDRAM, DDR SDRAM, DDR2 SDRAM memory stick
◼ Port expander
◼ Note : Not every model/make of the peripherals mentioned
above use I2C. Some use analog, some use SPI, some use
UART etc.
◼ For example, there are many accelerometers with SPI interface
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 I2C Devices on the Board

To Do : Answer the
rest of the qns in
PCI-4 lab sheet

The devices highlighted above use I2C2 for data transfer. They also use GPIOs (EXTIs) for interrupts
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 I2C Signals

◼ Two bi-directional lines:

Vdd, typically +5 V or +3.3V
◼ Serial Data line SDA contains
the data
◼ Serial Clock line SCL with the
clock signal for
synchronization
◼ When the bus is free, both
lines are high due to pull-up
STM32 Chip
◼ The output stages of devices
connected to the bus must
have an open-drain or open-
Open drain -> collector to perform the wired-
AND function
Output drive is disconnected ->
a pin outputs Z or low, never high

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 I2C Bus Protocol
◼ All transactions begin with a START S and can be terminated by a
STOP P, and are always generated by the master

◼ The bus is considered to be busy after S. The bus is free again a

certain time after P
◼ Another master (if multiple masters are present on the same bus)
will not attempt to send a S condition if the bus is not free – all
devices will keep listening to the bus all the time to know whether
the bus is free or not!
◼ SDA changes when SCL is high only for S and P. For usual data bits,
SDA can change only when SCL is low
Why is S a high->low transition, P a low->high transition, and not the other way around?
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 I2C Bus Protocol

Possible clock stretching

◼ After S, a slave address is sent. This address is 7 bits long followed

by an eighth bit which is a data direction bit R/W
◼ 0 → transmission WRITE
◼ 1 → request for data READ

Sometimes, datasheets mention read (high) and write (low) addresses

separately : 7-bit address appended with a 1 (R) / 0 (W)

To do : Find the I2C addresses of the peripherals on the board 9

 I2C Bus Protocol
◼ Every byte put on the SDA line must be 8 bits long
◼ The number of bytes that can be transmitted per transfer is
unrestricted
◼ The transmitter releases the SDA line during the 9th clock so
the receiver can pull the SDA line low, and it remains stable
low during the high period of this clock pulse to indicate an
ACK (A)
◼ When SDA remains high during this 9th clock pulse, this is
defined as the Not Acknowledge (NACK / Ā) signal
◼ Interpretation depends on whether the master or the slave
generates it
◼ Note : Ā is fact not 'generated'. A lack of A is Ā

Why is A specified to be a low, rather than a high during the 9th clock period?
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 Master Transmitter mode

◼ Master transmitter transmits to slave receiver

◼ The slave receiver acknowledges each byte
◼ The master sends a P after writing the required number of
bytes to terminate the transfer, or a repeated start for a change
of direction to start a read transaction (slide 13)
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 Master Receiver mode

◼ Master reads slave immediately after first (address) byte

◼ At the moment of the first acknowledge, the master transmitter
becomes a master receiver, and the slave receiver becomes a slave
transmitter
◼ This first acknowledge is still generated by the slave, subsequent
acknowledges are generated by the master
◼ The master sends an Ā just prior to the P
◼ Ā from the master has only one interpretation - the master doesn't want
anymore data
◼ It will follow the Ā with a P to finish the transfer, or an Sr to start a new
transfer / change the direction
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 Change of Direction

◼ During a change of direction within a transfer (write->read or read-

>write), a START condition (Sr) and slave address (with R/W bit
reversed) are both repeated without a preceding P
◼ Essentially, it is similar to two separate transfers, but without P in
between
◼ Sr -> sending S without a P just before
◼ Allows master to retain control of the bus
◼ If a master-receiver sends Sr, it sends Ā just prior to the Sr
Which one is more popular : write->read or read->write? 13
 Clock Stretching
◼ An Ā from the slave has no standard meaning - it is up to the master
(i.e., the software controlling the master) to interpret it and decide on
the next course of action. In response to Ā, master can generate
either
◼ a P to abort the transfer or
◼ a Sr to start a new transfer or to retry the previous byte
◼ If a slave cannot receive or transmit another complete byte of data
until it has performed some other function, it can hold the clock line
SCL low to force the master into a wait state
◼ Clock will not appear on the SCL line - in open drain, if anyone drives a
low, the line will remain low
◼ Data transfer then continues when the slave is ready for another byte of
data and releases clock line SCL
◼ This is called clock stretching - the only scenario in which the slave
controls SCL
◼ Not all I2C devices support clock stretching well
What if the master does not receive the data properly from the slave?
Can it not acknowledge? 14
 I2C in Action : xxx Sensor
STM32 Chip Board
BUS
MODER
0x00 REG_1

PUPDR
AFR 0x01 REG_2

OTYPER …
.…
P
yyy SENSOR
I2C_CR1 U
N
SDA
..
I2C_ISR
P 0x00 CONTROL
ARM I2C_TXDR
D
N

Cortex . . 0x01 LSB_SENSOR

I2C_RXDR
M4 Core P 0x02 MSB_SENSOR
…
U
N
I2C INTERFACE SCL …
.. P
D
xxx SENSOR
N INT
From other interfaces
. .
such as SPI, UART etc.
IDR P
U
N
NVIC EXTI
P
ODR D
N
.
GPIO BLOCK
to analog

Sometimes, you need to read only

Which instructions can be used to read / write I2C_CR1, MODER etc.? when there is a real need to, for
example, when the luminous intensity
LDR / STR (helper functions in HAL) exceeds a certain threshold for a light
Can the processor write directly to CONTROL, LSB_SENSOR etc.? sensor. This could trigger an interrupt
(depending on the capability and
No! (write can only be done through the I2C interface, helper functions in BSP) configuration of the sensor), but the
data transfer itself is through I2C 15
 Example: Writing 0x80

Writing an I2C Slave Register

to CONTROL register of
xxx SENSOR

◼ Typically, every register inside an I2C device has an 8-bit

address, containing an 8-bit value
◼ I2C protocol defines the meaning of only the first byte sent over
the I2C interface (SA+R/W)
The meaning of the rest of the bytes is a matter of 0x00 CONTROL
◼ SDA
0x01 LSB_SENSOR

interpretation by the receiving party SCL 0x02 MSB_SENSOR

A programmer needs to read the datasheet of the specific …

◼ …
slave device, figure out how it will interpret the bytes sent, xxx SENSOR

and send values appropriately to meet the needs of the appln 7-bit SA = 0x44

◼ Typically, the second byte written by the master is interpreted by

the slave as the address of the register within the slave
◼ Typically, the third byte written by the master is interpreted by
the slave as the value to be written to the register addressed in
by the previous byte
SLAVE REGISTER SLAVE REGISTER
S SLAVE ADDRESS W A A A P
ADDRESS VALUE
0x88 0x00 0x80
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 Example: Reading from
LSB_SENSOR register of xxx

Reading an I2C Slave Register SENSOR. Assume LSB_SENSOR

contains 0xF3 (value_LSB)

◼ Reading a register typically involves sending (writing) the address of the

register to be read, followed by a read to get the register content

S SLAVE ADDRESS W A SLAVE REGISTER ADDRESS A

0x88 0x01

Sr SLAVE ADDRESS R A SLAVE REGISTER VALUE A P

0x89 0xF3

◼ Many sensors give 16-bit readings and will have separate LSB and MSB
registers. How can we read 2 registers?
◼ Write LSB address, read value_LSB, write MSB address, read value_MSB
◼ Alternative: Autoincrement - reading multiple registers in one transaction
◼ The master reads two bytes in a single read transaction. The first byte is the
content of the register whose address was written in the preceding write. The
second byte is the content of the register with address++, i.e., a pointer
internal to the slave keeps track of which register is read, and increments it
with each byte read
◼ Only if the sensor supports it. May need to be enabled/configured explicitly
◼ Can be used for writing to multiple registers too, not just for reading
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 I2C Advantages
◼ Two lines reduce space, simplify circuit layout and reduces
packing and PCB complexity and costs
◼ Each slave device connected is uniquely addressable using slave
addresses - just two lines can support a fairly large number of
devices
◼ No strict baud rate specified since the clock is driven directly by
the master. This reduces the complexity of the circuit
◼ Multi master support (vast majority of the systems have only a
single master though)
◼ Very simple standardized protocol which can be emulated by
microcontrollers without integrated I2C peripheral devices
through GPIO. This is called bit-banging
◼ Supports up to 3.4 Mbits/sec transfer speeds
◼ ICs can be added to or removed from a system without affecting
any other circuit on the bus
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 I2C Disadvantages
◼ High protocol overhead – a lot of time is wasted sending slave
addresses, acknowledgements etc. (i.e., because of in-band
addressing)
◼ Not very fast compared to other protocols such as SPI / USB
◼ 7-bit addressing supports only a very small number of devices
◼ Different devices from different manufacturers come with hard
coded slave address or address will be configurable in a small
range only
◼ This can lead to address clashes
◼ No automatic bus configuration or plug and play
◼ Slower devices may stretch the clock thereby increasing latency
and keeping other devices waiting for access to the bus
◼ Only handles short distances (because of being synchronous)
compared to other standards such as RS-232, RS-485 or CAN

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Questions?

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