Timing &

Pipelining
LECTURE# 06
MICROPROCESSOR SYSTEMS AND INTERFACING

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Last Lecture
Calling a Subroutine
◦ Role of Stack (Stack Pointer)
◦ Nested Call
◦ CALL and RET Instruction

Other Call instructions

◦ RCALL, ICALL, EICALL

Timing and Machine Cycle

Pipelining (overview)

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Timing & Machine Cycle
Every instruction execution in AVR takes a finite amount of time.
Most instruction takes
◦ One machine cycle to complete execution,
◦ and some instructions take two or more cycles.

AVR uses
◦ Crystal oscillator connected to the XTAL1 and XTAL2 pins
◦ or internal oscillator provides machine clock cycles.
◦ Oscillator cycle is equal to machine cycle

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AVR machine cycle
AVR uses three methods to ensure that most of the instructions take
one cycle to execute:
◦ Harvard architecture
◦ RISC Architecture – provides benefit of having fixed size instructions
◦ 2-byte or 4-byte
◦ Pipelining
Instructions execute in one cycle Instructions execute in two cycles
ADD, ADC, AND, INC, DEC, COM, NEG, SUB BREQ (if true), BRNE (if true)
BREQ (if false), BRNE (if false) LDS, STS
CLR, IN, OUT RJMP

CALL instruction; 4, with 16-bit PC; 5, with 22-bit PC

JMP; 3 cycles
RET; 4 cycles

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Pipelining
In old processors, the CPU executes only one instruction at a time.
◦ Not all the resources of the processor were utilized at a given time
◦ First FETCH ad instruction and then EXECUTE,
◦ then FETCH second and EXECUTE.

Single stage Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3

2 Stage Fetch 1 Fetch 2 Fetch 3

pipeline Execute 1 Execute 2 Execute 3

Time

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Pipelining cont.
In pipelining the CPU executes instructions in parallel.
While fetching the 2nd instruction it executes the first.
The process is split up, in to two parallel processes.
◦ The speed-up offered by the pipelining is shown in previous figure.

Pentium II with MMX uses 11-stages pipeline, Pentium 4 up to 20 stages.

ARM Cortex A9 has 8-11 stages.
Most RISC-V have 5-stage pipeline

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 microcontroller can perform many task paralley with this overall speed of the microcontroller can be improve

Pipelining in AVR
The AVR offers three-stages of pipeline, which are:
1. Operand fetch,
2. ALU operation Execution
3. and results write-back

AVR Fetch 1 Fetch 2 Fetch 3

3- Stage Execute 1 Execute 2 Execute 3
pipeline Write 1 Write 2 Write 3
Time

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 Branch Penalty in Pipelining
The overlapping of instructions in processor causes a problem
◦ when conditional branches are being executed.
◦ Consider the program on the right.
IF condition is TRUE (Penalty)
LDI R16, 0x09
STAGE Count:
FETCH LDI R16, 0x09 DEC R16 BRNE Count ADD R0, R2 DEC R1 BRNE Count DEC R16
EXECUTE LDI R16, 0x09 DEC R16 BRNE Count DEC R1 BRNE Count
WRITE- LDI R16, 0x09 DEC R1 BRNE Count ADD R0, R2
Time
ADD R6, R2

If condition is FALSE (No Penalty) *The condition will be true 8

STAGE times and false one time.
FETCH LDI R16, 0x09 DEC R16 BRNE Count ADD R0, R2 ADD R6, R2
EXECUTE LDI R16, 0x09 DEC R16 BRNE Count ADD R0, R2 ADD R6, R2
WRITE- LDI R16, 0x09 DEC R16 BRNE Count ADD R0, R2
Time

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 Execution Time
Consider the Assembly program
◦ Find the execution time when 𝑓𝑜𝑠𝑐 = 10 MHz
1
Oscillator Time period, 𝑇𝑜𝑠𝑐 = = 0.1 𝜇𝑠
1 MHz

Machine cycles 𝑇𝑜𝑡𝑎𝑙 𝑐𝑦𝑐𝑙𝑒𝑠 = 29

Number of times Cycles for each
Instruction for single
executed instruction
execution
LDI R16, 0x09 1 1 1×1=1 𝑇𝑜𝑡𝑎𝑙 𝐷𝑒𝑙𝑎𝑦
= 𝑇𝑜𝑠𝑐 × 𝑇𝑜𝑡𝑎𝑙 𝑐𝑦𝑐𝑙𝑒𝑠
Count: Not an instruction 0 = 0.1 μs × 29
DEC R16 1 9 1×9 = 9 = 𝟐. 𝟗 𝛍𝐬
BRNE Count 2 (True) / 1 (False) 8 (True) / 1 (False) 2 × 8 + 1 × 1 = 17
ADD R0, R2 1 1 1×1=1
ADD R6, R2 1 1 1×1=1

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 Quiz 1 – Draw Empty table
Type A Type B
Q1: Before this code, date memory has Q1: Before this code, date memory has
◦ 52 at location 0x401, 71 at location 0x302 ◦ 176 at location 0x320, 216 at location 0x301
◦ 216 at location 0x303 ◦ 19 at location 0x302
Contents of (in hex) Contents of (in hex)

0x303

0x302

0x401

0x303

0x302

0x320
Instructions Instructions
R16

R18

R19

R16

R18

R19
L1: LDI R16, 0x23 L1: LDI R18, 0x32
LDI R18, 107 LDI R16, 107
STS 0x401, R18 LDS R16, 0x320
STS 0x302, R16 LDS R18, 0x302
LDS R19, 0x303 STS R19, 0x303
SUB R19, R18 ADD R16, R18
STS 0x303, R19 STS 0x303, R16

Q2: For a program memory 8k x 32 Q2: For a program memory 2k x 64

a) Calculate the memory size in bytes? a) Calculate the memory size in bytes?
b) Calculate program counter width b) Calculate program counter width

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 Quiz 1
Type A Type B
Q1: Before this code, date memory has Q1: Before this code, date memory has
◦ 52 at location 0x401, 71 at location 0x302 ◦ 176 at location 0x320, 216 at location 0x303
◦ 216 at location 0x303 ◦ 19 at location 0x302
Contents of (in hex) Contents of (in hex)

0x303

0x302

0x401

0x303

0x302

0x320
Instructions Instructions
R16

R18

R19

R16

R18

R19
L1: LDI R16, 0x23 L1: LDI R18, 0x32
LDI R18, 107 LDI R16, 107
STS 0x401, R18 LDS R16, 0x320
STS 0x302, R16 LDS R18, 0x302
LDS R19, 0x303 STS 0X303, R19
SUB R19, R18 ADD R16, R18
STS 0x303, R19 STS 0x303, R16

Q2: For a program memory 8k x 32 Q2: For a program memory 2k x 64

a) Calculate the memory size in bytes? a) Calculate the memory size in bytes?
b) Calculate program counter width b) Calculate program counter width

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