Subject Name:- HPC& Code:- CS-3010

Branch (s): - CSE, Semester: 5th

AUTUMN MID SEMESTER EXAMINATION-2023

Scheme of evaluation
School of Computer Engineering
Kalinga Institute of Industrial Technology, Deemed to be University High Performance Computing (HPC)
[Subject code: CS-3010]
Time: 1 1/2 Hours Full Mark: 40

Q1.

A. Consider two processors P1 and P2 executing the same same program. Assume that under identical
conditions, for the same input, a program running on P2 takes 40% less time but incurs 20% more CPI
(clock cycles per instruction) as compared to the program running on P1. If the clock frequency of P1 is
2GHZ, then calculate the clock frequency of P2.
Ans:

B. Consider the cache memory which is 5 time faster than main memory and it can be used 85% of the total
time.then calculate the overall speedup gain by cache memory?
ANS:

C. Represent the machine code for the MIPS instruction SLT R10, R14, R16 in 32 bit binary. Assume the
opcode value for SLT (set to 1 if less than) and Function code in hexadecimal is 0X00 and 0x2A respectively.
ANS:
 D. For the code sequence below, state whether it must stall, can avoid stalls using only forwarding,
or can execute without stalling or forwarding ?Justify your answer?
LW R1,8(R2)
ADD R2,R1,R1
ANS: it must stall
We cannot avoid stall using only forwarding or can execute without stalling or
forwarding

E. Consider a 5 stage pipeline processor operating with ideal CPI is 1clock cycle which allow all
the instructions except the branch instructions. Processor stops the fetching of the following
instructions after the branch instructions until the branch target address is available in the pipeline.
In the pipeline, the branch target address is available when the instruction is completed (at last
stage).Program contains 60% branch instructions among them 60% are conditional branch in which
60% does not satisfy the condition. When the condition is false, then the following instructions are
overlapped. Calculate the pipeline speedup?
ANS
Q2.
A. Briefly, Explain different MIPS instruction format (R type, I type, and J type) with examples from each
type?
ANS:MIPS Instruction format
Instructions are divided into three types: R, I and J.
Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a
shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-
type instructions follow the opcode with a 26-bit jump target
ADD r1.r2,r3
addi rt, rs, imm
BEQ r2,r3,8
J 32;

[5 marks]
B. For a given computer system, following are the different type of instructions supported by machine. The
number of clock cycle taken for each of load, store, ALU, branch and Jump instruction are 5, 4, 3, 3 and 2
clock cycle respectively. If a program has 40% ALU instructions,20% load instructions, 20% store
instructions, 18% branch instructions and 2% Jump instructions. If the program has 5000 instructions and the
speed of the computer is 3.25GHZ, calculate the overall CPI and time taken to execute the program.
[5 marks]

ANS:

Q3.

A. Distinguish between RISC and CISC? Briefly, explain the 7 dimensions of Instruction set architecture
with suitable examples.
ANS:The CISC approach attempts to minimize the number of instructions per program, sacrificing the number
of cycles per instruction.
A complex instruction set computer is a computer in which single instructions can execute several low-level
operations (such as a load from memory, an arithmetic operation, and a memory store)
capable of multi-step operations or addressing modes within single instructions.
RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per
program.
A reduced instruction set computer is a computer with a small, highly optimized set of instructions.
the instruction set is optimized with a large number of registers and a highly regular instruction pipeline, allowing
a low number of clock cycles per instruction (CPI).
Core features of a RISC philosophy are a load/store architecture in which memory is accessed through specific
instructions rather than as a part of most instructions in the set, and requiring only single-cycle instructions.
7 dimension of ISA
Class ISA,memory addressing,addressing mode,type and size of operand,operations,control flow
instruction,encoding of ISA

[5 marks]

B. Consider the following instructions sequence [5 marks]

I1: LW R2, 0(R1)

I2: LW R1, 8(R3)
I3: SUB R3, R1, R2
I4: ADD R3, R2, R1
I5: ADDI R4, R3, 8
I5: SW R3,32(R1)

Identify the Read after write hazard. Assume the 5-stage MIPS pipeline without forwarding and each stage
takes 1 cycle. Instead of inserting nops, let the processor stall on hazards. How many times does the
processor stall ? calculate the total number of clock cycle required to execute the above instructions without
operand forwarding?

Q4.

A. What is branch hazard ?Discuss Delayed Branch resolution techniques for eliminating branch hazard
[5marks]
ANS:Branch hazard also known as Control hazards arise when the CPU cannot determine which instruction to
fetch next.We can minimize delays by doing branch tests earlier in the pipeline.
We can also take a chance and predict the branch direction, to make the most of a bad situation.
Delayed Branch resolution techniques:
 B. Consider the following instructions:-
LW R1, 8(R11)
ADD R1, R5, R1
SW R1, 8(R11)
LW R1, 16(R15)
BEQ R1, R12, Label
ADDI R1, R1, 8
OR R1, R12, R17
Label: SW R10, 16(R8)
SUBI R4, R4, 8
Find out the independent instruction which can be scheduled into the delayed slot for branch taken. Draw
time phase diagram to calculate the total number of clock cycle required to execute the above
instructions with operand forwarding for the taken branch. Assume the value of R1 and R12 is 20 while
executing BEQ (Branch if Equal) instruction and branch decision is done in decode stage in a 5 stage
MIPS pipeline processor. [5marks]

ANS:
the independent instruction which can be scheduled into the delayed slot for branch taken is
SW R10, 16(R8)

Q5.
A. Explain static branch prediction and dynamic branch predictions schemes and provide details for each of
them?
ANS:
In case of Static branch prediction technique underlying hardware assumes that either the branch is not taken
always or the branch is taken always.
In Dynamic branch prediction technique prediction by underlying hardware is not fixed, rather it changes
dynamically.
Some dynamic branch prediction techniques are:

1-bit predictor(last time predictor)

1-bit branch prediction technique: There are two states 0 and 1. Each state represents one prediction. If anyone
makes a wrong prediction then move to another state.

2-bit predictor.

B. The outcome of a branch is T, T, T, T, T, NT and this pattern is repeated 4 times by an outer loop. Find
out the no of miss and correct predictions using 2-bit predictor scheme. Assuming the initial state is strongly
not taken (NT) and 2 bits counter value is 002. [5 marks]
ANS: