Made by : Shailesh Mittal 100805063 Shikha Khattar 100805065 Suresh Malhotra 100805071 Samarth Gulati 100805086 EIC 3rd yr

Power supply . Working 5. Introduction 2. PIC 6. Pin description 8. Pin diagram 7.Contents 1. Aim 3. Components used 4.

amber sequence can be varied from about 10s to any desired value. Each output becomes high in turn as the clock pulses are received. Here we propose a solution for traffic light management . whenever a vehicle crosses the red signal a hidden cctv camera captures the vehicle’s number that is further connected to the control traffic head quarter. Some amber LEDs emit light that is almost red so you may prefer to use a yellow LED. Appropriate outputs are combined with diodes to supply the amber and green LEDs. .red & amber .1. 2.Introduction . amber and green LEDs in the correct sequence for a single traffic light. Traffic Light Project This project operates red. With lanes having a traffic light for the traffic moving on the opposite roads .Aim: In this traffic light project we consider traffic moving on two parallel Roads. The time taken for the complete red .green .

LED ‘s ( red . 3. green . Capacitor (10uf ) 6.Working : 1. 7805 Ic 5. 2. Oscillator 10. yellow) 3.Component used: 1. Yellow of both the lanes glow simultaneously for 2 sec . Bread board 9. When the red of one lane glows correspondingly green of the other lane glows . the vehicle crossed the traffic signal ) the camera takes a picture of that vehicle number plate .( here camera is represented by a led) .3.e. Resistance 7. Red and green LED’s glow for an interval of 10 sec each. PIC16F877A 2. If one of the push buttons is pressed ( only during the red light i.Battery 4. Connecting wires 8. Push buttons 4. 4.

derived from the PIC1640 originally developed by General Instrument's Microelectronics Division. PICs are popular with both industrial developers and hobbyists alike due to their low cost. and serial programming (and re-programming with flash memory) capability.5 . availability of low cost or free development tools.    A hardware stack for storing return addresses A fairly small amount of addressable data space (typically 256 bytes). large user base. Core architecture The PIC architecture is characterized by its multiple attributes: Separate code and data spaces (Harvard architecture) for devices other than PIC32.e. which has a Von Neumann architecture. and peripheral registers The program counter is also mapped into the data space and writable (this is used to implement indirect jumps). the use of which (as source operand) is implied (i. PIC ( Peripheral interface controller) PIC is a family of Harvard architecture microcontrollers made by Microchip Technology.    A small number of fixed length instructions Most instructions are single cycle execution (2 clock cycles. is not encoded in the opcode)  All RAM locations function as registers as both source and/or destination of math and other functions. with one delay cycle on branches and skips One accumulator (W0). . Microchip announced on February 2008 the shipment of its six billionth PIC processor. port. extended through banking   Data space mapped CPU. wide availability. or 4 clock cycles in 8bit models). extensive collection of application notes. The name PIC initially referred to "Peripheral Interface Controller".

Data space (RAM) PICs have a set of registers that function as general purpose RAM. external code memory is not directly addressable due to the lack of an external memory interface. any register move had to be achieved via the accumulator. i. Code space The code space is generally implemented as ROM. In earlier devices. PICs in the baseline and mid-range families have program memory addressable in the same wordsize as the instruction width.There is no distinction between memory space and register space because the RAM serves the job of both memory and registers. and all PIC devices have some banking mechanism to extend addressing to additional memory. In general.e. For example. a "file select register" (FSR) and "indirect register" (INDF) are used. The exceptions are PIC17 and select high pin count PIC18 devices. External data memory is not directly addressable except in some high pin count PIC18 devices.[5] Word size All PICs handle (and address) data in 8-bit chunks. A register number is written to the FSR. and the RAM is usually just referred to as the register file or simply as the registers. Later series of devices feature move instructions which can cover the whole addressable space. the unit of addressability of the code space is not generally the same as the data space. independent of the selected bank. This also allows FSR to be treated almost like a stack pointer (SP).and preincrement/decrement for greater efficiency in accessing sequentially stored data. Special purpose control registers for on-chip hardware resources are also mapped into the data space. However. after which reads from or writes to INDF will actually be to or from the register pointed to by FSR. 12 or 14 bits . The addressability of memory varies depending on device series. To implement indirect addressing. Later devices extended this concept with post. EPROM or flash ROM.

respectively. PIC cores have skip instructions which are used for conditional execution and branching. conditional jumps are implemented by a conditional skip (with the opposite . as well as for conditional execution. it is necessary to load it into W before it can be moved into another register. In contrast. and program branching. such as bit setting and testing. The hardware stack is not software accessible on earlier devices. Instruction set A PIC's instructions vary from about 35 instructions for the low-end PICs to over 80 instructions for the high-end PICs. On the older cores. the accumulator and a literal constant or the accumulator and a register. but this changed with the 18 series devices. Because cores before PIC18 had only unconditional branch instructions. rather than in bytes. The skip instructions are 'skip if bit set' and 'skip if bit not set'. in the PIC18 series. but this changed on the "high end" cores. can be performed on any numbered register. all register moves needed to pass through W. but bi-operand arithmetic operations always involve W (the accumulator). but this greatly improved in the 18 series. Stacks PICs have a hardware call stack. Some operations. making the 18 series architecture more friendly to high level language compilers. which is used to save return addresses. The instruction set includes instructions to perform a variety of operations on registers directly. Hardware support for a general purpose parameter stack was lacking in early series. To load a constant. the program memory capacity is usually stated in number of (single word) instructions. the program memory is addressed in 8-bit increments (bytes). which differs from the instruction width of 16 bits. In order to be clear. writing the result back to either W or the other operand register.

These take a register number and a bit number. Other than the skip instructions previously mentioned. Such lookups take one instruction and two instruction cycles. 4. Operation on working register (WREG) with 8-bit immediate ("literal") operand. Bit operations. PIC instructions fall into 5 classes: 1. Control transfers. there are only two: goto and call. addwf reg. or the selected register (e. andlw (AND literal with WREG). The result can be written to either the Working register (e. The PIC instruction set is suited to implementation of fast lookup tables in the program space.g. E. and is still among the simplest and cheapest. In general.g. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible. 2. 5. One instruction peculiar to the PIC is retlw. Performance The architectural decisions are directed at the maximization of speed-to-cost ratio. movlw (move literal to WREG). and test and skip on set/clear. load immediate into WREG and return. such as return from subroutine. and sleep to enter low-power mode. Skips are also of utility for conditional execution of any immediate single following instruction. and perform one of 4 actions: set or clear a bit.g. 3. The Harvard architecture—in which instructions and data come from separate sources—simplifies timing and microcircuit design greatly.condition) followed by an unconditional branch. Operation with WREG and indexed register. which is used with computed branches to produce lookup tables.f). providing hardware support for automatically saving processor state when servicing interrupts. price. A few miscellaneous zero-operand instructions. The PIC architecture was among the first scalar CPU designs. The latter are used to perform conditional branches. and this benefits clock speed. . addwf reg. and power consumption. The 18 series implemented shadow registers which save several important registers during an interrupt.w).

An example of this is a video sync pulse generator. The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. and execute a "RETLW" which does as it is named .Many functions can be modeled in this way. Internal interrupts are already synchronized. interrupt latency is constant at three instruction cycles.g. because they have a synchronous interrupt latency of three or four cycles. SPI. this simplifies design of real-time code. a branch instruction's target may be indexed by W. A/D. For example. Optimization is facilitated by the relatively large program space of the PIC (e. programmable Comparators. PWM. PSP. and Ethernet Limitations The PIC architectures have these limitations: . Execution time can be accurately estimated by multiplying the number of instructions by two cycles. CAN. USART. USB. Advantages The PIC architectures have these advantages:     Small instruction set to learn RISC architecture Built in oscillator with selectable speeds Easy entry level. Similarly. in circuit programming plus in circuit debugging PICKit units available from Microchip. which allows for embedded constants. LIN. This is no longer true in the newest PIC models. External interrupts have to be synchronized with the four clock instruction cycle. otherwise there can be a one instruction cycle jitter.return with literal in for less than $50   Inexpensive microcontrollers Wide range of interfaces including I2C. 4096 x 14-bit words on the 16F690) and by the design of the instruction set.

In both cases. where you add to PCL. the page size is 256 instruction words. so preemptive task Software-implemented stacks are not efficient.  One accumulator Register-bank switching is required to access the entire RAM of many devices Operations and registers are not orthogonal. in 2008. but still apply to earlier cores:  Stack: 1. PCLATH must also be preserved by any interrupt handler. 2. Microchip released their own C compilers. so it is difficult to switching cannot be implemented generate reentrant code and support local variables With paged program memory. the upper address bits are provided by the PCLATH register. for the line of 18F 24F and 30/33F processors. Judicious use of simple macros can increase the readability of PIC assembly language. By contrast. For . some instructions can address RAM and/or immediate constants. so the page size is 2048 instruction words. but feature a more traditional instruction set—have long been supported by the GNU C Compiler. there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups). For example. on PIC16.[7] Compiler development While several commercial compilers are available. This register must be changed every time control transfers between pages. The hardware call stack is not addressable. C18 and C30. CALL and GOTO have 11 bits of addressing. The easy to learn RISC instruction set of the PIC assembly language code can make the overall flow difficult to comprehend. while others can only use the accumulator  The following limitations have been addressed in the PIC18 series. For computed GOTOs. Atmel's AVR microcontrollers—which are competitive with PIC in terms of hardware capabilities and price.

sbit red1 at PORTD. sbit red2 at PORTD. } void CAMERA1() { int i. a" (move the data from address a to address b) and "add b. b.i++) { PORTC=0xFF . Delay_ms(500). extern sbit red1. // 1/2 second delay PORTC=0x00 . It has macro instructions like "mov b. } // 1/2 second delay . PORTC=0x00 . dest" (compare a with b and jump to dest if they are not equal).B7.example. a" (add data from address a to data in address b). sbit stline1 at PORTB. for(i=0. } INTCON. extern sbit stline2.i<=4. extern sbit red2.i++) { PORTC=0xFF . for(i=0.B1. void CAMERA0() { int i.i<=2. the original Parallax PIC assembler ("SPASM") has macros which hide W and make the PIC look like a two-address machine. Delay_ms(250). Delay_ms(250). Programme aextern sbit stline1.B0.B4.B1 = 0x0. Delay_ms(500). sbit stline2 at PORTB. It also hides the skip instructions by providing three operand branch macro instructions such as "cjne a.

B1 = 0. Delay_ms(10000). Delay_ms(10000). if (INTCON.INTCON. Execute RD1 ISR } void main(){ TRISB = 0x01. } while(1). // Set PB0 as input // set direction to be output // set direction to be output do { PORTD = 0x84. // Endless loop } .B1*red2==1) CAMERA1(). } void interrupt(){ // Interrupt rutine if (INTCON.B1*red1==1) CAMERA0() . PORTD = 0x30. //RDO causes interrupt? //Yes. TRISC = 0x00. // Turn ON LEDs on PORTB // 10 second delay // Turn ON LEDs on PORTB // 2 second delay // Turn ON LEDs on PORTB // 10 second delay INTCON = 0x90. Execute RDO ISR //Or was it RD1? // Yes. PORTD = 0x48. TRISD = 0x00. Delay_ms(2000).

Pin diagram: .6.

diagram of supply : Here we are using 5V power supply with the help of 7805 regulator Ic. LM 7805 .7.Pin description: Pin 33 : red led of one side Pin 34 : yellow led of one side Pin 35 : green led of one side Pin 36 : red led of second side Pin 37 : yellow led of second side Pin 38 : green led of second side Pin 20: push button 1 Pin 19: push button 2 Pin 16 : camera 1 Pin 15 : camera 2 8.