KALINGA INSTITUTE OF INDUSTRIAL TECHNOLOGY (KIIT)

(Deemed to be University)
SCHOOL OF COMPUTER ENGINEERING

AUTUMN SEMESTER 2021

ACTIVITY / ASSIGNMENT 1

Date: 03/08/2021

Subject: HPC

You all have to write the answers then scasn it to upload at KIIT MOODLE only
in pdf format.

Last date of submission is 31ST August 2021.

ACTIVITY - 1

List of Activities

1. Why CISC architecture can not leads to have improved performance with respect to RISC architecture.
2. Give a brief comparison between pipeline computers, array processor and multiprocessor.
3. What are the different types of pipeline hazards? Explain different types of hazards with examples.
4. Derive the performance equation for the pipeline with stall. Express the same using pipeline depth.
5. A Pipeline system affected by branch instructions is 10 stall cycles. If 30% instruction are branch
instructions and pipeline is operating with a clock cycle of 20 ns providing the speed up factor is 40
then, find out the number of stages in the pipeline system?
6. Consider an un-pipelined processor takes 5 clock cycles for ALU and other operations but it takes 10
clock cycles for memory operations. Assume the relative operation frequencies like ALU and other
operations are 80% and memory operations are 20%. Ignore the effect of branching operations. If
cycle time is 1 ns and pipeline overhead is 0.2 nanosecond then, calculate the speed due to pipeline.
7. Consider the following instructions:-
MUL R2, R3, R5
ADD R5, R2, R6
SUB R7, R2, R5
MUL R9, R7, R2
DIV R8, R9, R7
SUB R9, R8, R6
Find out all type of data dependency and list the two instructions Involved.
For the above sequence of instructions, find out total number of clock cycles and stalls required to
complete the execution, if operand forwarding is not used?
8. A five stage pipeline processor has IF, ID, EXE, MEM, WB. The IF, ID, MEM, WB stages takes 1 clock
cycles each for any instruction. The EXE stage takes 2 clock cycles for logical instructions, 2 clock cycles
for ADD, SUB, MUL instructions, 3 clock cycles for DIV and memory instructions respectively. Consider
the following instructions:-
LOAD R3, 9(R6)
DIV R1, R3, R4
ADD R5, R1, R3
STORE R2, 2(R5)
SUB R2, R1, R8
MUL R9, R2, R10
XOR R2, R9, R7
For the above sequence, find out total number of clock cycles and stalls required to complete the
execution, if operand forwarding is used?
9. Consider the following instructions:-
ADD R2, R3, R4
ADD R5, R2, R6
OR R7, R2, R8
AND R9, R2, R10
XOR R8, R2, R7
For the above sequence:-
a) Find out all type of data dependency?
b) Find out total number of clock cycles required to complete the execution of above instructions
without operand forwarding?
c) Find out total number of clock cycles required to complete the execution above instructions, if
operand forwarding is used?
10. Consider the following instructions :-
STORE 20(R1), R6
SUB R2, R3, R4
DIV R2, R2, R5
LOAD R2, 11(R6)
ADD R7, R2, R4
LOAD R9, 9(R8)
BEQZ R9, L2
MUL R9, R7, R2
LOAD R11, (0)R7
 ADD R9, R11, R3
MUL R8, R2,R11
END
L2:- DIV R7, R1,R8
ADD R6, R7, R8
If the branch instruction is not taken in the above sequence of instructions, then find out the total
number of clock cycles required to complete their execution by using operand forwarding
11. Consider the following instructions:-
SUB R1, R3, R2
LOAD R2, 10(R5)
STORE (04)R8, R2
DIV R3, R2, R1
SUB R2, R3, R1
BNEQZ R2, L1
LOAD R7, 14(R6)
ADD R8, R7, R2
DIV R9, R8, R7
END
L1:- LOAD R7, 11(R2)
SUB R4, R7,R5
MUL R7, R4, R5
If the branch instruction is taken in the above sequence of instructions, then find out the independent
instruction which can be enter in to delayed slot for all possible cases in order to improve the system
performance.
12. Consider the following instructions :-
SUB R1, R2,R3
MUL R4, R1,R2
STORE (09)R5, R4
LOAD R4, (50)R6
DIV R1, R4, R5
BNEQZ R1, L3
ADD R2, R2, R3
LOAD R2, (12)R9
STORE (10)R7, R2
END
L3:- DIV R6, (10)R6, R3
SUB R8, R4, R6
If the branch instruction is taken in the above sequence of instructions, then find out the independent
instruction which can be entered into the delayed slot for all possible cases in order to improve the
system performance.

Total Marks 6