Scribd Logo
Upload

Welcome to Scribd!

  • Activity 2 - 2022 Hpca

    Uploaded by

    venu
    9 views3 pages
    The document provides 7 questions as an activity or assignment related to high performance computing (HPC). The questions cover topics such as instruction scheduling and loop unrolling to reduce clock cycles, dynamic scheduling using scoreboarding, dynamic scheduling using Tomasulo's approach, analyzing cache hits and misses with write-allocate vs no-write-allocate policies, cache miss penalty time and how to reduce it, states of a directory-based cache coherence protocol, and cache coherence in distributed shared memory architectures. Students are instructed to answer the questions, scan them as a PDF, and upload to the KIIT MOODLE classroom by November 20th, 2022.

    Original Description:

    Original Title

    ACTIVITY 2 - 2022 HPCA

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document provides 7 questions as an activity or assignment related to high performance computing (HPC). The questions cover topics such as instruction scheduling and loop unrolling to reduce clock cycles, dynamic scheduling using scoreboarding, dynamic scheduling using Tomasulo's approach, analyzing cache hits and misses with write-allocate vs no-write-allocate policies, cache miss penalty time and how to reduce it, states of a directory-based cache coherence protocol, and cache coherence in distributed shared memory architectures. Students are instructed to answer the questions, scan them as a PDF, and upload to the KIIT MOODLE classroom by November 20th, 2022.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    9 views3 pages

    Activity 2 - 2022 Hpca

    Uploaded by

    venu
    The document provides 7 questions as an activity or assignment related to high performance computing (HPC). The questions cover topics such as instruction scheduling and loop unrolling to reduce clock cycles, dynamic scheduling using scoreboarding, dynamic scheduling using Tomasulo's approach, analyzing cache hits and misses with write-allocate vs no-write-allocate policies, cache miss penalty time and how to reduce it, states of a directory-based cache coherence protocol, and cache coherence in distributed shared memory architectures. Students are instructed to answer the questions, scan them as a PDF, and upload to the KIIT MOODLE classroom by November 20th, 2022.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 3

    KALINGA INSTITUTE OF INDUSTRIAL TECHNOLOGY (KIIT)

    (Deemed to be University)
    SCHOOL OF COMPUTER ENGINEERING

    AUTUMN SEMESTER 2022

    ACTIVITY / ASSIGNMENT - 2

    Date: 12/11/2022

    Subject: HPC

    You all have to write the answers then scasn it to upload at KIIT MOODLE class
    room only in pdf format.

    Last date of submission is 20th November 2022.

    ACTIVITY - 2

    List of Activities

    1. Consider the loop on MIPS without any scheduling will execute as follows:-
    Clock Cycles Issued
    LOOP: LOAD F2, 0(R7) 1
    STALL 2
    ADD F0, F2, F4 3
    STALL 4
    STALL 5
    SUB F6, F0, F2 6
    STALL 7
    STALL 8
    STORE F0, 0(R7) 9
    STALL 10
    ADD R7, R7, #+8 11
    STALL 12
    BEQ F1, F5, LOOP 13
    Use the benefits of instruction scheduling and loop unrolling to reduce the number of clock cycle
    required to complete the execution of the above given code. [Refer to the latency table given in the test
    book]

    2. Assume we have 2 multipliers, 2 adders, 1 divide & 1 integer unit. The following set of MIPS
    instruction is going to be executed in a pipelined system.

    Consider the following instructions:-


    MUL R3, R5, R4
    ADD R7, R3, R5
    SUB R6, R7, R5
    LOAD R6, 48(F5)
    LOAD R9, 48(F5)
    MUL R10, R9, R3
    DIV R7, R3, R2
    ADD R2, R7, R3
    Consider the following execution status for the above instruction set:-
     1st MUL instruction is completed in its write result phase.
     All other remaining instruction is in its execution phase.
    Show the status of instruction, reservation station, & register result status using dynamic scheduling
    with the Scoreboard approach.
    3. Assume we have 3 multipliers, 4 adders & 3 loader units. The following set of MIPS instruction is
    going to be executed in a pipelined system.

    Consider the following instructions:-


    LOAD R1, 23(R2)
    LOAD R5, 48(F1)
    MUL R3, R5, R4
    LOAD R3, 48(F5)
    ADD R7, R3, R5
    SUB R6, R2, R5
    DIV R7, R3, R2
    ADD R2, R6, R3
    Consider the following execution status for the above instruction set:-
     1st two LOAD instructions are completed their write result phase.
     MUL & DIV instructions are ready to go for their write result phase.
     All other remaining instruction is in its execution phase.
    Show the status of instruction, reservation station, & register result status using dynamic scheduling
    with tomasulo approach.

    4. Assume a fully associative write back cache with many cache entries that starts empty. Below is a sequence of 7
    memory operations (the address is in square brackets).
    WriteMem [100]
    ReadMem [300 ]
    WriteMem [200]
    ReadMem [100 ]
    ReadMem [400 ]
    WriteMem [200]
    WriteMem [300]
    What are the numbers of hits and misses when using no-write allocate Vs write allocate?
    5. What is cache miss penalty time? Explain how to improve cache memory performance by reducing cache miss
    penalty.
    6. Draw and explain the states of directory-based cache protocol which implements both CPU request and BUS
    request for each cache block access.

    7. What is a distributed shared memory architecture? Explain cache coherence in symmetric shared-
    memory multiprocessors with an example.

    You might also like