13.

3 RISC MACHINES
In the mid-1970's advances in semiconductor technology
began to reduce the difference
increased, and
between main memory and processor chips. As memory speed
uSpeed the major reasons for CISC began to
displaced assembly language,
-level languages to look at ways computer performance
could
sappear, and computer designers began
hardware.
De optimized
beyond just making faster

13.3.1 RISC Characteristics

In RISC machine, the instruction set contoin
Simple Instruction Set.
a

from which more complex instructions can be comp0sed

simple, basic instructions,
386 DiGITAL DEs1GN AND COMPUTER
ORGANISATION
so that it
Same Length Instructions. Each instruction is of the same length,
may be fetched in a single operation.
1 in
machine-cycle Instructions.
cycle, which allows the processor to handle
Most instructions complete one macnine
several instructions at the same
time. This pipelining is a key technique used to speed up RISC machines.

13.3.2 Advantages
Implementing a processor with a simplified instruction set design provides several
advantages over implementing a comparable CISC design:
Speed. Since a simplified instruction set allows for a pipelined, superscalar
design RISC processors often achieve 2 to 4 times the performance of CISC
processors using comparable semiconductor technology and the same clock rates.
Simpler Hardware. Because the instruction set of a RISC processor is so
simple, it uses up much less chip space; extra functions, such as memory
management units or floating point arithmetic units, can also be placed on the
same chip. Smaller chips allow a semiconductor manufacturer to place more
parts on a single silicon wafer, which can lower the per-chip cost dramatically.

Shorter Design Cyele. Since RISC processors are simpler than

corresponding
CISC processors, they can be designed more
quickly, and can take advantage
of other technological developments sooner than corresponding CISC
leading to
designs,
greater leaps in performance between generations.

13.3.3 RISC Instructions

instruction set of a typical RISC processor is restricted to the
The
use of load and store
instructions when communicating between memory and CPU. All
other instructions are
executed within the registers of the CPU without
referring to memory. A
program for a
RISC-type CPU consists of LOAD and STORE instructions that have
one memory and one
register address, and computational-type instructions that
have three addresses with all
three specifying processor registers. For
example, the program to evaluate X
(C + D) using RISC instructions is as follows: =(A + B) x

LOAD R1, A R1
LOAD R2, B
M[A]
R2
LOAD R3, C
M[B]
R3
LOAD R4, D M[CI
R4
ADD R1, R1, R2 M[D]
R1
ADD R3, R3, R4 R3
R1+R2
MUL R1, R1, R3 R3R4
R1
STORE X, R1
MX]
R1x R3
R1
instructions transter the operands
The load
and multiply
operations are exeeuvea with data infrom-memory to CPU
the registers without registers. The add
Finally the result of the computations
is stored in accessing memory.
memory si
 CISC AND RISC
13.3.4 RISC Hazards ARCHITECTURE 387

transition from a CISC design

emS. Sof
its problems. Software engineers shouldstrategy
be
to a RISC design
strategy isn't without
aware of the key
moving code fron
om a CISC processor to issues which arise
a RISC processor. when
Code Quality
The performance ofa RISC processor depends greatly on the
1f the programmer (or compiler) does a code that it is
poor job of instruction executing.
an SDend quite a bit of time stalling: waiting for the result of
scheduling, the processor
can proceed with a subsequuent instruction. one instruction before it
Since the scheduling rules can be
complicated, most
language (such as C or C++) and leave the instruction programmers use a high level
scheduling to the compiler.
This makes the performance ofa RISC
the code generated by the compiler.
application depend critically on the quality of
Therefore, developers (and development tool suppliers
such as Apple) have to choose their
compiler carefully based on the of quality the generated
code.

Debugging
Unfortunately, instruction scheduling can make debugging difficult. If scheduling
(and other optimizations) are turned off, the
machine-language instructions show a clear
connection with their corresponding lines of source. However, once instruction
is turned on, the machine
scheduling
language instructions for one line of source may appear in the
middle of the instructions for another line of source code.
Such an intermingling of machine language instructions not only makes the code
hard to read, it can also defeat the purpose of using a source-level compiler, since single
lines of code can no longer be executed by themselves.
Therefore, many RISC programmers debug their code in an un-optimized, un-scheduled
form and then turn on the scheduler (and other optimizations) and hope that the program
continues to work in the same way.

Code Expansion
Since CISC machines perform complex actions with a single instruction, where RISC
machines may require multiple instructions for the same action, code expansion can be
a problem.
Code expansion refers to the increase in size that you get when you take a program
that had been compiled for a CISC machine and re-compile. it for a RISC machine. The
on the quality of the compiler and the nature of the
exact expansion depends primarily
machine's instruction set.

Fortunately forthe code expansion between a 68K processor used in the non-
us,
PowerPC Macintoshes and the PowerPC seems to be only 30-50% on the average, although
code can be the same size (or smaller) than corresponding 68K
size-optimized PowerPC
code.
388 DiGiTAL DesiGN AND COMPUTER ORGANISATION

System Design
Another problem that faces RISC machines is that they require very 1ast memory
contain large memory
S
0
reed them instructions. RISC-based systems typically
caches, usually on the chip itself.

13.4 CISC VS. RISC

From the above discussion on CISC and RISC we conclude that the main characteristics
of CISC
microprocessors are:
Extensive instructions.
Complex and efficient machine instructions.
Microencoding of the machine instructions.
Extensive addressing capabilities for memory operations.
Relatively few registers.
In comparison, RISC processors are more or less the opposite of the above:
Reduced instruction set.
Less complex, simple instructions.
Hardwared control unit and machine instructions.
.Few addressing schemes
for memory operands with only two basic instructions,
LOAD and STORE
Many symmetric registers which are oraganised
into a register file.
The question of which of these two
approaches to use in designing a
become one of the great arguments of the processor has
computer world. This is
because once a platform
makes an instruction
set decision, it especially true
order to ensure compatibility with existing tends to stick with it in
software. Somewhat
RISC and CISC has become blurred in recent
years, with each
ironically, the line between
ground in an attempt to improve performance. In
moving toward the middle
and CISC concepts have emerged addition, new ways to mixing RISC
through the use of
translating processors.

SUMMARY
.Microprogram sequencer sequences the
microinstructions in control
.CISC machines are more
complex and less efficient. memory.
T h e aim of employing RISC design is to
execution time of instructions. increase the
computing speed by reducing the