RISC ARCHITECTURE/

INTRODUCTION TO ARM
PROCESSORS
MPMC
RISC

 RISC, or Reduced Instruction Set Computer is a type of

microprocessor architecture that utilizes a small, highly-optimized
set of instructions, rather than a more specialized set of
instructions often found in other types of architectures.
 HISTORY
 Thefirst RISC projects came from IBM, Stanford, and UC-Berkeley in the late
70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2
were all designed with a similar philosophy which has become known as
RISC.
 Certain design features have been characteristic of most RISC processors:
 one cycle execution time: RISC processors have a CPI (clock per instruction) of one
cycle. This is due to the optimization of each instruction on the CPU and a technique
called pipelining.
 pipelining: a technique that allows for simultaneous execution of parts, or stages, of
instructions to more efficiently process instructions;
 large number of registers: the RISC design philosophy generally incorporates a larger
number of registers to prevent in large amounts of interactions with memory.
 ARCHITECTURE

 The Blocks have their usual

operations.
 Examples of RISC processors :
 MIPS,
 SPARC,
 IBM POWER instruction set,
 Alpha, RISC-V,
 ARM architecture.
PIPELINING IN RISC
 RISC instructions are simple and engage one word (32 bit) in the memory.
 Even the ‘location of operands’ within the’ word’ is the same for the different
instructions.
 Among all the instruction the Load and Store are the operations that accesses
memory operand.
 Most of the RISC instructions are register to register.
 If we consider the arithmetic and logic instructions related to registers only, then we
have two stages as follow:
 Instruction Fetch (IF): Fetching the instruction
 Instruction Execute (IE): ALU operation with the register
 If we are considering the Load and Store instruction i.e. register to memory or memory
to register, then three stages are required as follow.
 Instruction Fetch (IF): Fetching the instruction
 Instruction Execute (IE): Calculate memory address
 Memory Store (M): register to register operation or memory to memory operation
RISC INSTRUCTION SETS
 RISC instructions are simple and are of fixed size.
 Each RISC instruction engages a single memory word.
 RISC instructions operate on processor registers only.
 The instructions that have arithmetic and logic operation should have their
operand either in the processor register or should be given directly in the
instruction.
 Example of operands in registers
 Add R2, R3
 Add R2, R3, R4
 The operand can be mentioned directly in the instruction as below:
 Add R2, 100
LOAD AND STORE

 But initially, at the start of execution of the program, all the operands are
in memory.
 So, to access the memory operands, the RISC instruction set
has Load and Store instruction.
 The Load instruction loads the operand present in memory to the
processor register. The load instruction is of the form:
 Load destination, Source
 Example Load R2, A // memory to register

 The load instruction above will load the operand present at memory
location A to the processor register R2.
CONT..

 The Store instruction stores the operand back to the memory.

 Store source, destination
 Example Store R2, A // register to memory
 The Store instruction will store the content of register R2 into the A (a memory location).
PIPELINING REVISITED

 Now consider the following instruction: A  B + C

 Creating a RISC instruction set for the above instruction will be.
Load R1, B
Load R2, C
Add R3, R2, R1
Store R3, C

 The pipelined instructions fasten the execution twice when compared to execution in
sequence. The instruction execution stage of first instruction & instruction fetch stage
of second instruction is performed parallelly.
 Observing the figure we can see that the execute/memory stage of second
instruction has to stall till the first instruction memory stage completes. This is the case
when we use the single port memory i.e. only one memory access can be done at a
time.
 USE OF NOOP
 The above stalling condition reduces the
execution speed.
 To overcome this, we can use NOOP (No
Operation) instruction which can be inserted in
the instruction stream by the compiler or
assembler.
 This would speed up the execution as all the
stages are of equal duration.
 But, what if the execution stage is longer, as it ALU
operation.
 In this case, the IE stage is divided in two parts
IE1 register reading and IE2 ALU operation.
ADVANTAGES OF RISC PROCESSOR
 RISC instructions are simpler machine instruction.
 RISC instructions are hardwired to fasten the execution.
 There are very fewer instructions in s RISC instruction set.
 RISC instruction has simple addressing modes.
 RISC instruction executes faster because most of instruction operates on processor
register and there is no need to access memory for each instruction.
 It is easy to pipeline RISC instruction as all instruction is of fixed size and opcode
and operand are located in the same position in the word.
 RISC instructions execute one instruction per clock cycle.
DISADVANTAGES OF RISC PROCESSOR
 RISC instruction size is reduced but more instructions are required to perform an
operation when compared with CISC. So, we can say that the length of the
program is increased.
 The machine instructions are hardwired in RISC so, it would cost if any instruction
needs modification.
 It finds is difficulty in processing complex instruction and complex addressing
mode.
 RISC instructions do not allow direct memory to memory transfer, it requires Load
and Store instructions to do so.
SUMMARY
 RISC instructions are simple and engages one word in memory.
 RISC instructions are of fixed size, the opcode and the operands in the instruction
are located in the same position within a word in different instructions.
 One instruction in RISC architecture executes in one clock cycle.
 The instruction size is reduced but, it has increased the program length.
 The pipelining of RISC instruction is easier.
 The machine instructions in RISC architecture are hardwired.
 RISC instruction operates only on register operands.
 RISC instruction executes faster as registers are placed in the processor chip which
is faster available memory resource.
 RISC instruction performs memory to memory transfer via Load and Store instruction.
INTRODUCTION TO ARM PROCESSORS
INTRODUCTION

 ARM is a 32-bit reduced instruction set computer (RISC) instruction set

architecture (ISA) developed by ARM Holdings.
 The ARM architecture is the most widely used 32-bit ISA in terms of numbers
produced.
 The first ARM processor was developed in the year 1978 by Cambridge University,
and the first ARM RISC processor was produced by the Acorn Group of
Computers in the year 1985.
 These processors are specifically used in portable devices like digital cameras,
mobile phones, home networking modules and wireless applications and
embedded system design due to the benefits, such as low power consumption,
reasonable performance, etc.
 FEATURES
 The main features of ARM Processor are mentioned below :
 Multiprocessing Systems
 ARM processors are designed so that they can be used in cases of multiprocessing systems where
more than one processors are used to process information.
 Tightly Coupled Memory
 Memory of ARM processors is tightly coupled. This has very fast response time (shared memory). It
has low latency (quick response) that can also be used in cases of cache memory being
unpredictable.
 Memory Management
 ARM processor has management section. This includes Memory Management Unit and Memory
Protection Unit. These management systems become very important in managing memory
efficiently.
 Thumb-2 Technology
 Thumb-2 Technology was introduced in 2003 and was used to create variable length instruction
set. It extends 16-bit instructions of initial Thumb technology to 32-bit instructions.
CONT..
 One cycle execution time
 ARM processor is optimised for each instruction on CPU. Each instruction is of fixed
length that allows time for fetching future instructions before executing present
instruction. ARM has CPI (Clock Per Insttuction) of one cycle.
 Pipelining
 Processing of instructions is done in parallel using pipelines. Instructions are broken
down and decoded in one pipeline stage. The pipeline advances one step at a time
to increase throughput (rate of processing).
 Large number of registers
 Large number of registers are used in ARM processor to prevent large amount of
memory interactions. Registers contain data and addresses. These act as local
memory store for all operations.
CONT..

 Most ARM’s implement two instruction sets

 32-bit ARM Instruction Set
 16-bit Thumb Instruction Set
 Jazelle cores can also execute Java bytecode
ARM ARCHITECTURE

 Arithmetic Logic Unit

 Booth multiplier
 Barrel shifter
 Control unit
 Register file
ARM ARCHITECTURE
 Arithmetic Logic Unit (ALU)
 The ALU has two 32-bits inputs.
 The primary comes from the register file, whereas the other comes from the shifter.
 Status registers flags modified by the ALU outputs.
 Booth Multiplier
 The multiplier factor has 3 32-bit inputs and the inputs return from the register file.
 Booth algorithm is a multiplication algorithmic rule for 2’s complement numbers.
 Barrel Shifter
 The barrel shifter features a 32-bit input to be shifted.
 Control Unit
 The control unit is sometimes a pure combinational circuit design.
 Here, the control unit is implemented by easy state machine. The processor timing is
additionally included within the control unit. Signals from the control unit are
connected to each component within the processor to supervise its operation.
REGISTER FILE
 ARM has 37 registers all of which are 32-bits long.
 1 dedicated program counter
 1 dedicated current program status register
 5 dedicated saved program status registers
 30 general purpose registers
 The Current Program Status Register (CPSR) holds execution status of the processor,
processor operation mode, interrupt enable bit status etc.
B31 B30 B29 B28 B27 B25 To B26 B24 B8 TO B23 B7 B6 B5 B4 To B0
N Z C V Q J I F T Mode Select

 A Saved Program Status Register (SPSR) stores the current value of the CPSR when an
exception is taken so that the CPSR can be restored after handling the exception.
Each exception handling mode can access its own SPSR. User mode and System
mode do not have an SPSR because they are not exception handling modes.
CONT..
 N, bit [31]
 Negative condition flag. Set to bit[31] of the result of the last flag-setting instruction. If the result is
regarded as a two's complement signed integer, then N is set to 1 if the result was negative, and
N is set to 0 if the result was positive or zero.
 Z, bit [30]
 Zero condition flag. Set to 1 if the result of the last flag-setting instruction was zero, and to 0
otherwise. A result of zero often indicates an equal result from a comparison.
 C, bit [29]
 Carry condition flag. Set to 1 if the last flag-setting instruction resulted in a carry condition, for
example an unsigned overflow on an addition.
 V, bit [28]
 Overflow condition flag. Set to 1 if the last flag-setting instruction resulted in an overflow condition,
for example a signed overflow on an addition.

B31 B30 B29 B28 B27 B25 To B26 B24 B8 TO B23 B7 B6 B5 B4 To B0

N Z C V Q J I F T Mode Select
CONT..
 Q, bit [27]
 Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some
instructions.
 Bits [26:25]
 Reserved, RES0.
 J, Bit [24]
 Jazelle is the hardware implementation of the Java Virtual Machine (JVM) for executing
Java codes.
 Bits [23:8]
 Reserved.
 I, Bit [7]
 IRQ mask bit.

B31 B30 B29 B28 B27 B25 To B26 B24 B8 TO B23 B7 B6 B5 B4 To B0

N Z C V Q J I F T Mode Select
CONT..

 F, Bit [6]
 FRQ mask bit.
 T, Bit [5]
 T=32 bit ARM instruction or Thumb Instructions
 Mode Select, Bit [4:0]
 for selecting different operating modes

B31 B30 B29 B28 B27 B25 To B26 B24 B8 TO B23 B7 B6 B5 B4 To B0

N Z C V Q J I F T Mode Select
MODES
 The ARM has seven basic operating modes:
 User: unprivileged mode under which most tasks run
 Fast Interrupt Processing (FIQ): entered when a high priority (fast)
interrupt is raised
 Normal Interrupt Processing (IRQ): entered when a low priority
(normal) interrupt is raised
 Supervisor: entered on reset and when a Software Interrupt
instruction is executed
 Abort: used to handle memory access violations
 Undefined: used to handle undefined instructions
 System: privileged mode using the same registers as user mode
CONT..

 The current processor mode governs which of several banks is accessible.

 Each mode can access
 a particular set of r0-r12 registers
 a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
 the program counter, r15 (pc)
 the current program status register, cpsr
 Privileged modes (except System) can also access
 a particular SPSR (saved program status register)
REGISTER ORGANIZATION FOR
VARIOUS MODES

r0 r0
r1 r1
r2 r8 r2
r3 r9 r3
: r10 :
r12 r11 r12
r13 (SP) r12 r13 (SP)
r14 (LR) r13 (SP) r13 (SP) r13 (SP) r13 (SP) r13 (SP) r14 (LR)
r15 (PC) r14 (LR) r14 (LR) r14 (LR) r14 (LR) r14 (LR) r15 (PC)

CPSR SPSR SPSR SPSR SPSR SPSR CPSR

User FIQ IRQ Supervisor Undefined Abort System

END OF SLIDES