Computer Architecture and

Organization
Lecture 6
RISC Vs CISC

1
 Introduction

An important aspect of computer architecture is the design of the

instruction set for the processor.
The instruction set chosen for a particular computer determines the
way that machine language programs are constructed.
Early computers had small and simple instruction sets
As digital hardware became cheaper integrated circuits, instructions
increase both in number and complexity.
 Introduction
Many computers have instruction sets that include more than 100 and
sometimes even more than 200 instructions.
 These computers also employ a variety of data types and a large
number of addressing modes.
 The trend into computer hardware complexity was influenced by
various factors, such as upgrading existing models to provide more
customer applications, adding instructions that facilitate the translation
from high-level language into machine language
 CISC

CISC is an acronym for Complex Instruction Set Computer and are chips
that are easy to program and which make efficient use of memory.
It is a processor design where single instructions can execute several low-
level operations such as
A load from memory,
An arithmetic operation,
And a memory store) or
 are capable of multi-step operations or addressing modes within single
instructions.
 Characteristics of CISC

 A large number of instructions

 Some instructions that perform specialized tasks and are used
infrequently
 A large variety of addressing modes
 Variable length instruction formats
 Instruction that manipulate operands in memory
 Small number of general purpose registers
 RISC

Reduced Instruction Set Computer is a type of microprocessor architecture

that utilizes a small, highly-optimized set of instructions, rather than a
more specialized set of instructions often found in other types of
architectures.
A reduced instruction set computer (RISC) is a computer that uses a
central processing unit (CPU) that implements the processor design
principle of simplified instructions.
To day, RISC is the most efficient CPU architecture technology.
 Characteristics of RISC
Relatively few instructions
Relatively few addressing modes
Memory access limited to load and store instructions
All operations are done within the register of the CPU
Fixed-length and easily decoded instruction formats
Single-cycle instruction execution
Hardwired and micro-programmed control
A relatively large number of registers in the CPU
Efficient instruction pipelining
Compiler support for efficient translation of high-level programs into
machine language programs
 RISC Vs CISC : An Example

An Example of multiplication of two numbers in memory. Suppose that

the main memory stores the numbers. The execution unit is responsible
for carrying out all computations. However, the execution unit can only
operate on data that has been loaded into one of the four registers (A,B,
C, or D).
Let's say we want to find the product of two numbers - one stored in
location 100 and another stored in location 400 and store back the result
to 100
 RISC Vs CISC : An Example

CISC:-MUL 100,400;
finish the task in the minimum possible instructions by implementing
hardware which could understand and execute series of operations.
Thus the processor would come with a specific instruction ‘MUL’ in its
instruction set.
 ‘MUL’ will loads the two values from the memory into separate registers,
multiplies the operands in the execution unit, and then stores the product in
the appropriate location.
So, the entire task of multiplying two numbers can be completed with one
instruction.
 RISC Vs CISC : An Example

RISC processors use simple instructions that can be executed within one
clock cycle.
Thus, ‘MUL’ instruction will be divided into three instructions.
LOAD, which moves data from the memory bank to a register,
PROD, which finds the product of two operands located within the registers, and
STORE, which moves data from a register to the memory banks.
In order to perform the task, a programmer would need to code four lines
of assembly:
LOAD A, 100
LOAD B, 400
PROD A, B
STORE 100, A
 From the Example:
RISC design uses more lines of code and hence, more RAM is
needed to store the assembly level instructions.
RISC "reduced instructions" require less transistors of hardware
space than the complex instructions, leaving more room for general
purpose registers.
As all of the instructions execute in a uniform amount of time (i.e.
one clock), pipelining is possible.
 Separating the "LOAD" and "STORE" instructions actually reduces
the amount of work that the computer must perform.
Computer Architecture and
Organization

Control Unit
12
 Micro-operations
The execution of a program consists of the sequential execution of
instructions.
 Each instruction is executed during an instruction cycle made up of
shorter sub-cycles (fetch, indirect, execute, interrupt)
 The execution of each sub-cycle involves one or more shorter operations,
that is, micro-operations
Micro-operations are the functional or atomic operations of a processor.
Micro-operations
 The Fetch Cycle
Causes an instruction to be fetched from memory. Four registers are
involved:
 Memory Address Register (MAR)
 Connected to address bus
Specifies address for read or write operation
 Memory Buffer Register (MBR)
 Connected to data bus
 Holds data to write or last data read
 Program Counter (PC)
 Holds address of next instruction to be fetched
Instruction Register (IR)
 Holds last instruction fetched
 The Fetch Cycle

Let us look at the sequence of events for the fetch cycle

At the beginning of the fetch cycle, the address of the next instruction to be
executed is in the program counter (PC); in this case, the address is 1100100.
The first step is to move that address to the memory address register (MAR)
because this is the only register connected to the address lines of the system
bus.
 The second step is to bring in the instruction.
 The Fetch Cycle
 A single fetch cycle, actually consists of three steps and four micro-operations.

Fetch Sequence
Address of next instruction is in PC
Address (MAR) is placed on address bus
 Control unit issues READ command
 Result (data from memory) appears on data bus
 Data from data bus copied into MBR
 PC incremented by 1 (in parallel with data fetch from memory)
 Data (instruction) moved from MBR to IR
 MBR is now free for further data fetches
 The Fetch Cycle
Fetch Sequence (symbolically)

OR
 Rules for Clock Cycle Grouping
The groupings of micro-operations must follow two simple rules:

1. The proper sequence of events must be followed.

 Thus MAR <- (PC) must precede MBR <- (memory) because the memory read
operation makes use of the address in the MAR.

2. Conflicts must be avoided.

One should not attempt to read to and write from the same register in one time unit,
because the results would be unpredictable.
Also: PC <- (PC) +1 involves addition
Use ALU
 May need additional micro-operations
 The Indirect Cycle
Once an instruction is fetched, the next step is to fetch source operands.
 If the instruction specifies an indirect address, then an indirect cycle must
precede the execute cycle.

MAR <- (IRaddress) - address field of IR

MBR <- (memory)
IRaddress <- (MBRaddress)
 MBR contains an address
 IR is now in same state as if direct addressing had been used
 Interrupt Cycle
 At the completion of the execute cycle, a test is made to determine whether
any enabled interrupts are occurred.
If so the interrupt cycle occurs.

t1: MBR <-(PC)

t2: MAR <- save-address
PC <- routine-address
t3: Memory <- (MBR)

 This is a minimum
 May be additional micro-ops to get addresses
 N.B. saving context is done by interrupt handler routine, not micro-ops
 The Execute Cycle
 First, consider an ADD instruction:
ADD R1,X
(Add the contents of location X to Register 1 , result in R1)
t1: MAR <- (IRaddress)
t2: MBR <- (memory)
t3: R1 <- R1 + (MBR)

Lets look at : ISZ X - increment and skip if zero instruction.

t1: MAR <- (IRaddress)

t2: MBR <- (memory)
t3: MBR <- (MBR) + 1
t4: memory <- (MBR)
if (MBR) == 0 then PC <- (PC) + 1
 The Execute Cycle
BSA X - Branch and save address instruction
Address of instruction following BSA is saved in X and the
execution continues from X+1

t1: MAR <- (IRaddress)

MBR <- (PC)
t2: PC <- (IRaddress)
memory <- (MBR)
t3: PC <- (PC) + 1
 Control of the Processor
Functional Requirements
 Functional requirements for the control units are those functions that the control unit
must perform.
 Basic functional elements of the processor are:
 ALU
 Registers
 Internal data paths
 External data paths
 Control Unit
Types of Micro-operation
 Transfer data between registers
Transfer data from register to external
 Transfer data from external to register
 Perform arithmetic or logical ops
 Control of the Processor

Functions of Control Unit

 Sequencing: Causing the CPU to step through a series of microoperations
in the proper sequence, based on the program being executed.
 Execution: Causes each micro-operations to be performed
 This is done using Control Signals
Control Signals
 Control Signals: Inputs
 Clock
 The control unit causes one micro-instruction (or set of parallel microinstructions) to
be performed per clock cycle
 Instruction register
 Op-code for current instruction
 Determines which micro-instructions are performed
Flags
State of CPU
 Results of previous operations
 From control bus
 Interrupts
Acknowledgements
 Control Signals: Outputs

 Control signals within CPU:

 Cause data movement from one register to another
Activate specific ALU functions
Control signals to control bus:
 To memory
 To I/O modules

Reading Ass: Control Signal Example page 572

Hardwired Implementation page 581
Question???

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