MODULE – V 18CS34: Computer Organization

MODULE-5
Basic Processing Unit
5.1 Introduction
 Instruction Set Processor (ISP) or processor executes machine instructions and
coordinates the activities of other units.
 It is also termed Central Processing Unit (CPU). The term “Central” is less
appropriate today because many modern computer systems include several
processing units.
 Organization of processors has evolved over the years, driven by developments in
technology and need to provide high performance.
 To achieve high performance, make various functional units operate in parallel.
 Such high performance processors have:
* Pipelined organization – execution of one instruction is started before the
execution of preceding instruction is completed.
* Superscalar operation – several instructions are fetched and executed at the
same time.
 Here, we discuss on basic ideas that are common to all processors.

5.2 SOME FUNDAMENTAL CONCEPTS

 To execute a program, the processor fetches one instruction at a time and
performs the operations specified.
 To execute an instruction, the processor has to perform the following 3 steps:
1. Fetch the contents of the memory location pointed to by the PC. The content of
this location is the instruction to be executed. Hence, load into IR.
IR [[PC]]
2. Assuming memory is byte addressable, increment the contents of the
PC by 4
PC [PC] + 4
3. Carry out the actions specified by the instruction in the IR.
1 & 2 are fetch phase. 3 is execution phase.

 Register MDR has 2 inputs and 2 outputs.

 Register MAR gets input from internal bus and gives output to the external
bus.
 The control lines of memory bus are connected to the instruction decoder
and control logic block.
 This unit is responsible for issuing the signals that control the operation of all
the units inside the processor and for interacting with memory bus.
 R0 to R(n-1) are the general-purpose registers used by the programmer.
 Special purpose registers are index or stack pointers.

Dr. M J Sudhamani, Dept of CSE, RNSIT 1

MODULE – V 18CS34: Computer Organization

 Y,Z, TEMP are registers that are never referenced by an instruction.

 They are used by the processor for temporary storage during execution of
some instructions.
 MUX – multiplexer selects either output of Y or constant 4 (to increment the
contents of program counter).

 2 possible values of MUX control input Select are Select4 and SelectY.
 As instruction execution progresses, data are transferred from one register
to another, passing through ALU to perform arithmetic and logic operation.
 Instruction decoder and control logic unit is responsible for implementing the
actions specified by instruction loaded in the IR register.
 Decoder generates the control signals needed to select the registers
involved and direct the transfer of data.
 ALU and interconnecting bus is referred to as data path.
 An instruction can be executed by performing one or more of the following
operations in some specified sequence:

Dr. M J Sudhamani, Dept of CSE, RNSIT 2

MODULE – V 18CS34: Computer Organization

 Ri , Rj: Transfer a word of data from one processor register to another or to

the ALU.

5.2.1 Register Transfers

 Instruction execution involves data transfers from one register to another.
 For each register, 2 control signals are used. It is represented symbolically as
shown in Figure 7.2.

 are switches controlled by signals Riin and Riout.

 When Riin is set to 1, the data on the bus are loaded into Ri.
 When Riout. is set to 1, the contents of register Ri are placed on the bus.

Dr. M J Sudhamani, Dept of CSE, RNSIT 3

MODULE – V 18CS34: Computer Organization

Move R1,R4 is an instruction. This can be accomplished as follows:

o Enable the output of R1 by setting R1out to 1. This places the contents of R1
on the processor bus.
o Enable the input of R4 by setting R4in to 1. This loads data from processor
bus into R4.
 All operations and data transfers within processor takes place within time periods
defined by processor clock.
 Example: At the start of clock cycle, R1out and R4in are set to 1.
 Registers are edge-triggered flip-flops.
 At next active edge of clock, data is loaded into R4. At the same time, R1out and
R4in return to 0.
Alternate approach:
 Data transfers may use both rising and falling edges of the clock.
 When edge-triggered flip-flops are not used, 2 or more clock signals may be
needed to guarantee proper transfer of data. This is multi phase clocking.

 When Riin=1, mux selects data on the bus. Data is loaded into flip-flop at rising
edge of the clock.
 When Riin=0, mux feeds back the value currently stored in flip-flop.
 When Riout=0, gate’s output is in high-impedance (electrically disconnected) state.
i.e. open- state of switch.
 When Riout=1, gate drives the bus to 0 or 1, depending on the value of Q.

5.2.2 Performing an Arithmetic or logic operation

 The ALU is a combinational circuit that has no internal storage. Input to ALU is
through mux and from the processor bus.
 Output is stored temporarily in register Z.

Dr. M J Sudhamani, Dept of CSE, RNSIT 4

MODULE – V 18CS34: Computer Organization

Sequence of operations to perform Add R1,R2,R3

1. R1out, Yin
2. R2out, SelectY,Add,Zin
3. Zout, R3in
 Only one register output can be connected to the bus during any clock cycle.

5.2.3 Fetching a word from memory

 To fetch a word of information from memory, processor has to specify the address
of the memory location where this information is stored and request a Read
operation.
 Information can be instruction or an operand
 Processor transfers the required address to MAR.
 Processor uses control lines to indicate that a Read operation is needed.
 When requested data are received from the memory , they are stored in register
MDR

 The processor completes one internal data transfer in one clock cycle.
 The speed of operation of the addressed device varies with the device.
 Devices include cache memory, register in memory mapped I/O devices, main
memory, etc.
 The cache responds to a read request in one clock cycle.
 When cache miss occurs, request is forwarded to main memory which introduces
several clock cycles delay.
 To accommodate variability in response time, the processor waits until it receives
an indication that requested Read operation has been completed.
 A control signal called Memory Function Completed(MFC) is used for this purpose.
 Addressed device sets this signal to 1 to indicate that the contents of the specified

Dr. M J Sudhamani, Dept of CSE, RNSIT 5

MODULE – V 18CS34: Computer Organization

location have been read and are available on the data lines of the memory bus.

 Consider the instruction Move (R1), R2. The actions needed to execute this
instruction are:
o MAR [R1]
o Start a Read operation on the memory bus.
o Wait for the MFC response from the memory.
o Load MDR from the memory bus.
o R2 [MDR]

 Contents of MAR are always available on the address lines of memory bus.
 When a new address is loaded into MAR, it will appear on the memory bus at the
beginning of the next clock cycle as shown.
 A Read control signal is activated at the same time MAR is loaded.
 This signal will cause the bus interface circuit to send a read command,
MR(Memory Read) on the bus.
 MDRinE is active waiting for a response from the memory.
 Data received from memory are loaded into MDR at the end of the clock cycle in

Dr. M J Sudhamani, Dept of CSE, RNSIT 6

MODULE – V 18CS34: Computer Organization

which MFC signal is received.

 In the next clock cycle. MDRout is activated to transfer the data to register R2.
 Signals are activated as follows:
1. R1out, MARin, Read
2. MDRinE, WMFC (wait for arrival of MFC signal.
3. MDRout, R2in

5.2.4 Storing a word in memory

 Desired address is loaded into MAR

 Data is loaded into MDR.
 Write command is issued

Move R2,(R1) requires the following sequence:

1. R1out, MARin
2. R2out, MDRin, Write
3. MDRoutE, WMFC
Note: WMFC:- Wait for arrival of MFC signal

5.3 EXECUTION OF A COMPLETE INSTRUCTION

Consider the instruction Add (R3), R1
 Executing this instruction requires the following actions:
o Fetch the instruction
o Fetch the first operand (the contents of the memory location pointed to by
R3).
o Perform the addition.
o Load the result into R1.
Control sequence for execution of the instruction Add (R3), R1
1. PCout, MARin, Read, Select4, Add, Zin
Fetch operation is initiated by loading the address in PC into MAR and sending a Read
request to the memory. Select signal is set to Select4, which causes the MUX to select
constant value 4. This value is added to the operand at input B (contents of PC) and
the result is stored in register Z.
2. Zout, PCin, Yin, WMFC
The updated value in Z is moved to PC (to point to the next address) while waiting for
the memory to respond.
3. MDRout, IRin
Once MFC signal is received from memory, the fetched instruction will be moved into
MDR and then to IR.
These 3 phases are instruction fetch phase.
4. R3out, MARin, Read
The instruction decoding circuit interprets the contents of IR and the processor starts
the execution phase. Contents of R3 (address of the operand) are loaded into MAR

Dr. M J Sudhamani, Dept of CSE, RNSIT 7

MODULE – V 18CS34: Computer Organization

and a Read signal is issued.

5. R1out, Yin, WMFC
While waiting for the memory to respond, contents of R1 are transferred into Y register.
6. MDRout, SelectY, Add, Zin
The memory provides data on the bus, which is moved into MDR and onto the B input
of ALU. The contents of Y (R1 contents) are gated into input A of ALU using SelectY
signal of MUX.
Add control signal is activated.
After addition, result is transferred to Z.
7. Zout, R1in, End.
Finally, the sum is moved out of register Z into R1. The End signal causes new
instruction fetch cycle to begin by returning to step 1.

Ex: Control sequence for the instruction Add (R3)+,, R1

1. PCout, MARin, Read, Select4, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read, Select4, Add, Zin
5. Zout, R3in
6. R1out, Yin, WMFC
7. MDRout, SelectY, Add, Zin
8. Zout, R1in, End

Dr. M J Sudhamani, Dept of CSE, RNSIT 8

MODULE – V 18CS34: Computer Organization

5.3.1 Branch Instructions

 A branch instruction replaces the contents of the PC with the branch target
address.
 This address is usually obtained by adding an offset X, which is given in the
branch instruction, to the updated value of PC.

 The offset X used in a branch instruction is the difference between the branch
target address and the address immediately following the branch instruction.
 Ex:- If branch instruction is at 2000, branch target address is 2050, then value of X
must be 46. (This is because PC would have incremented during fetch phase, so it
would be pointing to 2004 already. Therefore, only 46 is the offset.)
 For a conditional branch, we need to check status of condition codes before
loading a new value into PC.
 For (Branch > 0) instruction, Step 4 is replaced with Offset-field-of IRout, Add, Zin, If
N=0, then End.If N=0, the processor returns to step 1 immediately after step 4.
 If N=1, step 5 is performed to load a new value into PC, thus performing the branch
operation.

5.4 Multiple-Bus Organization

 Single bus structure results in control sequences which are quite long because only
one item can be transferred over the bus in 1 clock cycle.
 To reduce the number of steps and enhance the CPU performance, modern
processors provide multiple internal paths that enable several transfers to take
place in parallel.

Dr. M J Sudhamani, Dept of CSE, RNSIT 9

MODULE – V 18CS34: Computer Organization

All general purpose registers are combined into a single block called the register file.
 Register file has 3 parts.
o 2 output’s allowing contents of two different registers to be accessed
simultaneously and their contents are placed on A and B.
o 1 port allows the data on C to be loaded into third register during the same
clock cycle.
 Buses A and B are used to transfer the source operands to the A and B inputs of
ALU.
 Output of ALU is transferred over bus C.
 If ALU simple pass one of its two input operands unmodified to bus C, indicate
using R=A or R=B
 Using incremental eliminates the need to add 4 to PC using ALU and add
operation.

Ex: - Control sequence for the instruction Add R4, R5, R6 for the 3-bus organization

Dr. M J Sudhamani, Dept of CSE, RNSIT 10

MODULE – V 18CS34: Computer Organization

1. PCout, R=B, MARin, Read, IncPC

Contents of PC are passed through ALU using R=B control signal and loaded into
MAR to start a memory read operation. PC is incremented by 4 to point to the next
instruction in sequence.
2. WMFC
Processor waits for MFC signal from memory.
3. MDRoutB, R=B, IRin
The instruction code is received in MDR and transferred to IR.this completes the fetch
phase.
4. R4outA, R5outB, SelectA, Add, R6in, End.
The instruction is decoded and add operation takes place.

5.5 Hardwired Control

 To execute instructions, processor must have some means of generating the
control signals needed in proper sequence.
 Two approaches:
o Hardwired control
o Microprogrammed control

 The decoder/encoder block is a combinational circuit that generates the requested

control signals (outputs) depending on the states of all its inputs.

Dr. M J Sudhamani, Dept of CSE, RNSIT 11

MODULE – V 18CS34: Computer Organization

 The step decoder provides a separate signal line for each step, or time slot, in the
control sequence.
 Output of instruction decoder consists of a separate line for each machine
instruction.
 For any instruction loaded in IR, one of the output lines INS1 through INSm is set to
1 and all other lines are set to 0.
 Input signals to the encoder block are combined to generate the individual control
signals like Yin, PCout, Add, End, etc.

Dr. M J Sudhamani, Dept of CSE, RNSIT 12

MODULE – V 18CS34: Computer Organization

 This circuit implements the logic function: Zin= T1+T4.Br+T6.Add+...

 This signal is asserted during time slot T1 for all instructions, during T4 for
unconditional branch instructions and T6 for an Add instruction.

RUN control signal:

 When set to 1, RUN causes the counter to be incremented by one at the end of
every clock cycle.
 When set to 0, the counter stops counting. This is needed when WMFC signal is
issued, to cause the processor to wait for reply from memory.

 Logic Function:
 End signal starts a new instruction fetch cycle by resetting the control step counter
to its starting value.
 The control hardware can be viewed as a state machine that changes from one
state to another in every clock cycle, depending on the contents of IR, condition
codes and external inputs.
 Output of the state machine are control signals
 Sequence of operations carried out by the machine is determined by wiring of the
logic elements, hence the name “hardwired”.

5.5.1 A Complete Processor

 Instruction unit fetches the instructions from an instruction cache or from the main
memory when the desired instructions are not already in cache.
 It has separate processing units to deal with integer data and floating-point data.

Dr. M J Sudhamani, Dept of CSE, RNSIT 13

MODULE – V 18CS34: Computer Organization

 Most of the processors today use separate caches for instructions and data.
 Processor is connected to the system bus through bus interface.
 To increase the potential for concurrent operations, several integer and floating
point units.
5.6 Micro programmed Control
 Using hardwired control, the control signals required inside the processor can be
generated using a control step counter and a decoder/ encoder circuit.
 In micro programmed control, the control signals are generated by a program
similar to machine language programs.
 A control word (CW) is a word whose individual bits represent the various control
signals.
 A sequence of CWs corresponding to the control sequence of a machine
instruction constitutes the micro routine for that instruction.
 Individual control words in this micro routine are referred to as micro instructions.
The micro routines for all instructions in the instruction set of a computer are stored
in special memory called the control store.

Dr. M J Sudhamani, Dept of CSE, RNSIT 14

MODULE – V 18CS34: Computer Organization

The control unit can generate the control signals for any instruction by sequentially reading
the CWs of the micro routine from the control store.To accomplish this, the organization of
CU can be:
 Micro Program Counter (µPC) is used to read the control words sequentially from the
control store.
 Every time a new instruction is loaded into the IR, the output of the block labelled
“starting address generator” is loaded into the µPC.
 µPC is automatically incremented by the clock, causing successive micro
instructions to be read from the control store.

Dr. M J Sudhamani, Dept of CSE, RNSIT 15

MODULE – V 18CS34: Computer Organization

 Therefore, the control signals are delivered to various parts of the processor in
correct sequence.
 This organization cannot handle a situation, wherein the CU has to check the
status of condition codes or external inputs.
 Hardwired control handles this situation by including an appropriate logic function
in the encoder circuit.

In micro programmed control, alternative approach is used for conditional branch micro
instructions.
 The micro-routine for Branch instruction says that: After loading Branch<0 into IR, a
branch microinstruction transfers control to the corresponding micro-routine, which
is assumed to start at location 25 in control store.
 The micro instructions at location 25 tests the N bit of condition codes.
o If it is 0, a branch takes place to location 0 to fetch a new machine
instruction.
o Otherwise, microinstruction at location 26 is executed. Then 27 is followed.
 To support this micro program branching, CU is as shown:

Dr. M J Sudhamani, Dept of CSE, RNSIT 16

MODULE – V 18CS34: Computer Organization

5.6.1 Micro instructions

 A straight forward way to structure micro instructions is to assign one bit position to
each control signal.
 This scheme has a serious drawback – assigning individual bits to each control
signal results in long micro instructions because the number of required signals is
large.
 Only few bits are set to 1, which means the available bit space is poorly used.

Approaches to design a format for micro instructions:

1) Assuming that a processor contains only 4 general-purpose registers, R0,R1,R2 and
R3.
 Enable some of the connections in this processor permanently. Such as
output of IR to decoding circuits – both inputs to the ALU.
 Connections to various registers require 20 gating signals
 Control signals like Read, Write, Select, WMFC and End signals need
space.
 Assuming 16 functions to perform ALU including Add, Subtract, AND and
XOR.
 In total 42 control signals are needed.
 Disadvantage of this approach: Most signals are not needed simultaneously,
and many signals are mutually exclusive. This space can be reduced.
2) The signals can be grouped so that all mutually exclusive signals are placed in same
group.
A binary coding scheme is used to represent the signals within a group. In this CU,
the µPC is incremented every time a new microinstruction is fetched from the micro
program memory, except in the following situations:
 When a new instruction is loaded into IR, the µPC is loaded with starting
address of µroutine for that instruction.
 When a Branch µinstruction is encountered and the branch condition is
satisfied, the µPC is loaded with the branch address.
 When an End µinstruction is encountered, the µPC is loaded with the
address of first CW in the µ-routine for instruction fetch cycle.

Dr. M J Sudhamani, Dept of CSE, RNSIT 17

MODULE – V 18CS34: Computer Organization

Disadvantage of this approach: this format requires a little more hardware because decoding
circuits must be used to decode the bit patterns of each field into individual control signals.
Advantage: - This format results in smaller control store Only 20 bits are needed to store the
patterns for 42 signals.
3) Enumerating the patterns of required signals in all possible microinstructions.
 Each meaningful combination of active control signals can be assigned a
distinct code that represents the microinstruction.
 Such full encoding reduces the length of MW’s but increase complexity of
required decoder circuits.
 Such highly encoded schemes that use compact codes to specify only a
small number of control functions in each µinstruction are referred to as a
“vertical organization”.
 “Horizontal organization” is an encoded scheme in which many resources
can be controlled with a single ingle instruction as shown in Figure 7.15.
 This organization is useful when a higher operating speed is desired and

Dr. M J Sudhamani, Dept of CSE, RNSIT 18

MODULE – V 18CS34: Computer Organization

when the machine structure allows parallel use of resources

 The second approach is a horizontal organization.

5.6.2 Micro program Sequencing

 A simple micro program using the format in Figure 7.15 is fairly simple for writing
and verification. But this scheme has 2 disadvantages:
o Requirement of large control store, since each machine instruction has a
separate micro routine.
o If the machine instructions have several addressing modes, a separate
micro routine for each of these combinations may produce duplication of
common parts of the program.
 To solve these problems, the microprogram should be organized so that micro
routines share the common parts
o This requires many branch instructions to transfer control among various
parts.
o This leads to another problem-program execution time will be longer since
more time is required to carry out the branch instructions.
 Consider an instruction “Add src,Rdst” to illustrate the complexity of sequencing the
operations
 This instruction adds the source operand to the contents of register Rdst and
places the sum in Rdst, the destination register.
 Source operand can be in any of the following addressing modes: register, auto
increment, auto decrement, indexed, indirect.
 A microprogram is presented in flowchart form, for easier understanding.
 Each box in the chart represents a microinstruction that controls the transfers and
operations indicated within the box.
 The microinstruction (µinstruction) is located at the address indicated by the octal
number above the upper right-hand corner of the box.
 Each octal digit represents 3 bits.
 Techniques used:
Branch Address Modification using Bit-ORing
 From the flowchart, it can be seen that branches are made to different
addresses because some parts of the micro routineis shared among all the
microprograms
 At a point labelled α, a decision is to be made about branching:
o If direct mode is specified, instruction at location 170 is bypassed and
control goes to 171
o If indirect mode is specified, then the µinstruction at location 170 is
executed to fetch the operand from memory.
 This is performed using a technique called bit-ORing.

Dr. M J Sudhamani, Dept of CSE, RNSIT 19

MODULE – V 18CS34: Computer Organization

Bit-ORing
 Simplest way to transfer control directly to location 171 is to make the preceding
branch µinstruction specify the address 170 and then use an OR gate to change
the LSB of this address to 1 if direct addressing mode is specified. This is known as
bit-ORing technique.

Dr. M J Sudhamani, Dept of CSE, RNSIT 20

MODULE – V 18CS34: Computer Organization

5.6.3 Wide-Branch Addressing

 The flowchart includes a wide branch in the µinstruction at location 003.
 The instruction decoder, InstDec generates the starting address of the µroutine that
implements the instruction that has just been loaded into IR.
 In our example, the instruction “Add src, Rdst” is loaded into IR.
 The instruction decoder generates µinstruction address 101.
 However, this address cannot be loaded as it is into the µPC, because src operand
can be in any of the several addressing modes.
 The flowchart shows 5 possible branches starting from left to right: indexed, auto
decrement, auto increment, register direct and register indirect.
 Bit-ORing technique is used to modify the starting address generated by the
instruction decoder to reach the appropriate path.
 WMFC is used in a branch µinstruction because branch must not take place until
the memory transfer in progress is completed.
 A case of source operand being accessed in auto increment mode:
Add (Rsrc)+,Rdst

Dr. M J Sudhamani, Dept of CSE, RNSIT 21

MODULE – V 18CS34: Computer Organization

Octal Binary
Address generated by instruction decoder 101 001 000 001
Indexed 161 001 110 001
Autodecrement 141 001 100 001
Autoincrement 121 001 010 001
Register direct 101 001 000 001
Register indirect 111 001 001 001

Mode Bits Assumptions:

10th Bit 9th Bit Mode
1 1 Indexed
1 0 Autodecrement
0 1 Autoincrement
0 0 Register

8th Bit
0 Direct
1 Indirect

 Processor has 16 registers being used for addressing, each specified using 4-bit
code.
 There are 2 stages of decoding:
o The microinstruction field must be decoded to determine that an Rsrc orRdst
register is involved.
o The decoded output is then used to gate the contents of the Rsrc or Rdst
fields in IR. Into second decoder, which produces the gating signals for
actual registers R0 to R15
 The micro routine for Add (Rsrc)+Rdst has two Bit-ORing examples:
1) Microinstruction at location 003:
 There are 5 starting addresses for the micro routine depending on the
addressing mode.
 These addresses differ in the middle octal digit only.
 The 3 bits to be ORed with the middle digit are supplied by decoding circuitry
connected to the src address.

2) Microinstruction at location 123:

 It causes a branch to the microinstruction at location 170, which causes
another fetch from memory using indirect addressing mode.
 Using direct addressing mode, the above additional fetch is bypassed by
ORing the inverse of the indirect bit in the src address field (bit 8 in the IR)
with the 0-bit position of the micro processor

Dr. M J Sudhamani, Dept of CSE, RNSIT 22

MODULE – V 18CS34: Computer Organization

5.6.4 Microinstructions with next-address field

 The flowchart in Figure 7.20 contains several branch µinstructions which perform
no useful operation in the data path.
 These instructions are needed only to determine the address of the next
µinstruction.
 More number of such instructions will reduce the speed of computation.
 Solution to this problem is:
o Include an address field as part of every µinstruction to indicate the location of
next µinstruction to be fetched.
 Advantage of this scheme is:
o Need for separate branch µinstruction is eliminated.
o No need of a counter to keep track of address. Therefore, µPC is replaced
by µAR(microinstruction Address Register). This register is loaded from next
address field of each µinstruction.
 New micro programming control structure with µAR and bit-ORing capability can be
designed as:
 The decoding circuits generate the starting address of a given µroutine on the basis
of opcode in IR.
 The next address bits are fed through OR gates to µAR.

Dr. M J Sudhamani, Dept of CSE, RNSIT 23

MODULE – V 18CS34: Computer Organization

 The address can be modified depending on the data in the IR, condition codes and
external inputs.
 Reconsidering the instruction, “Add (Rsrc)+, Rdst”
o µroutine is shown in Figure 7.21
o if we use the control structure just designed, we need to modify the
µinstruction format designed on Figure 7.19
 Extra fields to be added along with the previous format are:
o Signal ORmode is used to indicate whether bit-ORing is used or not.
o Signal ORindsrc is used to indicate whether indirect addressing of source
operand is used for wide branching in the flowchart of Figure 7.20.
o One bit in the µinstruction is used to indicate when the output of the
instruction decoder is to be gated into the µAR.
o Each µinstruction contains an 8-bit field that holds the address of the next
µinstruction.

Dr. M J Sudhamani, Dept of CSE, RNSIT 24

MODULE – V 18CS34: Computer Organization

The branch µinstruction at location 123 is continued with 122.

 When µinstruction sequencing is controlled by µPC, the End signal is used to reset
the µPC to point to the starting address of the µinstruction that fetches the next
machine instruction to be executed.
 In the organization considering µAR, this starting address is 0008(i.e 000 in octal).
 End signal is explicitly specified in FO field.

Dr. M J Sudhamani, Dept of CSE, RNSIT 25

MODULE – V 18CS34: Computer Organization

 Figure 7.25 and 7.26 of textbook gives in detail picture of control structure of figure
7.22 and circuitry for bit-ORing.

5.6.5 Prefetching Microinstructions

 One drawback of µprogrammed control is that it leads to slower operating speed
because of the time it takes to fetch µinstructions from control store
 Faster operation is achieved if the next µinstruction is prefetched while the current
one is being executed.
 Execution time can be overlapped with fetch time.
 Prefetching has some problems:
o The status flags and results of currently executed µinstruction are needed to
determine the address of next µinstruction.
o Therefore, straightforward prefetching occasionally prefetches a wrong
µinstruction.
o In such cases, the fetch must be repeated with correct address, which
requests complex hardware.
 These disadvantages are minor and prefetching technique is often used.

Problem:
Write the control sequence of execution of the instruction ADD (R3),R1. For this
sequence of instructions, the processor is driven by a continuously running clock such
that each control step is 2ns in duration. How long will the processor have to wait in
steps 2 & 5, assuming that a memory read operation takes 16ns to complete? Also
compute the percentage of time for which the processor is idle during the execution of
this instruction.

Solution:
Control sequence:
1. PCout, MARin, Read, Select4, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Zout, R1in, End.

Total time in execution is: (5X2)+(2X16)=42ns There are totally 7 steps.

Each step takes 2 ns.
Step 2 & 5 takes 16ns
Therefore, 5 steps take 2 ns. Remaining 2 steps takes 16+16 = 32ns

Therefore, (5X2)+(2X16)=42ns

Dr. M J Sudhamani, Dept of CSE, RNSIT 26

MODULE – V 18CS34: Computer Organization

The processor is idle during memory read operations. i.e. for a duration of 32ns out of
42ns. Therefore, processor idle time = 32ns/42ns = 76.2% of the total time.

5.7 Comparison between Hardwired &Microprogrammed

control

Attribute Hardwired Control Microprogrammed Control

Speed Fast Slow

Control Function Implemented in hardware Implemented in software

Not flexible, to accommodate new More flexible, to accommodate new

Flexibility
system specifications or new system specification or new
instructions instructions redesign is required.

Ability to handle large/complex Difficult Easier

instruction sets

Ability to support OS & diagnostic

features Very difficult Easy

Design process Somewhat complicated Orderly & systematic

Mostly RISC microprocessors Mainframes, some microprocessors

Applications

Usually under 100 instructions

Instruction set size Usually over 100 instructions

2K to 10K by 20-40bit
ROM size - microinstructions

Chip area efficiency Uses least area Uses more area

Dr. M J Sudhamani, Dept of CSE, RNSIT 27