Microprocessor Technology-1

MICROPROCESSOR TECHNOLOGY
COT 05212
Sub-enabling
 Describe the concepts of microprocessor and micro-controller.
 Explain micro-processor architecture families (8085).
 Explain micro-controller architecture families (8086).
 Describe various memories of microprocessor system.
 Describe the architecture of microprocessor families 8085
 Describe the architecture of microprocessor families 8086
 Explain various registers and pointers of microprocessor systems
 Explain various types of interrupts
MICROPROCESSOR/MICRO-CONTROLLER
Microprocessors:
– is a multipurpose, programmable ,clock driven, register based electronic
device, that read binary instructions from storage device called
“memory”.
– Microprocessor: Accept the binary data as input and process data
according to those instructions and provides results as an output.
• A typical programmable machine/device can represented with three
components:
 Microprocessor
 Memory
 I/O
 These three component work /interact with each other to perform a
given task.
Microcontroller:
– is a small computer on a single metal-oxide-semiconductor (MOS)
integrated circuit (IC) chip.
– A microcontroller contains one or more CPUs (processor cores) along
with memory and programmable input/output peripherals.
Binary Digits
– Microprocessor operates in binary digits(bits) –(0,1)
– These digits are represented in terms of electrical voltage in machine.
– “0” represent low voltage level and “1” represent high voltage level.
– Each microprocessor recognizes and process a group of bits called “word”
– So, each microprocessor can be classified according to their “word length”
– Then, it means a microprocessor with an 8-bit word(length) is know as 8-bit
microprocessor.
*16-bit word?
*32-bit word?
Microprocessor as programmable device.
– Its programmable, means it can be instructed to perform a given tasks within
its capability.
– Its design to understand and execute many binary instructions, defined by its
instruction set.
• Memory
– Memory is like pages of notebooks with space of a fixed number of binary
numbers on each line.
– Memory are made of semiconductors material.
– Each line is an 8-bit register.
– Several arrangement of these register in a sequence is called “memory”
– These registers are always grouped together in power of two(2)
– An 8-bit register on a semiconductor chip is known as “1k bytes of
memory”_>>>>1024 bytes
• I/O
– User can enter instruction and data into memory through devices such as
keyboard or simple switches.[Input devices]
{then microprocessor can read the instructions from the memory and process
the data according to those instruction}
– The result can be displayed by a device such as seven segments LEDs or
printed by a printer
Assignment
1. Describe CPU may be referred as Microprocessor

MICROPROCESSOR CLASSIFICATION
• Based on their specification, application and architecture microprocessors are
classified.
– Based on size of data bus:
• 4-bit microprocessor
– Based on application:
• General-purpose microprocessor-
– used in general computer system and can be used by programmer for any application. Examples, 8085
to Intel Pentium.
• Microcontroller
– microprocessor with built-in memory and ports and can be programmed for any generic control
application. Example, 8051.
• Special-purpose processors:
– designed to handle special functions required for an application. Examples, digital signal processors and
application-specific integrated circuit (ASIC) chips.
– Based on architecture:
• Reduced Instruction Set Computer (RISC) processors
• Complex Instruction Set Computer (CISC) processors
TYPES OF MICROPROCESSOR
• There are different types of microprocessors designed to be used for specific
purposes. It has been evolved to be used in various different applications.
• They are mainly classified into three major types:
– CISC Microprocessor (Complex Instruction Set Computer).
– RISC Microprocessor(Reduced Instruction Set Computer).
– Special Purpose Microprocessor
• Coprocessor
• Transputer (Transistor Computer)
• DSP (Digital Signal Processor)
• Input/Output Processor (IOP)
• Graphics Processors
• Bit-Slice Microprocessors (BSM)
• Scalar and Superscalar Microprocessors
TYPES OF MICROPROCESSOR…
• CISC is an acronym for complex instruction set computer.
CISC MICROPROCESSOR
• This microprocessor is designed to execute complex instructions (a combination of

multiple single instructions) which minimize the number of total instructions per
program.
• A complex instruction has multiple simple instructions like arithmetic operation,
storing in memory, reading from memory, etc.
• The overall length of the program is relatively very small but due to the large size
of its instruction set with many addressing modes in a single instruction, it takes
multiples machine cycles to execute an instruction.
• Thus it reduces the execution speed of the microprocessor.
• Features of CISC Microprocessor:
– The instructions are complex.
– The numbers of instructions are relatively more than RISC microprocessor almost 100 to 200.
– It takes more than four cycles to somewhere around 120 to complete complex instructions.
– The program is executed sequentially thus no feature of pipelining (parallel execution).
– The instructions are executed by micro program where the complexity lies.
– The instruction format and size may vary as opposed to RISC fixed instructions.
– The program code in CISC is simple and short thus it uses less memory or RAM.
– It put emphasis on the hardware and less on the software or programming.
• RISC stands for Reduced Instruction Set Computer.
RISC MICROPROCESSOR
• This type of microprocessor is based on an architecture designed to execute simple

instructions.
• The instructions are simplified to reduce the execution time.
• The instruction is usually completed in one clock cycle by using pipelining to
execute parts of instruction in parallel.
• Therefore, it requires program code with more lines and more memory to store
instruction.
• This architecture offers to execute program efficiently and quickly.
• Features of RISC Microprocessor
– The instructions in RISC microprocessors are simple.
– As suggested by its name, the numbers of instructions are reduced to between 30 and 40.
– The instructions are simple thus it takes only one machine cycle to complete.
– Pipelining (parallel execution) is fairly easy in a RISC microprocessor.
– The format and size of instructions is limited and fixed.
– Due to the low number of instructions, the program code lengthy and require more memory.
– It put emphasis on the software or compiler and less on the load on the hardware.
Difference between RISC and CISC
s/no RISC CISC

1. Simple instruction set Complex instruction set
2. Consists of Large number of registers. Less number of registers
3. Larger Program Smaller program
4. Simple processor circuitry (small number of Complex processor circuitry (more number
transistors) of transistors)
5. More RAM usage Little Ram usage
6. Simple addressing modes Variety of addressing modes
7. Fixed length instructions Variable length instructions
8. Fixed number of clock cycles for executing Variable number of clock cycles for each
one instruction instructions
Special Purpose Microprocessor:
There are various types of microprocessors designed for special purposes. Here
are some the special purpose microprocessor given below;
 Coprocessor
 The coprocessor is a type of special-purpose processor that helps the main or primary processor in processing
complex tasks.
 It increases the performance of the primary processor by lend its processing power to reducing the load off the
primary processor.
 These are used in graphic, complex arithmetic operation, single processing and I/O interfacing operations.
 The coprocessor is physically separate from the main processor (CPU) and it works independently.
 They are very fast in executing a specific task because of its limited instruction set.
 Therefore, they cannot be used for general purpose applications like CPU.
 Transputer (Transistor Computer)
 The transputer is the first general-purpose computer designed by INMOS to perform parallel computing.
 It also incorporates internal memory with serial communication links to communicate between processors for
parallel operation.
 The name Transputer is the combination of “transistor” and “computer”.
 The name was chosen due to its similarity with a transistor as the building block in the computer.
 It is the building block of parallel computer & multiple transputers connect together to form a fully functioning
parallel computer.
 They were designed to be used together to perform the parallel operation but a single transputer has the
essential circuitry to work on its own.
Special Purpose Microprocessor:………
 DSP (Digital Signal Processor).
 The DSP or digital signal processor is a type of microprocessor specifically designed to
process any signal.
 The architecture of DSP is fairly optimized to process signals in applications such as audio
processing, speech recognition, image processing, radar, sonar, smartphones, etc.
 The main objective of DSP is to convert between analog and digital signal (known as ADC &
DAC) and process them by filtering, compressing & applying various algorithms in digital
format. It can process multiple signals at a time in parallel operation.
 Input/Output Processor (IOP)
 Input/output Processor or IOP is a special type of processor designed to control and
manages the input and output tasks of a computer.
 They have direct access to the memory and are similar to the CPU except they only process
I/O peripherals such as a mouse, keyboard, printer, display unit, etc.
 The CPU and IOP acts as master and slave, the CPU sends the instruction for operation and
the IOP execute it.
 Graphics Processors
 The graphic processor or Graphics Processing Unit (GPU) is a special type of processor
specifically designed to accelerate the process of creation of images.
 The graphic processor executes the instructions in parallel which is the reason it is faster
than the CPU.
 They are mostly used for rendering images in CGI (computer-generated imagery) or in video
games.
 They are used in display devices such as smartphones, computers, gaming consoles, etc.
 The GPU contains a graphic processor with other essential components like ram and cooling
components.
 Eg. NVidia Corporation and ATI technologies are some of the companies that develop GPU
for gaming, 3d animation and rendering, video editing, and CGI, etc.
Special Purpose Microprocessor:………
 Bit-Slice Microprocessors (BSM)
 Bit-Slice Microprocessor or BSM is a special type of microprocessor whose main purpose is to
form a microprocessor of desired word size by combining identical BSMs.
 It is available in 2-bit, 4-bit, 8-bit, 16-bit and 32-bit word size.
 Bit-Slicing means that the microprocessor is made from modules of identical microprocessors
with a smaller bit size. Its main purpose is to increase the bit size of a microprocessor to our
desired width.
 Scalar and Superscalar Microprocessors
 The scalar microprocessor can process one set of data at a time. It can execute only one
instruction in a single clock cycle.
 The Superscalar microprocessor is a type of microprocessor that can execute more than one
instruction or task at a single time.
 It has multiple execution units that are used to process multiple instructions in parallel.
 These execution units are not processors but they are various ALUs inside the superscalar
microprocessor.
 Symbolic Processors
 Symbolic processors are designed for expert system, machine intelligence, knowledge based
system, pattern-recognition, text retrieval, etc.
 The basic operations which are performed for artificial intelligence are:
 Logic interference, compare, search, pattern matching, filtering, unification, retrieval, reasoning, etc.
 This type of processing does not require floating point operations. Symbolic processors are also
called LISP processors or PROLOG processors.
Microprocessor instruction set and Computer Language
– Microprocessor recognize and operate in binary numbers(binary words
meaning and language).
• As we explain early, word length(byte) is defined as the number of bits the
microprocessor recognize and processes at a time. It range from
(nibbles)4bits -64bits for super computer.
– Each machine has its own set of instruction based on the design of its CPU or
of its microprocessor.
– To communicate with computer, one much give instruction in binary language
(machine language).
– Because it is difficult for most people to write program is set bits, then
computer manufactures have devised “English-like” words to represent the
binary instructions of the machine.
– Now, the programmers can write programs called “assembly language
programs” using those words, assembly language is specific to a given
machine and are not transferable from one to another machine.
– To circumvent this limitation, such general purpose language as BASIC an
FORTAN have been devised; a program written in these language can be
machine –independent(high level language)
• Machine Language
– The number of bit in a word for a given machine is fixed, and these words are
formed through various combinations of these bits.
– (8 bit word length =8bit microprocessor =256 combination of eight
bits=language of 256 words)
– Designer engineer selects combinations of bit patterns and gives a specific
meaning to each combination by using electronic logic circuits(instruction).
– Instruction are made up of one word or several words.
– The set of instructions designed into machine makes up its machine language.
We are concerned with the language of widely used 8-bit

microprocessor,8085,manufactured by Intel corp.
• 8085 machine language
– The 8085 is a microprocessor with 8 bit word length; its instructions set(or language)
is designed by using various combinations of these eight bits.
– An instruction is a binary pattern entered through an input device in memory to
command the microprocessor to perform that specific function.
– For example: 0011 1100 { is an instruction that increments the number in the register
called the accumulator by one}
1000 0000 {is an instruction that adds the in register called B to the
number in the accumulator and keeps the sum in accumulator }
– The 8085 microprocessor has 246 such bit patterns, amounting to 74 different
instructions for performing various operations.
– These 74 different instructions are called its instruction set.
– These binary language with a predetermined instruction set is called the 8085
machine language.
– So because its tedious and error inductive for the people to recognize and write
instructions in binary language, these instructions are for convenience written in
hexadecimal code and entered is a single board microcomputer by using hex keys.
– For example the binary instruction 0011 1100 is equivalent to 3C in hexadecimal,
these instruction can be entered in single board microprocessor system with a hex key
board by simply pressing two keys: 3 and C then the monitor program of the system
translates these keys into their equivalent binary pattern.
8085 assembly language
– Even though the instruction can be written in hexadecimal code, sometimes is still
difficult to understand a program written in it.
– Therefore, each manufacturer of a microprocessor have devised a symbolic code for
each instruction called mnemonic(greek-means mindful).
– The mnemonic for a particular instructions consists of letters that suggest the
operation to be performed by that instructions.
– For example: 3C hex of 8085 microprocessor is represented by mnemonic INR A.
80 hex of 8085 microprocessor is represented by mnemonic ADD B.
– Although these symbols do not specify the complete operations, they suggest a
significant part.
– The complete description of each instruction must be supplied by the manufacturer.
The complete set of 8085 mnemonic is called assembly language.
– A program written in these mnemonic is called assembly language program.
– Again, the assembly language, or mnemonics, is specific to each microprocessor.
– An assembly language program written for one microprocessor is not
transferable to a computer with another microprocessor unless the two
microprocessors are compatible in their machine codes.
8085 assembly language…
– Machine language and Assembly language are microprocessor specific and are both
considered low level languages.
– As we see; machine language is binary and assembly language is in English like
words.
– The mnemonic can be written by hand on paper and translated manually in
hexadecimal code, called hand assembly.
– Also the mnemonic can be written electronically on a computer using a program
called an Editor in the ASCII code.
American Standard Code for Information Interchange
– A computer is binary machine; to communicate with the computer in alphabetic letters
and decimal numbers, translation codes are necessary.
– The commonly use code is known as ASCII.
– Its is 7 bit code, with 128 combinations, and each combinations from 00H to 7FH is
assigned to either a letter, a decimal number, a symbol, or a machine command.
– Example hexadecimal 30H to 39H represents 0 to 9 decimal digits,41H to 5AH represent
capital letters A to Z,20H to 2FH represent various symbols, and initial codes 00H to 1FH
represents such machine command as carriage return and line feed.
– Example of devices use ASCII code are; keyboards,printers,video screens.
– So when the key “9” is pressed on an ASCII key board, the computer receives 39H in
binary, called the ASCII character and the system program translates these character into
appropriate binary numbers.
– However, recent computer use many more characters than the original 128
combinations; this is called extended ASCII {it is an 8 bit code provides 256 combinations,
the additional 128 combinations are assigned to cover various graphics characters).
NOTE:
Assembler is a program that translates the mnemonics entered by the ASCII keyboard into the corresponding binary
machine codes of the microprocessor, each microprocessor has its own assembler due to the fact machine code ins not
transferable.
Differences between 8085 and 8086 Microprocessor
8085 Microprocessor 8086 Microprocessor
It is an 8-bit microprocessor. It is a 16-bit microprocessor.
It has an 8-bit wide data bus. It has 16-bit wide data bus.
It can address 28 = 256 I/O ports. It can address 216 = 65,536 I/O ports.
It has 16-bit wide address bus. It has 20-bit wide address bus.
It has an 8-bit ALU (Arithmetic Logic Unit). It has a 16-bit ALU.
It can process an 8-bit of data in one It can process 16-bit of data in one
machine cycle. machine cycle
The maximum accessible memory (RAM) The maximum accessible memory of 8086
it can access is 216 = 64KB is 220 = 1MB.
It has an on-chip oscillator of 3 MHz It is available in 3 versions with a clock
frequency of 5 MHz, 8 MHz and 10 MHz.
APPLICATION
Microprocessor application are classified primarily in two categories;
• Reprogrammable
• Embedded system
• In reprogrammable systems such as microcomputer ,microprocessor is used for
computing and data processing.
– These system include general purpose microprocessor capable of handling
large data ,mass storage devices(disks,cd-rom) and peripherals such as
printers.
– Personal computer is a typical illustration of reprogrammable systems.
• In embedded systems, the microprocessor is a part of a final product and it is not
available for reprogramming to the end user.
– Copy machine is a typical illustration of embedded system .
– Embedded system s can also be viewed as a products that uses
microprocessor to perform their operations(microprocessor based products)
APPLICATION
• Examples of Embedded system include a wide range of product such as:
» Washing machine
» Dish washers
» Automatic testing instruments
» Automatic dashboard control
» Traffic lights controllers
8085 MICROPROCESSOR ARCHITECTURE
Internal Architecture
8085 MICROPROCESSOR ARCHITECTURE..
• The 8085 microprocessor is an 8-bit processor available as a 40-pin IC package and
uses +5 V for power.
• It can run at a maximum frequency of 3 MHz
• Its data bus width is 8-bit and address bus width is 16-bit, thus it can address 2
power(16) = 64 KB of memory.
Registers:
• Registers in 8085 microprocessor can be classified into two category:
1. Special Purpose Registers
• These registers are used to store or copy temporary data, by using instructions,
during the execution of the program.
• Example of these registers are:
 Accumulator.
 Flag registers.
 Memory Registers like; PC and SP
2. General Purpose Registers
• The 8085 has six general-purpose registers to store 8-bit data; these are identified
as- B, C, D, E, H, and L.
• These can be combined as register pairs – BC, DE, and HL, to perform some 16-bit
operation.
• These registers are used to store or copy temporary data, by using instructions,
during the execution of the program.
Accumulator
• The accumulator is an 8-bit register that is a part of ALU.
• This register is used to store 8-bit data and to perform arithmetic and logical operations.
• The result of an operation is stored in the accumulator.
• The accumulator is also identified as register A.
Flag register
• The ALU includes five flip-flops, which are set or reset after an operation according to data condition
of the result in the accumulator and other registers.
• They are called Zero (Z), Carry (CY), Sign (S), Parity (P) and Auxiliary Carry (AC) flags.
• Their bit positions in the flag register are shown in Fig below.
• The microprocessor uses these flags to test data conditions.

• These flags have critical importance in the decision-making process of the microprocessor
• The conditions (set or reset) of the flags are tested through the software instructions
• The thorough understanding of flag is essential in writing assembly language programs
• The combination of the flag register and the accumulator is called Program Status Word (PSW) and
PSW is the 16-bit unit for stack operation.
Flag register…..
• If the sum in the accumulator is larger than eight bits, the flip-flop uses to indicate a carry -- called the
Carry flag (CY) – is set to one
• When an arithmetic operation results in zero, the flip-flop called the Zero (Z) flag is set to one.
1. Sign Flag
• Used for indicating the sign of the data in the accumulator.
• The sign flag is set if negative (1 –negative)
• The sign flag is reset if positive (0 –positive)
2. Zero Flag
• Is set if result obtained after an operation is 0.
• Is set following an increment or decrement operation of that register.
Eg: 10110011
+ 01001101
---------------
1 00000000
3. Carry Flag
• Is set if there is a carry or borrow from arithmetic operation.
Flag register…..
4. Parity Flag
– Indicates if the number of set bits is odd or even in the binary representation of the result of
the last operation.
– Is set if parity is even.
– Is cleared if parity is odd.
5. Auxiliary Carry Flag
• Is set if there is a carry out of bit 3.
Memory Registers
• There are two 16-bit registers used to hold memory addresses. The size of these registers is 16 bits
because the memory addresses are 16 bits.
• They are :-
 Program Counter:
 This register is used to sequence the execution of the instructions.
 The function of the program counter is to point to the memory address from which the
next byte is to be fetched.
 This register always holds the address of the next instruction to be fetched and
executed.
 When a byte (machine code) is being fetched, the program counter is incremented by
one to point to the next memory location..
 Also act as a memory pointer.
 Since it holds an address, it must be 16 bits wide.
 Stack Pointer:
 It is used as a memory pointer.
 It points to a memory location in read/write memory, called the stack.
 It is always incremented/decremented by 2 during push and pop operation.
 Points to a memory location in R/W memory, called the stack .
 The stack is an area of memory used to hold data that will be retrieved soon.
 The stack is usually accessed in a Last In First Out (LIFO) fashion.
 The stack pointer is also a 16-bit register that is used to point into memory.
Instruction Register/Decoder
• The instruction register and the decoder are considered as a part of the ALU
• The instruction register is a temporary storage for the current instruction of a program
• It is an 8-bit register. When an instruction is fetched from memory then it is stored in the Instruction
register.
• The decoder decodes the instruction and establishes the sequence of events to follow
Timing and control unit
– It provides timing and control signal to the microprocessor to perform the various operations.
– It controls all external and internal circuits. It operates with reference to clock signal.
– It synchronizes all the data transfers.
– Following are the timing and control signals, which control external and internal circuits.
• Control Signals: READY, RD’, WR’, ALE
• Status Signals: S0, S1, IO/M’
• DMA Signals: HOLD, HLDA
• RESET Signals: RESET IN, RESET OUT
 ALE (output)
 It is an address latch enable signal. It goes high during first clock cycle of a machine cycle and enables
the lower 8 bits of the address to be latched either into the memory or external latch.
 IO/m(output)
 It is a status signal which distinguishes whether the address is for memory or I/O. when it goes high
the address on the address bus is for an I/O device.
 When it goes low the address on the address bus is for a memory location.
 S0, S1 (output)
These are status signal sent by the microprocessor to distinguish the various types of operation. Status
code for Intel 8085.
8085 Machine Cycle Status and Control Signals
Timing and control unit…..
 RD (bar)(output)
 It is a signal to control READ operation
 When it goes low the selected memory or I/O device is read.
 WR(bar)(output)-
 It is a signal to control WRITE operation
 When it goes low the data on the data bus is written into the selected memory or I/O operation.
 READY(input)
 it is used by the microprocessor to sense whether a peripheral is ready to transfer data or not.
 A slow peripheral may be connected to the microprocessor through READY line.
 if READY is high the peripheral is ready .if it is low the microprocessor waits till it goes high.
 HOLD (input)
 it indicates that another device is requesting for the use of the address and data bus. Having received a
HOLD request the microprocessor relinquishes the use of the buses as soon as the current machine cycle
is completed. Internal processing may continue. the processor regains the bus after the removal of the
HOLD signal. when a HOLD is acknowledged .
 HLDA (output)
 it is a signal for HOLD acknowledgement. It indicates that the HOLD request has been received. after the
removal of a HOLD request the HLDA goes low. the CPU takes over the buses half clock cycle after the
HLDA goes low.
 RESET IN(bar) (input)
 It resets the program counter to zero .it also resets interrupts enable that is an HLDA flip-flops.
 RESETOUT (output)
 it indicates that the CPU is being reset.
MICROPROCESSOR ARCHITECTURE AND ITS OPERATION
• The process of data manipulation and communication is determined by
determined by the logic design of the microprocessor, called the architecture.
• All the various functions performed by the microprocessor can be classified in
three general categories;
 Microprocessor initiated operations.
 Internal operations.
 Peripheral (externally) operations.
• Microprocessor performs primary four operations;
 Memory read.
 Memory write.
 I/O read.
 I/O write.
• All these operations are part of the communications process between the MPU
and peripherals devices(include memory).
• To communicate with a peripheral(or memory location),the MPU needs to perform
the following steps;
 Identify the peripheral or the memory location(with its address).
 Transfer binary information(data and instructions).
 Provide timing or synchronization signals.
MICROPROCESSOR ARCHITECTURE…
• All the signals can be classified into six groups
 Address bus signals
 Data bus signals
 Control and status signals.
 Power supply and frequency signals
 Externally initiated signals
 Serial I/O port signals
MICROPROCESSOR ARCHITECTURE AND ITS OPERATION…
• The microprocessor performs these steps using three sets of communication lines
called system buses; the address bus, the data bus and control bus.
MICROPROCESSOR ARCHITECTURE AND ITS OPERATION…
ADDRESS BUS.
• Address bus is a group of 16 lines generally identified as A0 to A15.
• The address bus is unidirectional; bits flow in one direction-from the MPU to
peripheral devices.
• MPU uses the address bus to perform the first function; identifying a
peripheral or a memory location.
• Each peripheral/memory location is identified by a binary number called the
address, address bus is used to carry a 16 bit address.
• The number of address lines of the MPU determines its capacity to identify
different memory location(or peripherals).
• The MPU with its 16 address lines is capable of addressing 65,536(64k)
memory locations.
• Most 8-bit microprocessor have 16 address lines, this means 8 bit
microprocessor have 64k memory(location),however not every MPU has 64K
memory.
• Even if the MPU is capable of addressing 64k memory, the number of address
lines is arbitrary.( pins and application of the processor).
Microprocessor…
• Microprocessor Architecture And Its Operations…..
DATA BUS.
• Data bus is a group of eight lines used for data flow.
• The lines are bidirectional, data flows in both directions between the MPU and
Memory/peripheral devices.
• The MPU uses the data bus to transfer binary information.
• The 8 data lines enable MPU to manipulate 8-bit data, ranging from 00-FF
CONTROL BUS.
• The control bus is comprised of various single lines that carry synchronous signals.
• The MPU uses such line to perform the third function: providing timing signals.
• There are not groups of lines like address or data buses, but individuals lines that provide a
pulse to indicate an MPU operation.
• The MPU generates specific control signals for every operation it perform(such as memory read
or read I/O write).
• These signals are used to identify a device type with which the MPU intends to communicate.
{for example; to read an instruction from a memory location-the MPU places the 16-bit
address on the address bus, the address on the bus is decoded by an external logic circuits
and the memory location is identified. The MPU sends a pulse called Memory read as the
control signals. The pulse activates the memory chip, and the contents of the memory
location(8 bit data) are placed on the data bus and brought insides the microprocessor.}
Read memory Operation
A0-A15 16-bit Address Address bus
Instruction
Memory decode
and
data
MPU Memory chip
D0-D7 Data bus Data
Memory read pulse (MEMR)

Read memory Operation..
Internal Architecture of Microprocessor(8085)
Internal Architecture of Microprocessor(8085)
(PINS)
Demultiplexing AD7-AD0
As we previously see:
• The address bus has 8 signal lines A8 –A15 which are unidirectional and used as
the order address lines.
• The other 8 address bits are multiplexed(time shared) with the 8 data bits.
– So, the bits AD0 –AD7are bi-directional and serve as A0 –A7and D0 –D7at the
same time.
• In executing an instruction, during the an earlier part of the cycle, used as low
order address bus and during the later part of the cycle; these lines are used as
data bus(multiplexing the bus).
• In order to separate the address from the data, we can use a latch to save the
value before the function of the bits changes.
• It becomes obvious that the AD7–AD0l ines are serving a dual purpose and that
they need to be demultiplexed to get all the information.
• The high order bits of the address remain on the bus for three clock periods.
• However, the low order bits remain for only one clock period and they would be
lost if they are not saved externally. Also, notice that the low order bits of the
address disappear when they are needed most.
• To make sure we have the entire address for the full three clock cycles, we will use
an external latch to save the value of AD7–AD0 when it is carrying the address bits.
We use the ALE signal to enable this latch. Given that ALE operates as a pulse
during T1, we will be able to latch the address.
• Then when ALE goes low, the address is saved and the AD7–AD0 lines can be used
for their purpose as the bi-directional data lines.
• The high order address is placed on the address bus and hold for 3 clock periods.
• The low order address is lost after the first clock period, this address needs to be
hold however we need to use latch.
• The address AD7 –AD0 is connected as inputs to the latch 74LS373.
• The ALE signal is connected to the enable (G) pin of the latch and the OC –Output
control –of the latch is grounded.
74LS373 in Action
Overall Demultiplexing of AD7-AD0
• In a single picture
Generating Control signals
Schematic to generate read/write
Control signals for memory and I/O
Demultiplexed address and data bus

With control signal
Microprocessor: Communication and Bus Timings
• To understand the functions of various signals of the 8085,we should examine the
process communication (read from and writing into memory) between the
microprocessor and memory and the timings of these signals in relation to the
system clock.
• The first step in the communication process is reading from memory or fetching an
instruction(opcode fetch).
• Now, lets us examine the example of how the microprocessor fetches or get a
machine code from memory
Figure: Illustrate the steps and the timing of data flow

when the instruction code 0100 1111(4FH-MOV C,A),
stored in location 2005H,is fetched
(data flow from memory to the MPU)
To fetch the byte(4FH),the MPU needs to

identify the memory location 2005H and
enable the data flow from memory. This is
called the Fetch Cycle.
Microprocessor: Communication and Bus Timings…
T1
• The high-order memory address 20H is placed
on the address lines.
• The low order memory address 05H is placed
on the bus AD7-AD0 and the ALE goes high.
• Similarly, the status signal IO/m goes low,
indicating that this is memory related
operation.
T2
• Control unit send the RD to enable the
memory chip during two clock periods.
• When the chip is enabled; the instruction
byte(4FH0 is placed on the bus AD7-AD0 and
when RD goes high, it cause the bus to go high
impedance.
T4
• Machine code is decoded by the instruction
decoder and the contents of the accumulator
are copied into register C.
INTERRUPTS IN 8085 MICROPROCESSOR
• When microprocessor receives any interrupt signal from peripheral(s) which are requesting
its services, it stops its current execution and program control is transferred to a sub-routine
by generating CALL signal and after executing sub-routine by generating RET signal again
program control is transferred to main program from where it had stopped.
• When microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the
peripheral which is requesting for its service.
• Interrupts can be classified into various categories based on different parameters:
I. Hardware and Software Interrupts
II. Vectored and Non-Vectored Interrupts
III. Maskable and Non-Maskable Interrupts
Hardware Interrupts
 When microprocessors receive interrupt signals through pins (hardware) of
microprocessor, they are known as Hardware Interrupts.
 There are 5 Hardware Interrupts in 8085 microprocessor.
 They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
Software Interrupts
 Software Interrupts are those which are inserted in between the program which
means these are mnemonics of microprocessor.
 There are 8 software interrupts in 8085 microprocessor.
 They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.
Vectored and Non-Vectored Interrupts
 Vectored Interrupts are those which have fixed vector address (starting address of
sub-routine) and after executing these, program control is transferred to that
address.
 Vector Addresses are calculated by the formula 8 * TYPE.
INTERRUPT VECTOR ADDRESS
TRAP (RST 4.5) 24 H
RST 5.5 2C H
RST 6.5 34 H
RST 7.5 3C H
Vectored Interrupts
 Vectored Interrupts are those which have fixed vector address (starting address of
sub-routine) and after executing these, program control is transferred to that
address.
 Vector Addresses are calculated by the formula 8 * TYPE.
TRAP (RST 4.5) 24 H
RST 5.5 2C H
RST 6.5 34 H
RST 7.5 3C H
Vectored Interrupts ……
 For Software interrupts vector addresses are given by:
RST 0 00 H
RST 1 08 H
RST 2 10 H
RST 3 18 H
RST 4 20 H
RST 5 28 H
RST 6 30 H
RST 7 38 H
Non-Vectored Interrupts
• Non-Vectored Interrupts are those in which vector address is not predefined.
• The interrupting device gives the address of sub-routine for these interrupts.
• INTR is the only non-vectored interrupt in 8085 microprocessor.
Maskable Interrupts
• Maskable Interrupts are those which can be disabled or ignored by the
microprocessor.
• These interrupts are either edge-triggered or level-triggered, so they can be
disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085
microprocessor.
Non-Maskable Interrupts
• Non-Maskable Interrupts are those which cannot be disabled or ignored by
microprocessor.
• TRAP is a non-maskable interrupt.
• It consists of both level as well as edge triggering and is used in critical power
failure conditions.
Priority of Interrupts
• When microprocessor receives multiple interrupt requests simultaneously, it will
execute the interrupt service request (ISR) according to the priority of the
interrupts
Instruction for Interrupts
1. Enable Interrupt (EI)
The interrupt enable flip-flop is set and all interrupts are enabled following the
execution of next instruction followed by EI. No flags are affected. After a system reset,
the interrupt enable flip-flop is reset, thus disabling the interrupts. This instruction is
necessary to enable the interrupts again (except TRAP).
2. Disable Interrupt (DI)
This instruction is used to reset the value of enable flip-flop hence disabling all the
interrupts. No flags are affected by this instruction.
3. Set Interrupt Mask (SIM)
It is used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by setting
various bits to form masks or generate output data via the Serial Output Data (SOD)
line. First the required value is loaded in accumulator then SIM will take the bit pattern
from it.
4. Read Interrupt Mask (RIM)
This instruction is used to read the status of the hardware interrupts (RST 7.5, RST 6.5,
RST 5.5) by loading into the A register a byte which defines the condition of the mask
bits for the interrupts. It also reads the condition of SID (Serial Input Data) bit on the
microprocessor.
MEMORIES OF MICROPROCESSOR SYSTEM
Flip Flop/Latch
• Generally, memory is circuit that can store bits.
• Flip flop or latch is a basic element of memory for storing information.
• One latch or flip-flop can store one bit of information.
• The main difference between latches and flip-flops is that for latches, their outputs
are constantly affected by their inputs as long as the enable signal is asserted. In other
words, when they are enabled, their content changes immediately when their inputs
change.
• Flip-flops, on the other hand, have their content change only either at the rising or
falling edge of the enable signal.
• This enable signal is usually the controlling clock signal.
• After the rising or falling edge of the clock, the flip-flop content remains constant
even if the input changes.
• There are basically four main types of latches and flip-flops: SR, D, JK, and T.
• The major differences in these flip-flop types are the number of inputs they have and
how they change state.
• The simplest sequential circuit or storage element is a bistable element, which is
constructed with two inverters connected sequentially in a loop.
• To avoid unintentional change in the input and control the availability of the out, we
use tri-state (active low level) buffers on the latch.
Latch/flip flop
• Latch which can store one binary is called a memory cell.
Din D
Q Dout
Enable EN
• Tri-state buffer
Din D out Din Dout
Control//high Control//active low

• Latch with tri-state buffer(active low)
Flip Flop/Latch (4-bit latch)
LATCHES WITH DIFFERENT MEMORY CELL IN SINGLE CHIP
• Example four register with eight cells(4*8-bit) are arranged in sequence.
• To write or to read from any one of the registers, a specific register should be
identified or enabled(we replace EN signal with decoders).
• This is a simple decoding function; a 2 to 4 decoder can perform that function,
however we need two more input lines called address lines(A0-A1) is needed to
the decoder.
• These two input lines can have four different bit combinations.(00,01,10,11) and
each combination can identify or enable one of the register, named register 0
through register 3.
REGISTER WITH DIFFERENT MEMORY CELL IN DIFFERENT CHIP
• An interested part is how we deal with more than one chip; for example, two chips
with four registers each.
• We can have a total of eight registers; three address lines, but one line should be
used to select between the two chips(Chip select signal )
• A2(with inverter) and Chip select is used to select between these two chips.
• When A2 is low (0),chip M1 is selected and when M2 is high(1),chip M2 is selected.
• The address on A0 and A1 will determine the registers to be selected: thus by
combining the logic on,A0,A1,A2 the memory address range from 000 to 111.
• The concepts of the chip select signal gives us a more flexibility in designing chips
and allows us to expand memory size by using multiple chips.
REGISTER WITH DIFFERENT MEMORY CELL IN DIFFERENT CHIP….
REGISTER WITH DIFFERENT MEMORY CELL IN DIFFERENT CHIP….
• Now let us examine the problem from a different perspective, assume we have
available four address lines and memory chips with four registers.
• Four address lines are capable of identifying 16 registers; however we need only
three address lines to identify eight registers. What should we do with the fourth
line?
• Memory chip M1 is selected when A3 and A2 are both 0,therefore register in these
chip are identified with the address ranging from 0000 to 0011(0-3).
• Memory of chip M2 will range from 1000 to 1011 (8 to B);this chip is selected only
when A3 is 0 and A2 is 0.
Memory Mapping and Addresses
• Memory mapping is a pictorial representation in which memory devices are
located in the entire range of addresses.
• Memory addresses; provide the locations of various memory devices in the system
and interfacing logic defines the range of memory for each memory device.
• 16 address line are available for memory.
• This means it is a numbering system of 6 binary bits and is capable of identifying
65,536 memory registers, each register with a 16-bit address.
• The entire memory address can range from 0000-FFFF in Hexadecimal.
• Let assume that we have a memory chip with 256 registers, we need only 256
number out of 65,536 that require eight address line(8-bit).
• We can use other remaining 8 address lines to assign fixed logic to generate a
fixed number using for chip select through appropriate logic gate.
Memory Mapping and Addresses….
• Previously, we define 1024 as 1k,therefore a 1K-byte memory chip has 1024
register with 8 bit each.
• A group of 256 register is defined as one page and each register is viewed as line to
write on.
• So we can view 1k-byte memory as a chip with four pages(1024/256=4) with each
page have 256 registers each with 8 bit.
• In two hex digit,256 registers can numbered from 00H-FFH,and for 1024 register
can numbered from 00H-03FFH.
• If we examine the high-order digits, we can find that they range from 00-03
representing five pages(00,01,02,03).
• Memory map is used generally for the entire address range of a memory chips in a
given system.
• Illustrating the memory address range of the chip with 256 registers each with
eight bit//(256*8)memory.
eight bit//(256*8)memory………..
– It has eight address line from A0-A7 of the microprocessor which
required to identify 256 memory registers.
– The address line A0-A7 can assume any combination from 00H-FFH and
identify any of 256 register through the decoder.
– The remaining lines A8-A15 are connected to the chip select/chip enable
line through inverters and the NAND gate.
– The memory chip is selected or enable when chip select goes low,
therefore to select the chip the address line A8-A15 should be at logic
0,which will cause the output of NAND to go low.
– Since we have 16 address lines, the address range of the selected chip
will range from 0000H-00FFH.
– The address lines A15-A8 which are used to select the chip, must have
fixed levels, these lines are called High order address lines.
– The address lines A7-A0,they can be assigned logic levels from all 0s to
1s and any in between combination.
eight bit//(256*8)memory………..
– For example when low order address lines are all
0s;the register 0 is selected, and when they are all
1s,the register 255(FFH) is selected.
• Illustrating; memory address range can be assigned in various locations over the entire address of memory
map(0000H-FFFFH).
– It means address range of a given chip can be changed by
modifying the hardware of Chip select/chip enable.
– The chip select addresses are determined by the
hardware(inverters and NAND gate).
– For example; if the inverter on line A15 is moved, the address
required on A15-A8 to enable the chip will be as follows:
………………………..?????
– The memory address range will be ………?????
Note
– Both chip have 256*8 register.
– By modify the Chip select hardware, the location
of chip in the map is change, hence the chip addr.
• As we previously see, if the chip include 256 register; the high order address lines
(A15-A8)and low order address lines(A7-A0) were equally divided.
• So what if the chip include more than 256 register!!!! 512,1k-btye,2k-
byte……….;what might be their high order address lines and low order address
lines.
Memory address lines

• The number of address lines necessary for given chip can be obtained from data
sheet.
• However we need to know the relationship between the number of registers and
number of address lines.
• For example; the chip with 256*8 registers, we need 256 binary number to
identify each register.
• Each address line can assume only two logic(0,1),therefore we need to find power
of two(2),that will give us 256 combinations.
• The problem can be restated as follows; Find x where 2 power (x)=256,apply log
both sides….hence x is number of address line for given chip
• Find the address line for the following chips (256 reg,512*8-bit,1k-byte etc)
Machine cycle and Bus timing
• 8085 microprocessor is designed to execute 74 different instruction types.
• Each instruction has two parts;-
1. Opcode(operation code)-is a command/action to be performed(eg;add,mov,sub
ect) //knowing the bit for this command
2. Operand-is an object to be operated on(such as byte(constant) or content of
register.
• Some are one byte instructions and some are multi-byte instructions.
 Eg MOV A,C is one byte instruction.(How??),
 LDA addr is three byte instruction,
 MVI A,data (8bit data)-two byte instruction
• All instructions are divided into few basic Machine cycle and these cycles are divided
into precise system clock periods(T)
• To know the details of these machine cycles we will focus on three operation
performed by microprocessor;-
1. Opcode fetch machine cycle
2. Memory write machine cycle
3. Memory read machine cycle
Opcode fetch machine cycle
• The first operation in any instruction is an opcode fetch.
• Microprocessor needs to get/fetch these machine code from the memory register
before microprocessor can begin to execute the instruction.
• To differentiate an opcode from data byte or an address,this opcode fetch machine
cycle is identified by status signals-(011)
• Opcode fetch machine cycle has 4-clock periods.(4T-states).
• T1-T3 to fetch the opcode and T4-for instruction decoder to decode the byte.
• Opcode fetch machine cycle is also called M1.
Memory read machine cycle
• May be referred as M2.
• It has 3T-states.
• As we discuss, the first byte of any instruction is for opcode fetch, so will examine
memory read machine cycle by examine the execution of 2-byte instruction,3-byte
instruction and so on.
• Example.
1. Two machine codes(3EH) and 32H-are stored in memory locations 2000H and
2001H respectively.
-The first machine code (3EH) represents the opcode to load a data byte in the
accumulator.//see mnemonic code.
Memory location Machine code
Instruction
2000H 3EH
MVI A,32H;load byte/constant into accumulator
2001H 32H
 This instruction consists of two bytes; first is the opcode and the second is the
data byte.
 8085 needs to read these bytes first from memory and thus requires at least two
machine cycles(opcode fetch and second memory read machine cycle).
 This kind of instruction requires seven T-states for these two machine cycles.
8085 TIMING FOR THE EXECUTION OF THE INSTRUCTION; MVI A,32H
 The first machine cycle cycle(opcode fetch) is identical in bus timing with status
signal-011
 After completion of the M1,the 8085 place the address 2001H on the address
bus and increment PC by 1,to memory location 2002H.
– The M2 is identified by status signal-010
– ALE goes low after clock period one(T1) of M1 and M2 (WHY??)
– T2 of both cycle,read signal(active low) become active and enable the
chip/memory.
 At rising edge of T2,8085 activate the data bus as an input bus, memory place
the data byte 32H on the data bus, and reads and stores byte in the
accumulator during T3.
M1
T1:
• microprocessor identifies that is an M1 by
placing 011 status signal.
• It place 2000H memory address from PC on
address bus.20H ,high order memory address
on lines(A15-A8) and 00H into multiplexed
bus-low order memory address lines(A7-A0)-
refer latch, and the PC increment the memory
address by 1.
T2:
• Read signal(active low) is enabled to enable
the chip, and memory place the 32H data byte
on the data bus from memory location 2000H.
• 8085 places the opcode on instruction
decoder/register and disable the read signal
at rising edge of T3.
• So the fetch is completed at T3.
T4:decode the opcode to see its command
M2
T1:
• Place what in data bus?? ,which address is for
high/low order memory lines?
• Status signal for this cycles? why?
• Status of PC after operation?
T2:
• RD(active low) become active and enable the chip.
• At rising edge of T2,the 8085 activates the data bus
an input bus, memory place the data byte 32H on
the data bus
T3:
• 8085 reads and stores the bytes in the accumulator.
Execution time for machine Cycles
• Given
 Clock frequency (f)=2MHZ note; //diff processor have different clock speed
 T-states/clock period=1/f T-state=??
MVI A, 32H
//5687H (try this)
 Execution time for Opcode fetch;????

• needs 4 clock period (4T),where T-state is (1/f)
 Execution time for Memory read;????

• Need 3 clock period (3T),
 Execution time Instruction

• Need 7 clock period(7T)
Execution time for machine Cycles
Example;
1. Explain number of bytes, machine cycle,T-states of the below instruction;-
STA 2065H ,the machine code are stored in memory locations 2010H,2011H and 2012H
Memory addr Machine code

2010 32H opcode Instruction Mean;
2011 65H Low-order addr write the content of Acc
2012 20H High-order into given memory addr.
addr.
See your Instruction set for that instruction; STA,addr

Note:
The 16-bit of operand must be entered in reverse order.
8086 MICROPROCESSOR ARCHITECTURE
• TO BE PREPAIRED
8085 MICROPROCESSOR INSTRUCTION
INSTRUCTION SET CLASSIFICATION
• An instruction is a binary pattern designed inside a microprocessor to
perform a specific function.
• The entire group of instructions, called the instruction set,determines
what functions the microprocessor can perform.
• These instructions can be classified into the following five functional
categories:
a) data transfer (copy)operations
b) arithmetic operations
c) logical operations
d) branching operations
e) machine-control operations.
DATA TRANSFER (COPY)OPERATIONS
• This group of instructions copy data from a location called a source to
another location called a destination, without modifying the contents of
the source.
• In technical manuals, the term data transfer is used for this copying
function.
• However, the term transfer is misleading; it creates the impression that
the contents of the source are destroyed when, in fact, the contents are
retained without any modification.
• The various types of data transfer (copy) are listed below together with
examples of each type:
ARITHMETIC OPERATIONS.
These instructions perform arithmetic operations such as addition, subtraction,increment,
and decrement.
Addition
– Any 8-bit number, or the contents of a register or the contents of a memory location can be added to the
contents of the accumulator and the sum is stored in the accumulator.
– No two other 8-bit registers can be added directly (e.g., the contents of register B cannot be added directly
to the contents of the register C).
– The instruction DAD is an exception; it adds 16-bit data directly in register pairs.
Subtraction
– Any 8-bit number, or the contents of a register, or the contents of a memory location can be subtracted from
the contents of the accumulator and the results stored in the accumulator.
– The subtraction is performed in 2's compliment, and the results if negative, are expressed in 2's complement.
– No two other registers can be subtracted directly.
Increment/Decrement
– The 8-bit contents of a register or a memory location can be incremented or decrement by 1. Similarly, the
16-bit contents of a register pair (such as BC) can be incremented or decrement by 1.
– These increment and decrement operations differ from addition and subtraction in an important way; i.e.,
they can be performed in any one of the registers or in a memory location.
LOGICAL OPERATIONS
These instructions perform various logical operations with the
contents of the accumulator.
AND, OR Exclusive-OR
– Any 8-bit number, or the contents of a register, or of a memory location can be
logically ANDed, Ored, or Exclusive-ORed with the contents of the
accumulator.
– The results are stored in the accumulator.
Rotate
Each bit in the accumulator can be shifted either left or right to the next position.
Compare
Any 8-bit number, or the contents of a register, or a memory location can be
compared for equality, greater than, or less than, with the contents of the
accumulator.
Complement
– The contents of the accumulator can be complemented.
– All 0s are replaced by 1s and all 1s are replaced by 0s.
BRANCHING OPERATIONS.
This group of instructions alters the sequence of program execution either
conditionally or unconditionally.
Jump
• Conditional jumps are an important aspect of the decision-making
process in the programming.
• These instructions test for a certain conditions (e.g., Zero or Carry flag)
and alter the program sequence when the condition is met.
• In addition, the instruction set includes an instruction called
unconditional jump.
Call, Return, and Restart
• These instructions change the sequence of a program either by calling a
subroutine or returning from a subroutine. The conditional Call and
Return instructions also can test condition flags.
MACHINE-CONTROL OPERATIONS.
These instructions control machine functions such as Halt, Interrupt, or
do nothing.
Some of Instruction and their descriptions
Data Transfer Instructions
Opcode Operand Description
MOV Rd, Rs Copy from source to destination.
M, Rs
Rd, M
 This instruction copies the contents of the source register into the destination
register.
 The contents of the source register are not altered.
 If one of the operands is a memory location, its location is specified by the contents
of the HL registers.
 Example: MOV B, C or MOV B, M

MVI Rd, Data Move immediate 8-bit
M, Data
 The 8-bit data is stored in the destination register or memory.
 If the operand is a memory location, its location is specified by the contents of

the H-L registers.
 Example: MVI B, 57H or MVI M, 57H

LDA 16-bit address Load Accumulator
 The contents of a memory location, specified by a 16-bit address in the

operand, are copied to the accumulator.
 The contents of the source are not altered.
 Example: LDA 2034H

LDAX B/D Register Pair Load accumulator indirect
 The contents of the designated register pair point to a memory location.
 This instruction copies the contents of that memory location into the accumulator.
 The contents of either the register pair or the memory location are not altered.
 Example: LDAX B
LXI Reg. pair, 16-bit Load register pair immediate
data
 This instruction loads 16-bit data in the register pair.
 Example: LXI H, 2034 H

LHLD 16-bit address Load H-L registers direct
 This instruction copies the contents of memory location pointed out by 16-bit
address into register L.
 It copies the contents of next memory location into register H.
 Example: LHLD 2040 H


STA 16-bit address Store accumulator direct
The contents of accumulator are copied into the

memory location specified by the operand.
Example: STA 2500 H

STAX Reg. pair Store accumulator indirect
 The contents of accumulator are copied into the memory location specified by
the contents of the register pair.
 Example: STAX B
SHLD 16-bit address Store H-L registers direct
 The contents of register L are stored into memory location specified by the 16-
bit address.
 The contents of register H are stored into the next memory location.
 Example: SHLD 2550 H

XCHG None Exchange H-L with D-E
 The contents of register H are exchanged with the contents of register D.
 The contents of register L are exchanged with the contents of register E.
 Example: XCHG
SPHL None Copy H-L pair to the Stack Pointer (SP)
 This instruction loads the contents of H-L pair into SP.
 Example: SPHL
XTHL None Exchange H–L with top of stack
 The contents of L register are exchanged with the location pointed out by the
contents of the SP.
 The contents of H register are exchanged with the next location (SP + 1).
 Example: XTHL
PCHL None Load program counter with H-L contents
 The contents of registers H and L are copied into the program counter (PC).
 The contents of H are placed as the high-order byte and the contents of L as the
low-order byte.
 Example: PCHL
PUSH Reg. pair Push register pair onto stack
 The contents of register pair are copied onto stack.
 SP is decremented and the contents of high-order registers (B, D, H, A) are copied

into stack.
 SP is again decremented and the contents of low-order registers (C, E, L, Flags) are
copied into stack.
 Example: PUSH B
POP Reg. pair Pop stack to register pair
 The contents of top of stack are copied into register pair.
 The contents of location pointed out by SP are copied to the low-order register (C,
E, L, Flags).
 SP is incremented and the contents of location are copied to the high-order register
(B, D, H, A).
 Example: POP H
OUT 8-bit port address Copy data from accumulator to a port with 8-bit
address
 The contents of accumulator are copied into the I/O port.
 Example: OUT 78 H
IN 8-bit port address Copy data to accumulator from a port with 8-bit
address
 The contents of I/O port are copied into accumulator.
 Example: IN 8C H
Arithmetic Instructions
• These instructions perform the operations like:
– Addition
– Subtract
– Increment
– Decrement
Addition
• Any 8-bit number, or the contents of register, or the contents of memory location
can be added to the contents of accumulator.
• The result (sum) is stored in the accumulator.
• No two other 8-bit registers can be added directly.
• Example: The contents of register B cannot be added directly to the contents of

register C.
Subtraction
• Any 8-bit number, or the contents of register, or the contents of memory location
can be subtracted from the contents of accumulator.
• The result is stored in the accumulator.
• Subtraction is performed in 2’s complement form.
• If the result is negative, it is stored in 2’s complement form.
• No two other 8-bit registers can be subtracted directly.

Increment / Decrement
• The 8-bit contents of a register or a memory location can be incremented or
decremented by 1.
• The 16-bit contents of a register pair can be incremented or decremented by 1.
• Increment or decrement can be performed on any register or a memory location.

ADD R Add register or memory to accumulator
M
 The contents of register or memory are added to the contents of accumulator.
 The result is stored in accumulator.
 If the operand is memory location, its address is specified by H-L pair.
 All flags are modified to reflect the result of the addition.
 Example: ADD B or ADD M

ADC R Add register or memory to accumulator with
M carry
 The contents of register or memory and Carry Flag (CY) are added to the contents
of accumulator.
 Example: ADC B or ADC M

ADI 8-bit data Add immediate to accumulator
 The 8-bit data is added to the contents of accumulator.
 Example: ADI 45 H
ACI 8-bit data Add immediate to accumulator with carry
 The 8-bit data and the Carry Flag (CY) are added to the contents of accumulator.
 Example: ACI 45 H
DAD Reg. pair Add register pair to H-L pair
 The 16-bit contents of the register pair are added to the contents of H-L pair.
 The result is stored in H-L pair.
 If the result is larger than 16 bits, then CY is set.
 No other flags are changed.
 Example: DAD B
SUB R Subtract register or memory from accumulator
M
 The contents of the register or memory location are subtracted from the contents
of the accumulator.
 All flags are modified to reflect the result of subtraction.
 Example: SUB B or SUB M

SBB R Subtract register or memory from accumulator
M with borrow
 The contents of the register or memory location and Borrow Flag (i.e. CY) are
subtracted from the contents of the accumulator.
 All flags are modified to reflect the result of subtraction.
 Example: SBB B or SBB M


SUI 8-bit data Subtract immediate from accumulator
The 8-bit data is subtracted from the contents of the

accumulator.
The result is stored in accumulator.
All flags are modified to reflect the result of subtraction.
Example: SUI 45 H

SBI 8-bit data Subtract immediate from accumulator with
borrow
The 8-bit data and the Borrow Flag (i.e. CY) is subtracted
from the contents of the accumulator.
The result is stored in accumulator.
All flags are modified to reflect the result of subtraction.
Example: SBI 45 H

INR R Increment register or memory by 1
M
The contents of register or memory location are

incremented by 1.
The result is stored in the same place.
If the operand is a memory location, its address is

specified by the contents of H-L pair.
Example: INR B or INR M

INX R Increment register pair by 1
The contents of register pair are incremented by 1.
Example: INX H

DCR R Decrement register or memory by 1
M
The contents of register or memory location are

decremented by 1.
If the operand is a memory location, its address is

specified by the contents of H-L pair.
Example: DCR B or DCR M

DCX R Decrement register pair by 1
The contents of register pair are decremented by 1.
Example: DCX H
Logical Instructions
• These instructions perform logical operations on data stored

in registers, memory and status flags.
• The logical operations are:

– AND
– OR
– XOR
– Rotate
– Compare
– Complement
AND, OR, XOR
• Any 8-bit data, or the contents of register, or memory location

can logically have
– AND operation
– OR operation
– XOR operation
with the contents of accumulator.
• The result is stored in accumulator.

Rotate
• Each bit in the accumulator can be shifted either left or right

to the next position.
Compare
• Any 8-bit data, or the contents of register, or memory location

can be compares for:
– Equality
– Greater Than
– Less Than
with the contents of accumulator.
• The result is reflected in status flags.

Complement
• The contents of accumulator can be complemented.
• Each 0 is replaced by 1 and each 1 is replaced by 0.


CMP R Compare register or memory with accumulator
M
The contents of the operand (register or memory) are

compared with the contents of the accumulator.
Both contents are preserved .
The result of the comparison is shown by setting the

flags of the PSW as follows:

CMP R Compare register or memory with accumulator
M
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset.
Example: CMP B or CMP M


CPI 8-bit data Compare immediate with accumulator
The 8-bit data is compared with the contents of

accumulator.
The values being compared remain unchanged.
The result of the comparison is shown by setting the

flags of the PSW as follows:

CPI 8-bit data Compare immediate with accumulator
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H


ANA R Logical AND register or memory with
M accumulator
The contents of the accumulator are logically ANDed with the contents
of register or memory.
The result is placed in the accumulator.
If the operand is a memory location, its address is specified by the
contents of H-L pair.
S, Z, P are modified to reflect the result of the operation.
CY is reset and AC is set.
Example: ANA B or ANA M.

ANI 8-bit data Logical AND immediate with accumulator
The contents of the accumulator are logically ANDed with

the 8-bit data.
S, Z, P are modified to reflect the result.
CY is reset, AC is set.
Example: ANI 86H.

XRA R Exclusive OR register or memory with
M accumulator
The contents of the accumulator are XORed with the contents of the register or
memory.
If the operand is a memory location, its address is specified by the contents of H-L
pair.
CY and AC are reset.
Example: XRA B or XRA M.


ORA R Logical OR register or memory with accumulator
M
The contents of the accumulator are logically ORed with the contents of the register
or memory.
If the operand is a memory location, its address is specified by the contents of H-L
pair.
Example: ORA B or ORA M.


ORI 8-bit data Logical OR immediate with accumulator
The contents of the accumulator are logically ORed with the

8-bit data.
Example: ORI 86H.

XRA R Logical XOR register or memory with
M accumulator
The contents of the accumulator are XORed with the contents of

the register or memory.
If the operand is a memory location, its address is specified by the
contents of H-L pair.
Example: XRA B or XRA M.

XRI 8-bit data XOR immediate with accumulator
The contents of the accumulator are XORed with the

8-bit data.
Example: XRI 86H.

RLC None Rotate accumulator left
Each binary bit of the accumulator is rotated left by one

position.
Bit D7 is placed in the position of D0 as well as in the
Carry flag.
CY is modified according to bit D7.
S, Z, P, AC are not affected.
Example: RLC.

RRC None Rotate accumulator right
Each binary bit of the accumulator is rotated right by one

position.
Bit D0 is placed in the position of D7 as well as in the
Carry flag.
Example: RRC.

RAL None Rotate accumulator left through carry
Each binary bit of the accumulator is rotated left by one

position through the Carry flag.
Bit D7 is placed in the Carry flag, and the Carry flag is
placed in the least significant position D0.
Example: RAL.

RAR None Rotate accumulator right through carry
Each binary bit of the accumulator is rotated right by one

position through the Carry flag.
Bit D0 is placed in the Carry flag, and the Carry flag is
placed in the most significant position D7.
Example: RAR.

CMA None Complement accumulator
The contents of the accumulator are complemented.

No flags are affected.
Example: CMA.

CMC None Complement carry
The Carry flag is complemented.

No other flags are affected.
Example: CMC.

STC None Set carry
The Carry flag is set to 1.

No other flags are affected.
Example: STC.
Branching Instructions
• The branching instruction alter the normal sequential flow.
• These instructions alter either unconditionally or

conditionally.

JMP 16-bit address Jump unconditionally
The program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand.
Example: JMP 2034 H.

Jx 16-bit address Jump conditionally

operand based on the specified flag of the PSW.
Example: JZ 2034 H.
Jump Conditionally
Opcode Description Status Flags

JC Jump if Carry CY = 1
JNC Jump if No Carry CY = 0
JP Jump if Positive S=0
JM Jump if Minus S=1
JZ Jump if Zero Z=1
JNZ Jump if No Zero Z=0
JPE Jump if Parity Even P=1
JPO Jump if Parity Odd P=0


CALL 16-bit address Call unconditionally

operand.
Before the transfer, the address of the next instruction
after CALL (the contents of the program counter) is
pushed onto the stack.
Example: CALL 2034 H.

Cx 16-bit address Call conditionally

operand based on the specified flag of the PSW.
Before the transfer, the address of the next instruction
after the call (the contents of the program counter) is
pushed onto the stack.
Example: CZ 2034 H.
Call Conditionally

CC Call if Carry CY = 1
CNC Call if No Carry CY = 0
CP Call if Positive S=0
CM Call if Minus S=1
CZ Call if Zero Z=1
CNZ Call if No Zero Z=0
CPE Call if Parity Even P=1
CPO Call if Parity Odd P=0


RET None Return unconditionally
The program sequence is transferred from the

subroutine to the calling program.
The two bytes from the top of the stack are copied into
the program counter, and program execution begins at
the new address.
Example: RET.

Rx None Call conditionally
The program sequence is transferred from the

subroutine to the calling program based on the
specified flag of the PSW.
The two bytes from the top of the stack are copied into
the program counter, and program execution begins at
the new address.
Example: RZ.
Return Conditionally

RC Return if Carry CY = 1
RNC Return if No Carry CY = 0
RP Return if Positive S=0
RM Return if Minus S=1
RZ Return if Zero Z=1
RNZ Return if No Zero Z=0
RPE Return if Parity Even P=1
RPO Return if Parity Odd P=0


RST 0–7 Restart (Software Interrupts)
The RST instruction jumps the control to one of eight

memory locations depending upon the number.
These are used as software instructions in a program
to transfer program execution to one of the eight
locations.
Example: RST 3.
Restart Address Table
Instructions Restart Address

RST 0 0000 H
RST 1 0008 H
RST 2 0010 H
RST 3 0018 H
RST 4 0020 H
RST 5 0028 H
RST 6 0030 H
RST 7 0038 H
Control Instructions
• The control instructions control the operation of

microprocessor.

NOP None No operation
No operation is performed.

The instruction is fetched and decoded but no
operation is executed.
Example: NOP

HLT None Halt
The CPU finishes executing the current instruction

and halts any further execution.
An interrupt or reset is necessary to exit from the halt
state.
Example: HLT
DI None Disable interrupt
The interrupt enable flip-flop is reset and all the

interrupts except the TRAP are disabled.
Example: DI
EI None Enable interrupt
The interrupt enable flip-flop is set and all interrupts

are enabled.
This instruction is necessary to re-enable the
interrupts (except TRAP).
Example: EI
RIM None Read Interrupt Mask
This is a multipurpose instruction used to read the

status of interrupts 7.5, 6.5, 5.5 and read serial data
input bit.
The instruction loads eight bits in the accumulator
with the following interpretations.
Example: RIM
Instruction and data format
• Each Instruction has two(2) parts; opcode and operand
• The operand(or data byte) can be specified in various ways.
• Operand may include 8-bit/16-bit data/address/memory location and internal
register.
•
Instruction Word size/byte
• Instruction word size classified into:
a) One word or one byte instructions.
 It include the opcode and operand in the same byte.
 Eg;i/MOV C,A ii/ADD B
b) Two word or two byte instructions.
 In 2-byte instruction, the first byte specifies the opcode and the second byte
specifies the operand.
 Eg;i/MVI A,data ///3E,data
 assume data is 32H///MVI A,32H///3E,32H
 So the first byte is 3E and the second byte is 32H.
c) Three word or three instructions.
 The first byte specifies the opcode and the other two bytes specifies 16-bit address.
 In hex code,if given 16-bit address(eg.2000H),the lower order memory
address(00H) will be first followed by high order memory address (20H)
mnemonic Hex code

JMP 2000H C3
00
20
Opcode format
• In the design of the 8085 microprocessor chip, all operations, registers and status
flags are identified with specific code.
• So, to understand opcode, we need to examine how an instruction is designed
into the microprocessor.
• Below are special code for the 8085 internal registers.
Code Registers Registers pair

000 B Code Register
001 C 00
010 D 01
011 E 10
100 H 11 SP
111 A
110 RESERVED FOR MEMORY
OPERTION
• The microprocessor operations related to data manipulation can be
summarized in four functions:
a) copying data
b) performing arithmetic operations
c) performing logical operations
d) testing for a given condition and alerting the program sequence
• Some important aspects of the instruction set are noted below:

– In data transfer, the contents of the source are not destroyed; only the contents of the destination
are changed. The data copy instructions do not affect the flags.
– Arithmetic and Logical operations are performed with the contents of the accumulator, and the
results are stored in the accumulator (with some expectations). The flags are affected according to
the results.
– Any register including the memory can be used for increment and decrement.
– A program sequence can be changed either conditionally or by testing for a given data condition.
INSTRUCTION FORMAT
INSTRUCTION FORMAT
• An instruction is a command to the microprocessor to perform a given
task on a specified data.
• Each instruction has two parts: one is task to be performed, called the
operation code (opcode), and the second is the data to be operated on,
called the operand.
• The operand (or data) can be specified in various ways. It may include 8-
bit(or 16-bit ) data, an internal register, a memory location, or 8-bit (or 16-
bit) address.
• In some instructions, the operand is implicit.
INSTRUCTION FORMAT ….
Instruction word size

The 8085 instruction set is classified into the following three groups according to word size:
MICROPROCESSOR TECHNOLOGY
COT 05212
Part 2
Sub-enabling
 Employ microprocessor addressing modes and instruction sets to perform
various operations
 Execute immediate addressing mode
 Execute Register addressing mode
 Execute direct memory addressing mode
 Execute register based indirect addressing mode
 Execute register relative addressing mode
 Execute base indexed addressing mode
 Execute relative based indirect addressing mode
 Execute implied addressing mode
 Utilize low-level programming languages to program microprocessor

 Edit, compile, execute, and debug an assembler program.
 Write a syntactically and semantically correct assembler program.
 Implement subroutine library within an assembler program.
 Manipulate standard data types and other forms of data within an
assembler program.
 Implement conditional and looping structures within an assembler
program.
 Create and use assembly subroutines and macros.
Sub-enabling
 Apply microprocessor techniques to solve various engineering problem
 Describe microprocessor elements in solving engineering problem
 Interface microprocessor elements with I/O devices.
 Program microprocessor elements for various applications.
 Implement testing microprocessor-based system using appropriate tools
ADDRESSING MODE
• These are the instructions used to transfer the data from one
register to another register, from the memory to the register,
and from the register to the memory without any alteration in
the content.
• Addressing modes in 8085 is classified into 5 groups:
 Immediate addressing mode
 Register addressing mode
 Direct addressing mode
 Indirect addressing mode
 Implied addressing mode
ADDRESSING MODE…
• Immediate addressing mode
• Register addressing mode
• Direct addressing mode
• Indirect addressing mode
• Implied addressing mode

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MICROPROCESSOR TECHNOLOGY

1. Describe CPU may be referred as Microprocessor

• This microprocessor is designed to execute complex instructions (a combination of

• This type of microprocessor is based on an architecture designed to execute simple

s/no RISC CISC

We are concerned with the language of widely used 8-bit

• The microprocessor uses these flags to test data conditions.

A0-A15 16-bit Address Address bus

D0-D7 Data bus Data

Memory read pulse (MEMR)

Demultiplexed address and data bus

Figure: Illustrate the steps and the timing of data flow

To fetch the byte(4FH),the MPU needs to

TRAP (RST 4.5) 24 H

INTERRUPT VECTOR ADDRESS

TRAP (RST 4.5) 24 H

Din D out Din Dout

Control//high Control//active low

Memory address lines

 Execution time for Opcode fetch;????

 Execution time for Memory read;????

 Execution time Instruction

Memory addr Machine code

See your Instruction set for that instruction; STA,addr

 The contents of the source register are not altered.

 Example: MOV B, C or MOV B, M

 The 8-bit data is stored in the destination register or memory.

 If the operand is a memory location, its location is specified by the contents of

 Example: MVI B, 57H or MVI M, 57H

 The contents of a memory location, specified by a 16-bit address in the

 The contents of the source are not altered.

 Example: LDA 2034H

 The contents of the designated register pair point to a memory location.

 This instruction loads 16-bit data in the register pair.

 Example: LXI H, 2034 H

 It copies the contents of next memory location into register H.

 Example: LHLD 2040 H

Opcode Operand Description

The contents of accumulator are copied into the

Example: STA 2500 H

 Example: SHLD 2550 H

XCHG None Exchange H-L with D-E

 The contents of register H are exchanged with the contents of register D.

 The contents of register L are exchanged with the contents of register E.

 This instruction loads the contents of H-L pair into SP.

 The contents of register pair are copied onto stack.

 SP is decremented and the contents of high-order registers (B, D, H, A) are copied

 The contents of top of stack are copied into register pair.

 The contents of accumulator are copied into the I/O port.

 The contents of I/O port are copied into accumulator.

• The result (sum) is stored in the accumulator.

• No two other 8-bit registers can be added directly.

• Example: The contents of register B cannot be added directly to the contents of

• The result is stored in the accumulator.

• Subtraction is performed in 2’s complement form.

• If the result is negative, it is stored in 2’s complement form.

• No two other 8-bit registers can be subtracted directly.

• The 16-bit contents of a register pair can be incremented or decremented by 1.

• Increment or decrement can be performed on any register or a memory location.

 The contents of register or memory are added to the contents of accumulator.

 The result is stored in accumulator.

 If the operand is memory location, its address is specified by H-L pair.

 All flags are modified to reflect the result of the addition.