15.

1 Processors, Parallel
Processing and Virtual Machines
Computer A 2 - Paper 3
Control Unit
Control Unit is the part of the computer’s
central processing unit (CPU), which
directs the operation of the processor
It was included as part of the Von
Neumann Architecture by John von
Neumann.
A control unit works by receiving input
information to which it converts into Fig. 1.0 Basic Computer Architecture
control signals, which are then sent to the
central processor.
The computer’s processor then tells the
attached hardware what operations to
perform.
 The functions that a control unit
performs are dependent on the type of
CPU because the architecture of CPU
varies from manufacturer to
manufacturer.
•Examples of devices that require a CU
are:
1. Control Processing Units(CPUs)
2. Graphics Processing Units(GPUs)
 • 2 types of control Unit are:
Control Unit 1) Hard-wired CU
Functions of the Control Unit :
1. It coordinates the sequence of 2) Micro-programmed CU
data movements into, out of, and
between a processor’s many sub-
units.
2. It interprets instructions.
3. It controls data flow inside the
processor.
4. It receives external instructions or
commands to which it converts to
sequence of control signals.
5. It controls many execution
units(i.e. ALU, data buffers and
registers) contained within a CPU.
6. It also handles multiple tasks,
such as fetching, decoding,
execution handling and storing
results.
Hardwired Control Unit
•In the Hardwired control unit, the
control signals that are important for
instruction execution control are
generated by specially designed
hardware logical circuits, in which we
can not modify the signal generation
method without physical change of the
circuit structure.
•The operation code of an instruction
contains the basic data for control signal
generation. In the instruction decoder,
the operation code is decoded. The
instruction decoder constitutes a set of
•This matrix implements logical combinations of
many decoders that decode different the decoded signals from the instruction opcode
fields of the instruction opcode. with the outputs from the matrix that generates
•As a result, few output lines going out signals representing consecutive control unit
from the instruction decoder obtains
active signal values. These output lines states and with signals coming from the outside of
are connected to the inputs of the the processor, e.g. interrupt signals. 
matrix that generates control signals for •The matrices are built in a similar way as a
executive units of the computer.
programmable logic arrays.
Micro-programmable control
unit
•The fundamental difference between
these unit structures and the structure
of the hardwired control unit is the
existence of the control store that is
used for storing words containing
encoded control signals mandatory for
instruction execution.
•In micro programmed control units,
subsequent instruction words are
fetched into the instruction register in
a normal way. 1) With a single-level control store:
• However, the operation code of each In this, the instruction opcode from the instruction register is
instruction is not directly decoded to sent to the control store address register. Based on this address,
enable immediate control signal the first microinstruction of a microprogram that interprets
generation but it comprises the initial execution of this instruction is read to the microinstruction
address of a micro program contained register. This microinstruction contains in its operation part
in the control store. encoded control signals, normally as few bit fields. In a set
microinstruction field decoders, the fields are decoded. The
microinstruction also contains the address of the next
microinstruction of the given instruction microprogram and a
control field used to control activities of the microinstruction
address generator.
Micro-programmable control
unit
•With a two-level control store:
In this, in a control unit with a two-
level control store, besides the control
memory for microinstructions, a nano-
instruction memory is included. In
such a control unit, microinstructions
do not contain encoded control
signals.
•The operation part of
microinstructions contains the address
of the word in the nano-instruction In this way, unnecessary storing of the same operation parts of
memory, which contains encoded
microinstructions is avoided. In this case, microinstruction word
control signals.
• The nano-instruction memory
can be much shorter than with the single level control store. It
contains all combinations of control gives a much smaller size in bits of the microinstruction memory
signals that appear in microprograms and, as a result, a much smaller size of the entire control
that interpret the complete instruction memory. The microinstruction memory contains the control for
set of a given computer, written once selection of consecutive microinstructions, while those control
in the form of nano-instructions. signals are generated at the basis of nano-instructions. In nano-
instructions, control signals are frequently encoded using 1 bit/
1 signal method that eliminates decoding.
Show understanding of
Reduced Instruction Set
•Instruction set or instruction set
architecture is the structure of the
computer that provides commands to
the computer to guide the computer
for processing data manipulation.
•Instruction set consists of
instructions, addressing modes, native
data types, registers, interrupt,
exception handling and memory RISC, or Reduced Instruction Set Computer. is a
architecture. Instruction set can be type of microprocessor architecture that utilizes
emulated in software by using an a small, highly-optimized set of instructions,
interpreter or built into hardware of
the processor.
rather than a more specialized set of instructions
•Instruction Set Architecture can be often found in other types of architectures.
considered as a boundary between the History
software and hardware.
The first RISC projects came from IBM,
Stanford, and UC-Berkeley in the late 70s and
early 80s. The IBM 801, Stanford MIPS, and
Berkeley RISC 1 and 2 were all designed with
a similar philosophy which has become
known as RISC.
Reduce Instruction Set
Computers (RISC)
processors
Basic Understanding of RISC & CISC
•https://cs.stanford.edu/people/erobe
rts/courses/soco/projects/risc/risccisc
/index.html
•https://www.youtube.com/watch?v=
bXypTvDLG9g

What is RISC?
A reduced instruction set computer is a computer that only uses simple commands that can
be divided into several instructions that achieve low-level operation within a single CLK cycle,
as its name proposes “Reduced Instruction Set”.

This is a small or reduced set of instructions. Here, every instruction is

expected to attain very small jobs. In this machine, the instruction sets
are modest and simple, which help in comprising more complex
commands. Each instruction is of a similar length; these are wound
together to get compound tasks done in a single operation. Most
commands are completed in one machine cycle. This pipelining is a
crucial technique used to speed up RISC machines.
Complex instruction set
computing (CISC)
What is CISC?
A complex instruction set computer is
CISC computers have small programs. It has a huge
a computer where single instructions number of compound instructions, which takes a long
can perform numerous low-level time to perform. Here, a single set of instructions is
operations like a load from memory, protected in several steps; each instruction set has
an arithmetic operation, and a
memory store or are accomplished by additional than 300 separate instructions. Maximum
multi-step processes or addressing instructions are finished in two to ten machine cycles. In
modes in single instructions, as its CISC, instruction pipelining is not easily implemented.
name proposes “Complex Instruction
Set ”.
Differences between RISC and CISC
 Understand interrupt handling on CISC and RISC processors
 the way exceptions/interrupts are handled is very much affected by the design philosophy. It’s more about how
the machine itself was designed and how the OS deals with said interrupts.
Fundamentally when an interrupt is received ( be it synchronous or asynchronous) , the processor will need to
jump to some kind of software routine that deals with said interrupt.
Traditionally , when a processor encounters an interrupt , the current context (GPR , status , PC) are pushed onto
a stack. Once the ISR is done executing, the saved context is popped back into the registers and execution
resumes from there. This has a couple advantages : no extra hardware is required , and most importantly it allows
for nested interrupts.
But that’s also not the only way to do it. Some architectures ( particularly early RISC architectures) had shadow
register files or register windows that could be used for handling interrupts without needing to save the current
thread context. This approach doesn’t allow for nested interrupts (or only a limited number of them) and has
generally fallen out of favor.
 Thank You

End of the Chapter