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Examine
Design
Develop
Test
Deploy
Maintenance
Cont.
Advantages of Embedded System :
Embedded systems are fast in performance.
Microprocessors
1. hardware characteristics
Complex Instruction Set Computer (CISC)
instructions
parallelism not necessarily exposed to the compiler
Microprocessor
Microcontroller
Embedded Processor
Media Processor
Microprocessor
SPP (Special Purpose Processor)
ASIC (Application-Specific Integrated Circuit)
ASIP (Application-Specific Instruction-set Processor)
DSP (Digital Signal Processor)
GPP core(s) or ASIP core(s) on either an Application Specific
Integrated Circuit (ASIC) or a Very Large Scale Integration
(VLSI) circuit.
Microprocessor
CISC RISC
Higher clock cycles per second. Low clock cycle per second.
Emphasis is on hardware. Emphasis is on software.
Control unit implements large
Each instruction is to be executed by
instruction set using micro-program
hardware.
unit.
Slower execution, as instructions are to
Faster execution, as each instruction is
be read from memory and decoded by
to be executed by hardware.
the decoder unit.
Pipelining of instructions is possible,
Pipelining is not possible.
considering single clock cycle.
Digital Signal Processor
The digital signal processor (DSP) is a special designed
processor to handle signals, rather than data.
Processing signals ( whether audio or video) is much more
complex than processing digital signals. To process audio
and video signals, the hardware/software needs to perform an
operation called filtering, in which unwanted frequencies are
removed.
Pipelines
32 bit architectures
Slave Select (SS): Signal line for slave device select. It is an active
low signal
1-wire interface (protocol)
1- Wire is a device communications bus system designed by
Dallas Semiconductor Corp. that provides low-speed data,
signaling, and power over a single conductor.
1-Wire is similar in concept to I²C, but with lower data rates and
longer range. It is typically used to communicate with small
inexpensive devices such as digital thermometers and weather
instruments.
Cont.
Parallel communication:
In data transmission, parallel communication is a method of
conveying multiple binary digits (bits) simultaneously. It
contrasts with communication.
The communication channel is the number of electrical
conductors used at the physical layer to convey bits.
Parallel communication implies more than one such conductor.
For example, an 8-bit parallel channel will convey eight bits (or a
byte) simultaneously, whereas a serial channel would convey
those same bits sequentially, one at a time. Parallel
communication is and always has been widely used within
integrated circuits, in peripheral buses, and in memory devices
such as RAM.
The Product level communication interface‟ (External
Communication Interface) is responsible for data transfer
between the embedded system and other devices or modules
It is classified into two types
2. USB
USB (UNIVERSAL SERIAL BUS)
External Bus Standard.
Allows connection of peripheral devices.
Connects Devices such as keyboards, mice, scanners, printers,
joysticks, audio devices, disks.
Facilitates transfers of data at 480 (USB 2.0 only), 12 or 1.5
Mb/s (Mega bits/second).
Developed by a Special Interest Group including Intel,
Microsoft, Compact, DEC, IBM, Northern Telecom and NEC
originally in 1994.
Low - Speed: 10 – 100 kb/s
1.5 Mb/s signalling bit rate
Full-Speed: 500 kb/s – 10 Mb/s 12 Mb/s signalling bit rate
High-Speed: 400 Mb/s
ATmega32 Architecture
Cont.
The CPU components are shaded blue.
The memory components are shaded green.
The clock components are shaded in orange.
The I/O components are shaded in purple.
The ATmega32 microcontroller uses Harvard architecture,
meaning that storage for instructions that make up the program
and storage for data operated upon by that program use
physically separate memory structures. The “program memory”
in the ATmega32 is 32K bytes in size
ATmega32 Highlights
Native data size is 8 bits (1 byte).
Uses 16-bit data addressing allowing it to address 216 = 65536
unique addresses.
Has three separate on-chip memories
2KiB SRAM
8 bits wide
used to store data
1KiB EEPROM
8 bits wide
used for persistent data storage
32KiB Flash
16 bits wide
used to store program code
Cont.
I/O ports A-D
Digital input/output
Analog input
Serial/Parallel
Pulse accumulator
Programmers Model
languages like C, C++, and Java require little, if any, knowledge
of the CPU's internal configuration.
Assembly language requires knowledge of the internals of the
CPU since we are operating at a lower level.
Machine language is the native language of the CPU
Consists only of 1's and 0's.
memory.
Is stored in the .hex file generated by AVR studio.
Program hierarchy:
High-level language gets converted into assembly language
by a compiler.
Assembly language gets converted into machine language by
an assembler.
CPU and Registers
Cont.
Steps to execution
Program Counter fetches program instruction from memory
The PC stores a program memory address that contains the
When we placed the bootloader on the chip, we set a fuse that enables
a reset vector to load the PC with the address where the bootloader
program starts.
When the program begins, the PC must contain the address of
the first instruction in the program.
Program instructions are stored in consecutive program
memory locations.
The PC is automatically incremented after each instruction.
Cont.
Note: There are jump instructions that can modify the PC
(e.g., the PC must change when calling or returning from
some other routine).
Places instruction in Instruction Register.
Instruction Decoder determines what the instruction is.
Arithmetic Logic Unit executes the instruction.
Cont.
The CPU clock determines the timing of when instructions are
fetched and executed:
Cont.
Registers
Directly accessed by the CPU/ALU — very fast.
Registers contain:
Address of the next instruction to fetch from program
memory (PC).
Machine instruction to be executed (IR).
ANDI
etc...
Often used when adding numbers that are larger than 8 bits. Here we
need to use an add with carry instruction (ADC) to add the next most
significant byte.
Zero flag (Z) set if result is zero.
BREQ instruction says branch if zero flag is set.
BRNE instruction says branch if zero flag is not set.
Negative flag (N) set if MSB is one.
Arithmetic instructions change the flags
Data transfer instructions do not change the flag.
The instruction set documentation identifies which flags each
instruction may modify.
Status Register (SREG)
Overflow flag (V) set if 2's complement overflow occurs.
An overflow occurs if you get the wrong sign for your result, e.g.,
6410 + 6410 = -12810 (010000002 + 010000002 = 100000002).
Note: whenever the carry into the MSB and the carry out don't match,
we have an overflow.
Sign bit (S) s = N EXOR V.
Half carry flag (H) is set when carry occurs from b3 to b4.
Used with binary coded decimal (BCD) arithemtic.
Memory
Memory
The address bus is 16 bits wide.
The data bus is 8 bits wide.
Program memory is stored on Flash from 0x0000 to 0x3FFF
(F_END).
Our boot loader is loaded in the last 1KiB of the Flash
memory.
SRAM is used for:
32 General Purpose registers from 0x00 to 0x1F.