Literature Review

Previous Work
Historically, work into RTL test generation has grown in two directions. One of them
is targeted at checking ASIC's DFT at RTL. The other addresses microprocessor generation
development at the architecture level. Efforts are directed at the RTL testing and DFT of
ASICs , aimed at the subsequent ease of automatic test pattern generation (ATPG) at the gate
stage. Using these modes, the ATPG tool is directed to generate vectors for the built-in
module. This method requires both the circuit's RTL and gate-level models and relies on the
types of RTL coding. Some other RTL strategies were targeted as the underlying test
methodology . Also investigated was hierarchical test generation of ASIC's at the RTL.
Nonetheless, ASIC's inherent inflexibility makes these methods very different from the one
proposed here. The generation of test programs is not fully automated and the scope in these
works is not guaranteed. In more recent work , two custom ATPG packages are used to
generate tests — one for full RTL justification and propagation and the other for module-
level pattern generation.
This method is more suited for microprocessor-like circuits where it is easy to satisfy
the values at internal bus lines. The technique is inefficient for DSP circuits or other specially
designed circuits and may not generate good quality test sets. In, a new ATPG-based
technique is proposed to test built-in modules in the microprocessor using constraints derived
from the surrounding logic where the module is embedded. Such limitations, however, are
manually removed. It is relatively new to research on instruction set assembly to test the
BIST targeting of DSP. Nevertheless, deterministic generation of tests is targeted in our
research. There has been some work done to exploit ASIP's properties for testing purposes.
The method of producing test programs was not clarified in this study, however, and no
empirical findings were provided in terms of fault models to demonstrate how successful
their approach was in evaluating ASIPs. First described was the approach of using pre-
computed test sets for acyclic RTL circuits. Nonetheless, most popular RTL circuits have a
lot of cycles in them.

From (W. Zhao and C.A. Papachristou, “An evolution programming ap- proach on
multiple behaviors for the design of application specific programmable processors,” in Proc.
European Design and Test Conf., Feb. 1996, pp. 144–150.) .
This paper introduces an Evolution Programming Approach to the Behavior-level
Area-Efficient Design of ASPPs (Application Specific Programmable Processors). This
method, based on a given behavioral-level kernel, randomly transforms each input behavior,
and then the behavioral kernel is used in the evolution process to direct the survival of data
flow graphs (DFGs). Eventually, the remaining DFGs are used to synthesize a programmable
architecture instead of the required DFGs. This results in an area-efficient design for all
behaviors of data. Experimental results show that this strategy is promoting.
 From “Architectural partitioning of control memory for application specific
programmable processors,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1995, pp. 521–
526. It says Due to Application Specific Programmable Processors (ASPPs) programmability,
microcode-based control is used effectively to operate ASPP datapaths for various
applications. That software requires a separate microprogram in ASPPs which results in large
microcode memory. This paper suggests a distributed microcode memory model in which
only separate microcodes are stored for saving memory area in each separate memory
module. For the development of this distributed microcode memory, a hierarchical clustering
approach is also suggested. Experimental results suggest that this method is particularly
suitable for ASPP microcode memory layout due to multiple behavioral repetitive
microcodes .

From S. Bhatia and N. K. Jha, “Behavioral synthesis for hierarchical testability

of controller/data path circuits with conditional branches,” in Proc. Int. Conf. Computer
Design, Oct. 1994, pp. 91–96. The sophistication of integrated digital systems has greatly
increased since their introduction in the late fifties. At the beginning of the sixties, Gordon
Moore estimated that the number of transistors in a chip would double about every two years.
Since then, this law, known as the law of Moore, has been fulfilled [ Sap84], in fact, the
complexity of integrated circuits now reaches a billion transistors. These complex circuits can
be built thanks to the use of a set of methodologies and programs that assist the engineer in
all phases of the design process.

From S. Dey and M. Potkonjak, “Non-scan design-for-testability of RT-level

data paths,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1994, pp. 640–645. This paper
introduces non-scan design-for-testing techniques that relate to data path circuits at the level
of register-transfer (RT). In order to develop successful non-scan DFT techniques, knowledge
of high-level design details in the context of the RT-level layout as well as the functions of
the RT-level components is used. Instead of traditional flip-flop (FF) selection techniques,
execution units (EXU) are chosen using the EXU S-graph presented in the paper.Using
register files and constants, controllability / observability points can be enforced.
We introduce the notion of controllable and measurable loops at k-level and show that
all loops at k-level can be controlled / observed, k > 0, in order to achieve very high test
efficiency. The new testing measure removes the need for conventional DFT techniques to
control / observe all loops directly(0-level), significantly reducing the overhead hardware
needed, and making the non-scan DFT method feasible and effective. We address ways to
avoid the creation of reconvergent regions when adding test points to make controllable /
observable loops at the k-level. We add dual points that use the different loop levels of
controllability / observability to make one loop controllable while making another loop
observable. We present efficient algorithms to add the minimal hardware that can be used to
control / observe all loops in the data path k-level without the use of FFs scan.
The non-scan DFT techniques have been applied to different circuits in the data path.
The experimental results demonstrate the efficacy of the measure of k-level testing and the
use of distributed and dual points to produce easily testable data paths with reduced overhead
hardware. The overhead equipment and the time required for testing the non-scan designs
were substantially lower than the partial scan designs. Most notably, the experimental results
demonstrate the ability of the RT-level DFT techniques to generate non-scan testable data
paths that can be measured at-speed.

From I. Ghosh, A. Raghunathan, and N. K. Jha, “Design for hierarchical

testability of RTL circuits obtained by behavioral synthesis,” in IEEE Trans. Computer-
Aided Design, vol. 16, pp. 1001–1014, Sept. 1997. There has been increasing interest in
testability of behavioral (high-level) synthesis in recent years. This is due to the fact that,
when added during logic synthesis in the later phase of the development cycle, testing
features such as scanning or the built-in self-test will incur high overheads. Similar previous
work attempted to produce test sets at system level during behavioral replication using
hierarchical testability. The test generation scheme is independent of the bit width and is
therefore able to handle complex controller / data path circuits with large data path bit widths
(e.g. 32), which posed a serious challenge to sequential test generators at the logic level.
Nevertheless, if another high-level synthesis method is used, this previous work is not
applicable. In this paper, we present techniques that add minimal test hardware to a given
circuit of register-transfer level (RTL) obtained through behavioral synthesis to ensure that
the elements embedded in the circuit are hierarchically testable. An significant by-product of
our testing design (DFT) technique is a system-level test set that delivers pre-computed test
sets for each RTL circuit component. This removes the need for the combined controller /
data route to apply sequential test generation at the gate level.
We have performed comprehensive experiments with several complex controller /
data path circuits that are synthesized by three different high-level synthesis systems that do
not require research. The key advantages of our process, demonstrated by these tests, include:
1) the area, delay and power overheads incurred for testing are very small (the average area,
delay and power overheads for a large number of benchmarks are 3.5, 0.5, and 3.4 percent
respectively), 2) both the DFT hardware implementation and the test generation algorithms
are independent of the data path bit size.
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http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.35.2831&rep=rep1&type=pdf

https://ieeexplore.ieee.org/abstract/document/658568?section=abstract