[Computer Architecture CIA-3]

[Assignment Topic: CISC (Complex Instruction Set Computer) versus RISC (Reduced
Instruction Set Computer)]

[By : Nikhil Kumar Yadav]

[Roll. No. : 1847241]

[Date of Submission : 06-09-2019]

[RISC versus CISC : Compare and Contrast CISC
and RISC characteristics]
The architectural design of the CPU is Reduced instruction set computing (RISC) and Complex
instruction set computing (CISC). CISC has the capacity to perform multi-step operations or
addressing modes within one instruction set. It is the CPU design where one instruction works
several low-level acts. For instance, memory storage, loading from memory, and an arithmetic
operation. Reduced instruction set computing is a Central Processing Unit design strategy based
on the vision that basic instruction set gives a great performance when combined with a
microprocessor architecture which has the capacity to perform the instructions by using some
microprocessor cycles per instruction. This article discusses the RISC and CISC architecture
with appropriate diagrams. The hardware part of the Intel is named as Complex Instruction Set
Computer (CISC), and Apple hardware is Reduced Instruction Set Computer (RISC).

[What is RISC and CISC]

A complex instruction set computer is a computer where single instructions can perform
numerous low-level operations like a load from memory, an arithmetic operation, and a memory
store or are accomplished by multi-step processes or addressing modes in single instructions, as
its name propose “Complex Instruction Set”.

A reduced instruction set computer is a computer which only uses simple commands that can be
divided into several instructions which achieve low-level operation within a single CLK cycle, as
its name propose “Reduced Instruction Set”.

[RISC Architecture]

The term RISC stands for ‘’Reduced Instruction Set Computer’’. It is a CPU design plan based
on simple orders and acts fast.

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This is small or reduced set of instructions. Here, every instruction is expected to attain very
small jobs. In this machine, the instruction sets are modest and simple, which help in comprising
more complex commands. Each instruction is about the similar length; these are wound together
to get compound tasks done in a single operation. Most commands are completed in one machine
cycle. This pipelining is a crucial technique used to speed up RISC machines.

Reduced Instruction Set Computer is a microprocessor that is designed to carry out few
instructions at the similar time. Based on small commands, these chips need fewer transistors,
which make the transistors inexpensive to design and produce. The features of RISC include the
following

 The demand of decoding is less

 Few data types in hardware
 General purpose register Identical
 Uniform instruction set
 Simple addressing nodes

[“Also, while writing a program, RISC makes it easier by letting the computer programmer to
eliminate needless codes and stops wasting of cycles.”]

[CISC Architecture]

The term CISC stands for ‘’Complex Instruction Set Computer’’. It is a CPU design plan based
on single commands, which are skilled in executing multi-step operations.

CISC computers have small programs. It has a huge number of compound instructions, which
takes a long time to perform. Here, a single set of instruction is protected in several steps; each
instruction set has additional than 300 separate instructions. Maximum instructions are finished
in two to ten machine cycles. In CISC, instruction pipelining is not easily implemented.

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The CISC machines have good acts, based on the overview of program compilers; as the range
of innovative instructions are simply obtainable in one instruction set. They design compound
instructions in the single, simple set of instructions. They achieve low-level processes, that
makes it easier to have huge addressing nodes and additional data types in the hardware of a
machine. But, CISC is considered less efficient than RISC, because of its incompetence to
eliminate codes which lead to wasting of cycles. Also, microprocessor chips are difficult to
understand and program for, because of the complexity of the hardware.

[Comparison Between RISC AND CISC]

RISC stands for ‘Reduced Instruction Set Computer Whereas, CISC stands for Complex
Instruction Set Computer. The RISC processors have a smaller set of instructions with few
addressing nodes. The CISC processors have a larger set of instructions with many addressing
nodes.

Memory Unit

RISC has no memory unit and uses a separate hardware to implement instructions. CISC has a
memory unit to implement complex instructions

Program

RISC has a hard-wired unit of programming. CISC has a microprogramming unit

Design

RISC is a complex compiler design. CISC is an easy compiler design

Calculations

RISC calculations are faster and more precise. CISC calculations are slow and precise

Decoding

RISC decoding of instructions is simple. CISC decoding of instructions is complex

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Time

Execution time is very less in RISC. Execution time is very high in CISC.

External memory

RISC does not require external memory for calculations. CISC requires external memory for
calculations.

Pipelining

RISC Pipelining does function correctly. CISC Pipelining does not function correctly.

Stalling

RISC stalling is mostly reduced in processors. CISC processors often stall.

Code Expansion

Code expansion can be a problem in RISC whereas, in CISC, Code expansion is not a problem.

Disc space

Space is saved in RISC whereas in CISC space is wasted. The best examples of CISC instruction
set architecture include VAX, PDP-11, Motorola 68k,And your desktop PCs on Intel’s x86
architecture, whereas the best examples of RISC architecture include DEC Alpha, ARC, AMD
29k, Atmel AVR, Intel i860, Blackfin, i960, Motorola 88000, MIPS, PA-RISC, Power, SPARC,
SuperH, and ARM too.

[Applications of RISC and CISC]

RISC is used in high-end applications like video processing, telecommunications and image
processing. CISC is used in low-end applications such as security systems, home automation,
etc.

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[Conclusion]
From the above comparison of RISC and CISC, finally, we can conclude that we cannot
distinguish between RISC and CISC technology because both are apt at its precise application.
Today, both RISC and CISC designers are doing all to get an edge on the competition.

[Evaluate Performance of RISC and CISC]

[CISC Approach]
The primary goal of CISC architecture is to complete a task in as few lines of assembly as
possible. This is achieved by building processor hardware that is capable of understanding &
executing a series of operations, this is where our CISC architecture introduced.

For this particular task, a CISC processor would come prepared with a specific instruction (we’ll
call it “MULT”). When executed, this instruction

1. Loads the two values into separate registers

2. Multiplies the operands in the execution unit
3. And finally third, stores the product in the appropriate register.

Thus, the entire task of multiplying two numbers can be completed with one instruction:

MULT A, B <<<======this is an assembly statement

MULT is what is known as a “complex instruction.” It operates directly on the

computer’s memory banks and does not require the programmer to explicitly call any loading or
storing functions.

Advantage:

4. Compiler has to do very little work to translate a high-level language statement into
assembly
5. Length of the code is relatively short
6. Very little RAM is required to store instructions
7. The emphasis is put on building complex instructions directly into the hardware.

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[RISC Approach]
RISC processors only use simple instructions that can be executed within one clock cycle. Thus,
the “MULT” command described above could be divided into three separate commands:

8. “LOAD” which moves data from the memory bank to a register

9. “PROD” which finds the product of two operands located within the registers
10.“STORE” which moves data from a register to the memory banks.

In order to perform the exact series of steps described in the CISC approach, a programmer
would need to code four lines of assembly:

LOAD R1, A <<<======this is an assembly statement

LOAD R2, B <<<======this is an assembly statement

PROD A, B <<<======this is an assembly statement

STORE R3, A <<<======this is an assembly statement

At first, this may seem like a much less efficient way of completing the operation. Because there
are more lines of code, more RAM is needed to store the assembly level instructions. The
compiler must also perform more work to convert a high-level language statement into code of
this form.

Advantage: -

11.Each instruction requires only one clock cycle to execute, the entire program will execute
in approximately the same amount of time as the multi-cycle “MULT” command.
12.These RISC “reduced instructions” require less transistors of hardware space than the
complex instructions, leaving more room for general purpose registers. Because all of the
instructions execute in a uniform amount of time (i.e. one clock)
13.Pipelining is possible.

LOAD/STORE mechanism: - Separating the “LOAD” and “STORE” instructions actually

reduces the amount of work that the computer must perform. After a CISC-style “MULT”

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command is executed, the processor automatically erases the registers. If one of the operands
needs to be used for another computation, the processor must re-load the data from the memory
bank into a register. In RISC, the operand will remain in the register until another value is loaded
in its place.

[Example of RISC and CISC]

Example – Suppose we have to add two 8-bit number:

 CISC approach: There will be a single command or instruction for this like ADD which
will perform the task.
 RISC approach: Here programmer will write first load command to load data in
registers then it will use a suitable operator and then it will store result in desired
location.

So, add operation is divided into the parts i.e. load, operate, store due to which RISC programs
are longer and require more memory to get stored but require less transistors due to a less
complex command.

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