COMPUTER ARCITECTURE

ASSIGNMENT

RISC-REDUCED INSTRUCTION SET COMPUTER

 RISC-REDUCED INSTRUCTION SET COMPUTER

INTRODUCTION:

 RISC, or Reduced Instruction Set Computer.

 is a type of microprocessor architecture that utilizes a
small,
 highly-optimized set of instructions,
 rather than a more specialized set of instructions often
found in other types of architectures.

HISTORY:

The first RISC projects came from IBM, Stanford, and UC-
Berkeley in the late 70s and early 80s. The IBM 801, Stanford
MIPS, and Berkeley RISC 1 and 2 were all designed with a similar
philosophy which has become known as RISC. Certain design
features have been characteristic of most RISC processors:

 one cycle execution time: RISC processors have a CPI (clock

per instruction) of one cycle. This is due to the optimization
of each instruction on the CPU and a technique called 
pipelining
 pipelining: a techique that allows for simultaneous execution
of parts, or stages, of instructions to more efficiently process
instructions;
 large number of registers: the RISC design philosophy
generally incorporates a larger number of registers to
prevent in large amounts of interactions with memory

Main Characteristics of RISC Architectures:

• The instruction set is limited and includes only simple
instructions.
• Only LOAD and STORE instructions reference data in
memory.

• Instructions use only few addressing modes.

• Instructions are of fixed length and uniform format.

• A large number of registers is available.

RISC Processor Architecture (Block diagram):

 RISC processor is implemented using the hardwired control
unit. The hardwired control unit produces control
signals which regulate the working of processors hardware.
RISC architecture emphasizes on using the registers rather
than memory.
 This is because the registers are the ‘fastest’ available
memory source. The registers are physically small and are
placed on the same chip where the ALU and the control unit
are placed on the processor. The RISC
instructions operate on the operands present
in processor’s registers.

 Below we have the block diagram for the RISC architecture.

 Advantages and Disadvantages of RISC Processor

Advantages of RISC  Processor

1. RISC instructions are simpler machine instruction.

2. RISC instructions are hardwired to fasten the execution.
3. There are very fewer instructions in s RISC instruction set.
4. RISC instruction has simple addressing modes.
5. RISC instruction executes faster because most of
instruction operates on processor register and there is no
need to access memory for each instruction.
6. It is easy to pipeline RISC instruction as all instruction is of
fixed size and opcode and operand are located in the same
position in the word.
7. RISC instructions execute one instruction per clock cycle.
 Disadvantages of RISC Processor

1. RISC instruction
size is reduced but more instructions are required to perform an
operation when compared with CISC. So, we can say that the
length of the program is increased.
2. The machine
instructions are hardwired in RISC so, it would cost if any
instruction needs modification.
3. It finds
is difficulty in processing complex instruction and complex
addressing mode.
4. RISC instructions
do not allow direct memory to memory transfer, it requires Load
and Store instructions to do so.