COMPUTER

ORGANIZATION AND ASSEMBELY

LAGUAGE

RISC COMPUTER ARCHITECTURE

RISC, which stands for Reduced Instruction Set Computing, is a
type of computer architecture that emphasizes simplicity and
efficiency in instruction execution. RISC architectures are
designed to streamline the execution of instructions by using a
smaller set of simple instructions.

EXAMPLES:
Examples of RISC architectures include MIPS (Microprocessor
without Interlocked Pipeline Stages), SPARC (Scalable Processor
Architecture), and ARM (Advanced RISC Machine).

CHARECTERISTICS:
1. Simple Instructions:
 RISC architectures use a reduced set of simple
instructions, each typically taking one clock cycle to
 execute. This simplicity allows for faster instruction
execution.
2. Fixed Instruction Length:
 Instructions in RISC architecture have a fixed length,
often 32 bits. This fixed length simplifies instruction
decoding and pipelining, as each instruction takes up a
uniform amount of space.
3. Load/Store Architecture:
 RISC architectures often follow a load/store model,
meaning that arithmetic operations only operate on
data in registers, and data must be explicitly loaded
from memory into registers before performing
operations. The results are then stored back in
registers.
4. Single-Cycle Execution:

 The goal of RISC architectures is to execute

instructions in a single clock cycle whenever
possible. Each instruction performs a specific and
elementary operation, making it easier to pipeline
and execute quickly.
5. Register Use:
  RISC architectures typically have a larger number of
general-purpose registers. The emphasis is on keeping
data in registers for quick access and minimizing the
need to fetch data from memory.

6. Pipelining:
 RISC architectures often employ pipelining, where the
execution of instructions is broken down into stages,
and each stage can process a different instruction
concurrently. This enhances throughput and makes
better use of hardware resources.
7. Parallelism:
 RISC architectures encourage parallelism by simplifying
instruction formats and reducing dependencies
between instructions. This allows for easier
identification of parallelizable instructions, facilitating
the use of parallel processing techniques.
8. Hardwired Control Unit:
 RISC processors typically use a hardwired control unit
rather than a micro-programmed one. This means that
the control signals for executing instructions are
directly implemented using combinational logic,
contributing to faster instruction execution.
9. Optimized for Compiler:
 RISC architectures are designed with a focus on
optimizing compiler efficiency. The simple instruction
set allows compilers to more easily schedule and
optimize code for execution.

ADVANTAGES OF RISC:
The advantages of RISC architecture include improved
performance, better compiler support, and a more
straightforward design. However, RISC architectures may
require more complex compilers to fully exploit their
potential, and the benefits may vary depending on the
application and workload.

CISC COMPUTER ARCHITECTURE

CISC, or Complex Instruction Set Computing, is a type of
computer architecture that features a large set of instructions
with complex and variable-length formats. CISC architectures
are designed to perform a wide variety of operations in a single
instruction. Here are the key characteristics of CISC
architecture:

1. Complex Instructions:
  CISC architectures support a wide range of
complex instructions that can perform multiple
low-level operations in a single instruction.
These instructions often involve memory access,
arithmetic operations, and control flow.
2. Variable-Length Instructions:
 Unlike RISC architectures, CISC instructions can
have variable lengths. The length of an
instruction can vary, and it may include different
addressing modes and operand types. This
flexibility allows a single instruction to perform
more complex tasks but can complicate
instruction decoding.
3. Memory Access:
 CISC architectures often include instructions
that directly operate on memory locations,
reducing the need for explicit load and store
instructions. This can simplify the programming
model but may result in slower execution,
especially in modern memory hierarchies.
4. Multiple Addressing Modes:
  CISC architectures typically support a variety of
addressing modes, allowing instructions to
operate on different types of operands
(registers, immediate values, memory
addresses, etc.). This flexibility can make it
easier for programmers to express their intent
but may complicate the decoding and execution
process.
5. Hardware-Based Control Unit:
 CISC architectures often use a micro
programmed control unit, where instructions
are decoded and executed using a sequence of
microinstructions stored in a control memory.
This approach allows for more complex
instruction execution but may introduce
additional overhead.
6. Specialized Instructions:
 CISC architectures often include specialized
instructions for common tasks, such as string
manipulation, high-level language constructs,
and mathematical operations. This can reduce
 the number of instructions required to perform
certain operations but may also lead to
increased complexity.
7. Low Number of General-Purpose Registers:
 Compared to RISC architectures, CISC
architectures may have a smaller number of
general-purpose registers. This design choice
allows for more complex instructions but may
increase the need for memory accesses,
impacting performance.
8. Emphasis on Hardware Support:
 CISC architectures often include specialized
hardware support for certain operations, such
as multiply and divide instructions. This can
improve the performance of specific tasks but
may also increase the complexity of the
processor.
EXAMPLES
Examples of CISC architectures include x86 (e.g., Intel
and AMD processors), VAX (Virtual Address extension),
and IBM 360/370. CISC architectures were historically
popular due to their ability to reduce the number of
instructions needed for complex tasks, making them
suitable for general-purpose computing. However,
modern processors often use a combination of CISC and
RISC principles to achieve a balance between
performance and simplicity.
The choice between RISC and CISC is
based on the application, feature requirements and
available technology. Their effectiveness based on
intended use.