THE AVR MICROCONTROLLER: Module II

AN OVERVIEW MPMC 2022

INTRODUCTION
• The basic architecture of AVR was designed by two students of
Norwegian Institute of Technology (NTH), Alf-Egil Bogen
and Vegard Wollan, and then was bought and developed by
Atmel in 1996.
• The AVR stands for Advanced Virtual RISC, or Alf and
Vegard RISC.
• The AVR is an 8-bit RISC single-chip microcontroller with
Harvard architecture.
• Contains on chip FLASH , EEPROM, SDRAM memory and
built in peripherals like ADC
TYPES
• tinyAVR- smallest version 8 bit, 8kB of internal FLASH, 512 bytes of SRAM
and EEPROM.
• megaAVR-high performance with hw multiplier, 256kB of internal FLASH
program memory and 8K SRAM and 4K EEPROM.
• XMEGA High performace with inbuilt DMA
• Application based AVR:
• Automotive AVR, CAN AVR, LCD AVR, Lighting AVR etc.
AVR PART NUMBERS
BASIC FEATURES
The AVR processor family has the following features:
❑On-chip and In-System Programmable Flash memory used as Program Memory.
❑32-X-8 general-purpose working registers
❑On-chip data memory EEPROM and RAM
❑0 to 10-MHz clock speed operation. (Most instructions operate in 1 clock cycle, and this leads to an
almost 10-times performance improvement over conventional processors (e.g., the 8051) operating at
an equal clock frequency.)
❑On-chip programmable timer
❑Internal and external interrupt sources.
❑Programmable watchdog timer with an independent oscillator. This is used to recover in case of a
software crash
❑SLEEP and POWER DOWN modes of operation (This saves power when the processor is idling.)
❑Many chips with on-chip RC clock oscillators.
❑Wide device range (from a small 8-pin processor to a 68-pin processor), and one can choose a
processor to suit a given requirement while being able to use the same development facilities.
 ARCHITECTURE
❑The AVR uses Harvard architecture.
❑This entails separate data and
program memory buses.
❑The data memory data bus is an
8-bit bus and connects most of the
peripheral components to the
register file.
❑The program memory data bus is
16 bits wide and only feeds the
instruction register.
❑The program memory, besides
storing instructions, also stores
interrupt vectors
CONT..
❑The data memory, on the other hand, is split up in different
types. It has in five different components:
 A register file with 32 registers of 8-bit width.
 64 I/O registers of 8 bits each.
 Internal SRAM. (The amount of SRAM varies between 128 bytes to 4 Kbytes.
The SRAM is used for stack as well as storing variables. )
 External SRAM.
 EEPROM (Available on almost all AVR processors and is accessed in a
separate memory map. Various processors have between 64 bytes and 4
Kbytes of EEPROM.)
THE
•
REGISTER FILE
All AVR processors have 32 general-purpose registers.(
The registers are named R0 through R31.)
• Stack Pointer, Program Counter, Instruction Register,
Instruction Decoder and Status and control registers.
• All 32 registers are connected to ALU but 2
independent registers can be accessed in a single
instruction
• Register access time= 1 clock cycle
• 6 registers are used as 16 bit Indirect Address Registers
(X,Y and Z)
The following registers can be applied for specific use
• R1:R0 store the result of multiplication instruction
• R0 stores the data loaded from the program memory
• I/O registers – 64 8-bit registers
• Used in input/output instructions
• Status register (SREG) – A special I/O register to store
status
STATUS REGISTER (SREG)
❑The STATUS register contains 8-flag bits that indicate the current state of the
processor.
❑All these bits are cleared (i.e., at logic “0”) at reset and can be read or written to
by the program.
I T H S V N Z C
The various flags of the STATUS register and their functions are:
Bit7-I: Global Interrupt Enable. Setting this bit enables all the interrupts. Resetting this disables all
interrupts.
Bit6-T: Bit Copy Storage. Used with BLD (bit load) and BST (bit store) instructions for loading and storing
bits from one register to another.
Bit5:H. Half Carry Flag. Indicates half carry in some arithmetic instructions.
Bit4:S. Sign Flag. This bit is the exclusive OR between the negative flag N and the Overflow flag V.
Bit3:V. Two’s Complement Overflow Flag.
Bit2:N. Negative Flag.
Bit1:Z. Zero Flag.
Bit0:C. Carry Flag. Indicates a carry in arithmetic or logical operation.
STACK POINTER REGISTER
❑This register is 1 byte wide for processors that have up to 256 bytes of SRAM and
is 2 bytes wide (called SPH and SPL) for those processors that have more than 256
bytes of SRAM.
❑This register is used to point to the area in SRAM that is the top of the stack.
❑The stack grows down in memory address—i.e., pushing a value on stack results in
the SP getting decremented. Popping a value out of stack increments the SP.
THE ALU
❑The arithmetic logic unit (ALU) performs such operations as bit, arithmetic, and logic
upon the contents of the registers and writes back the result into the register file into
the designated register.
❑These operations are performed in a single clock cycle.
❑Each ALU operation affects the flags in the STATUS register, depending upon the
instruction
I/O MEMORY
❑Can be accessed in two ways: as SRAM as well as I/O registers.
❑To access the I/O registers, the AVR offers IN and OUT instructions.
SRAM
The SRAM is available on most high-end processors.
The amount varies from 128 bytes to 4 Kbytes.
The SRAM is accessed using the many data access instructions either directly or
indirectly using a pointer register.
The SRAM is used for the stack also. The SRAM access time is two clock cycles
INTERNAL WATCHDOG TIMER
A watchdog timer is a controlled timer that is used as a wakeup device in case the
software is lost in some infinite loop or in case of faulty program execution.
The watchdog timer has an output that has the capability to reset the controller.
The watchdog reset instruction, WDR, resets the watchdog timer.
OTHER FEATURES
10 different Addressing modes
Instructions types
 Data Transfer Instructions (MOV, LDI, STS, IN, OUT, PUSH, POP)
 Arithmetic and Logic Instructions( ADD, SUB, AND, OR, EOR, COM, NEG, MUL)
 Program Control Instructions (RJMP k, IJMP, CALL, Branch, Skip)
 Bit and Bit-test Instructions (SBI, CBI, SEC, CLC, NOP. SLEEP, WDR)
PIPELINING
❑AVR allows pipelined architecture (pre-fetch+execution)
❑Most of the AVR instructions are 1 word (2 bytes) long and so take 1 program memory location.
❑Many instructions execute in a single clock cycle, and a few take 2 or more clock cycles.
❑This single-cycle execution is achieved due to the use of a 2-stage pipeline.
❑The pipeline works by concurrently acquiring a new instruction from the program memory while the
previous instruction is executing in the other part of the processor.
❑Thus instruction fetch and decode and execution are processes that are being performed by the processor
concurrently
END OF SLIDES