INT numbers

&
NVIC Registers

1
2303ENG Embedded Systems(NA and GC)
 Interrupt numbers
 Determine interrupt
number for port/device.

 E.g. For port B, interrupt

number is 1.

Interrupt #0-15 contain faults,

software interrupt and SysTick,
which are handled differently
to interrupts 16-63
 Interrupt Vectors (TM4C1294)
Interrupt Vector Interrupt Interrupt Vector Interrupt
Description Description
Number Address Handlers Number Address Handlers
0x0000.0000 to 36 0x0000.00D0 16/32-Bit Timer 3B void TIMER3B_Handler();
– Processor exceptions
0x0000.003C 37 0x0000.00D4 I2C1 Master and Slave void I2C1_Handler();
0 0x0000.0040 GPIO Port A void GPIOA_Handler(); 38 0x0000.00D8 CAN0 void CAN0_Handler();
1 0x0000.0044 GPIO Port B void GPIOB_Handler(); 39 0x0000.00DC CAN1 void CAN1_Handler();
2 0x0000.0048 GPIO Port C void GPIOC_Handler(); 40 0x0000.00E0 Ethernet MAC void ETH_Handler();
3 0x0000.004C GPIO Port D void GPIOD_Handler(); 41 0x0000.00E4 Hibernate void HIB_Handler();
4 0x0000.0050 GPIO Port E void GPIOE_Handler(); 42 0x0000.00E8 USB MAC void USB0_Handler();
5 0x0000.0054 UART0 Rx and Tx void UART0_Handler(); 43 0x0000.00EC PWM Generator 3 void PWM0_3_Handler();
6 0x0000.0058 UART1 Rx and Tx void UART1_Handler(); 44 0x0000.00F0 μDMA 0 Software void UDMA_Handler();
7 0x0000.005C SSI0 Rx and Tx void SSI0_Handler(); 45 0x0000.00F4 μDMA 0 Error void UDMAERR_Handler();
8 0x0000.0060 I2C0 Master and Slave void I2C0_Handler(); 46 0x0000.00F8 ADC1 Sequence 0 void ADC1SS0_Handler();
9 0x0000.0064 PWM0 Fault void PWM0_FAULT_Handler(); 47 0x0000.00FC ADC1 Sequence 1 void ADC1SS1_Handler();
10 0x0000.0068 PWM0 Generator 0 void PWM0_0_Handler(); 48 0x0000.0100 ADC1 Sequence 2 void ADC1SS2_Handler();
11 0x0000.006C PWM0 Generator 1 void PWM0_1_Handler(); 49 0x0000.0104 ADC1 Sequence 3 void ADC1SS3_Handler();
12 0x0000.0070 PWM0 Generator 2 void PWM0_2_Handler(); 50 0x0000.0108 EBI0 External Bus Interface 0 void EBI0_Handler();
13 0x0000.0074 QEI0 Quadrature Encoder 0 void QEI0_Handler(); 51 0x0000.010C GPIO Port J void GPIOJ_Handler();
14 0x0000.0078 ADC0 Sequence 0 void ADC0SS0_Handler(); 52 0x0000.0110 GPIO Port K void GPIOK_Handler();
15 0x0000.007C ADC0 Sequence 1 void ADC0SS1_Handler(); 53 0x0000.0114 GPIO Port L void GPIOL_Handler();
16 0x0000.0080 ADC0 Sequence 2 void ADC0SS2_Handler(); 54 0x0000.0118 SSI2 Rx and Tx void SSI2_Handler();
17 0x0000.0084 ADC0 Sequence 3 void ADC0SS3_Handler(); 55 0x0000.011C SSI3 Rx and Tx void SSI3_Handler();
18 0x0000.0088 Watchdog Timers 0 and 1 void WDT0_Handler(); 56 0x0000.0120 UART3 Rx and Tx void UART3_Handler();
19 0x0000.008C 16/32-Bit Timer 0A void TIMER0A_Handler(); 57 0x0000.0124 UART4 Rx and Tx void UART4_Handler();
20 0x0000.0090 16/32-Bit Timer 0B void TIMER0B_Handler(); 58 0x0000.0128 UART5 Rx and Tx void UART5_Handler();
21 0x0000.0094 16/32-Bit Timer 1A void TIMER1A_Handler(); 59 0x0000.012C UART6 Rx and Tx void UART6_Handler();
22 0x0000.0098 16/32-Bit Timer 1B void TIMER1B_Handler(); 60 0x0000.0130 UART7 Rx and Tx void UART7_Handler();
23 0x0000.009C 16/32-Bit Timer 2A void TIMER2A_Handler(); 61 0x0000.0134 I2C2 Master and Slave void I2C2_Handler();
24 0x0000.00A0 16/32-Bit Timer 2B void TIMER2B_Handler(); 62 0x0000.0138 I2C3 Master and Slave void I2C3_Handler();
25 0x0000.00A4 Analog Comparator 0 void COMP0_Handler(); 63 0x0000.013C Timer 4A void TIMER4A_Handler();
26 0x0000.00A8 Analog Comparator 1 void COMP1_Handler(); 64 0x0000.0140 Timer 4B void TIMER4B_Handler();
27 0x0000.00AC Analog Comparator 2 void COMP2_Handler(); 65 0x0000.0144 Timer 5A void TIMER5A_Handler();
28 0x0000.00B0 System Control (PLL, OSC, BO) void SYSCTL_Handler(); 66 0x0000.0148 Timer 5B void TIMER5B_Handler();
29 0x0000.00B4 Flash Memory Control void FLASH_Handler();
67 0x0000.014C Floating-Point Exception (imprecise) void FPU_Handler();
30 0x0000.00B8 GPIO Port F void GPIOF_AHB_Handler();
31 0x0000.00BC GPIO Port G void GPIOG_Handler(); 68 ~ 69 Reserved
32 0x0000.00C0 GPIO Port H void GPIOH_Handler(); 70 0x0000.0158 I2C4 Master and Slave void I2C4_Handler();
33 0x0000.00C4 UART2 Rx and Tx void UART2_Handler(); 71 0x0000.015C I2C5 Master and Slave void I2C5_Handler();
34 0x0000.00C8 SSI1 Rx and Tx void SSI1_Handler(); 72 0x0000.0160 GPIO Port M void GPIOM_Handler();
35 0x0000.00CC 16/32-Bit Timer 3A void TIMER3A_Handler(); 73 0x0000.0164 GPIO Port N void GPION_Handler();
Interrupt Vectors (cont)

Interrupt Vector Interrupt

Description
Number Address Handlers
74 – Reserved
75 0x0000.016C Tamper void TAMPER_Handler();
76 0x0000.0170 GPIO Port P (Summary or P0) void GPIOP0_Handler();
77 0x0000.0174 GPIO Port P1 void GPIOP1_Handler();
78 0x0000.0178 GPIO Port P2 void GPIOP2_Handler();
79 0x0000.017C GPIO Port P3 void GPIOP3_Handler();
80 0x0000.0180 GPIO Port P4 void GPIOP4_Handler();
81 0x0000.0184 GPIO Port P5 void GPIOP5_Handler();
82 0x0000.0188 GPIO Port P6 void GPIOP6_Handler();
83 0x0000.018C GPIO Port P7 void GPIOP7_Handler();
84 0x0000.0190 GPIO Port Q (Summary or Q0) void GPIOQ0_Handler();
85 0x0000.0194 GPIO Port Q1 void GPIOQ1_Handler();
86 0x0000.0198 GPIO Port Q2 void GPIOQ2_Handler();
87 0x0000.019C GPIO Port Q3 void GPIOQ3_Handler();
88 0x0000.01A0 GPIO Port Q4 void GPIOQ4_Handler();
89 0x0000.01A4 GPIO Port Q5 void GPIOQ5_Handler();
90 0x0000.01A8 GPIO Port Q6 void GPIOQ6_Handler();
91 0x0000.01AC GPIO Port Q7 void GPIOQ7_Handler();
92-97 – Reserved
98 0x0000.01C8 16/32-Bit Timer 6A void TIMER6A_Handler();
99 0x0000.01CC 16/32-Bit Timer 6B void TIMER6B_Handler();
100 0x0000.01D0 16/32-Bit Timer 7A void TIMER7A_Handler();
101 0x0000.01D4 16/32-Bit Timer 7B void TIMER7B_Handler();
102 0x0000.01D8 I2C6 Master and Slave void I2C6_Handler();
103 0x0000.01DC I2C7 Master and Slave void I2C7_Handler();
104~108 – Reserved
109 0x0000.01F4 I2C8 Master and Slave void I2C8_Handler();
110 0x0000.01F8 I2C9 Master and Slave void I2C9_Handler();
111 ~ 113 – Reserved
 NVIC Registers
Set the NVIC to configure the interrupts using the designated interrupt number. The interrupt
number is between 0 and 110. n is 0, 1, 2 ,3 eg NVIC->PEND3
Programatically:
Starting Name n =Type
int(INTNUM/32);Description
b=INTNUM%32 Code
TheAddress
NVIC registers are as follows:
0xE000.E100 NVIC_ENn RW Interrupt Enable Register NVIC->ISER[n] |= (1<<b) ;
(1bit / interrupt number)

0xE000.E180 NVIC_DISn RW Interrupt Disable Register NVIC->ICER[n] |= (1<<b) ;

(1bit / interrupt number)

0xE000.E200 NVIC_PENDn RW Interrupt Set Pending Register NVIC->ISPR[n] |= (1<<b) ;

(1bit / interrupt number)

0xE000.E280 NVIC_UNPENDn RW Interrupt Clear-Pending Register NVIC->ICPR[n] |= (1<<b) ;

(1bit / interrupt number)

0xE000.E300 NVIC_ACTIVEn RO Interrupt Active Bit Register NVIC->IABR[n] |= (1<<b) ;

(1bit / interrupt number)

0xE000.E400 NVIC_PRIn RW Interrupt Priority Register NVIC->IP[intnum] = priority;

3 bits per interrupt number (0 <= priority <= 7)
4 interrupt numbers per register (0 is lowest priority)
 Interrupt Number and Relationship to NVIC Registers
Interrupt ENable Register
Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN1 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
EN2 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
EN3 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96

Interrupt DISable Register

Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIS0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIS1 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
DIS2 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
DIS3 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96

Interrupt PEND Register

Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEND0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEND1 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
PEND2 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
PEND3 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96

Interrupt UNPEND Register

Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNPEND0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNPEND1 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
UNPEND2 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
UNPEND3 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96

Programmatically
Regnum = int(INTNUM/32); BitPosition=INTNUM%32
NVIC->DIS[Regnum]=(1<<BitPosition) ;
NVIC Interrupt EN registers
Define NVIC_EN as 0xE000E100
Can access as NVIC_EN[0] for NVIC_EN0
(Interrupt set-enable registers) Can access as NVIC_EN[1] for NVIC_EN1 etc

Enable Reg. : NVIC_EN0, NVIC_EN1, NVIC_EN2, …

Base address: E000.E000 Offset 0x100, 0x104, 0x108, …

32-bit registers used to enable interrupts for each of devices.

For a particular device, there is a single enable bit associated with it.

For NVIC_EN0, bit 0 corresponds to interrupt (IRQ) 0,

& bit 31 corresponds to IRQ 31.
For NVIC_EN1, bit 0 corresponds to IRQ 32,
& bit 31 corresponds to IRQ 63. etc.

If read bit in NVIC_ENn: 0 = interrupt disabled, 1= interrupt enabled

If write to bit: 0 = no effect, 1 = enables interrupt
ie: can only use this register to set (enable) the interrupt!!

Clear Enable (DISn) register – required to disable (clear-enable) interrupt on device.

NVIC Interrupt DIS registers
Define NVIC_DIS as 0xE000E180
Can access as NVIC_DIS[0] for NVIC_DIS0
(interrupt clear-enable registers) Can access as NVIC_DIS[1] for NVIC_DIS1 etc

Clear Enable Reg: NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, …

Base address: E000.E000, offset 0x180, 0x184, 0x188, …

32-bit registers used to clear interrupt-enable bit for each of devices.

For a particular device, there is a single clear-enable bit associated with it.
For NVIC_DIS0, bit 0 corresponds to interrupt (IRQ) 0,
& bit 31 corresponds to IRQ 31.
For NVIC_DIS1, bit 0 corresponds to IRQ 32,
& bit 31 corresponds to IRQ 63. etc.
If read bit in NVIC_DISn: 0 = interrupt disabled, 1= interrupt enabled
If write to bit: 0 = no effect, 1 = disables interrupt & clears bit in NVIC_ENn Reg.
ie: can only use this register to clear (disable) the interrupt!!
NVIC Interrupt PEND registers
Define NVIC_PEND as 0xE000E180
Can access as NVIC_PEND[0] for NVIC_PEND0
(interrupt set-pending registers)
Can access as NVIC_PEND[1] for NVIC_PEND1 etc
Set pending Reg.: NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, …
Base address: E000.E000, offset 0x200, 0x204, 0x208, …

►32-bit registers which can force interrupts into pending state, and show
which interrupts are pending.
►For a particular device, there is a single set pending bit associated with it.

►For NVIC_PEND0, bit 0 corresponds to interrupt (IRQ) 0,

& bit 31 corresponds to IRQ 31.
►For NVIC_PEND1, bit 0 corresponds to IRQ 32,
& bit 31 corresponds to IRQ 63. etc.

►If read bit: 0 = interrupt not pending, 1= interrupt is pending

►If write to bit: 0 = no effect, 1 = interrupt set to pending, even if disabled.
►Can only clear this register using UNPENDn register.
NVIC Interrupt UNPEND registers
Define NVIC_UNPEND as 0xE000E280
(interrupt clear-pending registers) Can access as NVIC_UNPEND[0] for NVIC_UNPEND0
Can access as NVIC_UNPEND[1] for NVIC_UNPEND1 etc

Clear-pending Reg.: NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2,

…
Base address: E000.E000, offset 0x280, 0x284, 0x288, …

►32-bit registers which can clear pending state from interrupts, and show which
interrupts are pending.
►For a particular device, there is a single clear pending bit associated with it.

►For NVIC_UNPEND0, bit 0 corresponds to interrupt (IRQ) 0,

& bit 31 corresponds to IRQ 31.
►For NVIC_UNPEND1, bit 0 corresponds to IRQ 32,
& bit 31 corresponds to IRQ 63. etc.

►If read bit: 0 = interrupt not pending, 1= interrupt is pending

►If write to bit: 0 = no effect, 1 = clears corresponding bit in PENDn register, so
interrupt is no longer pending.
►Setting bit in UNPENDn register does not affect state of corresponding interrupt
 NVIC Interrupt ACTIVE registers
Define NVIC_ACTIVE as 0xE000E300
Can access as NVIC_ACTIVE[0] for NVIC_ACTIVE0
(interrupt Active Bit registers) Can access as NVIC_ACTIVE[1] for NVIC_ACTIVE1 etc

Active Bit Reg.: NVIC_ACTIVE0, NVIC_ACTIVE1, NVIC_ACTIVE2, …

Base address: E000.E000, offset 0x300, 0x304, 0x308, …

• 32-bit registers which indicate which interrupts are active.

• For a particular device, there is a single active bit associated with it.
• This is READ ONLY register.

• For NVIC_ACTIVE0, bit 0 corresponds to interrupt (IRQ) 0,

& bit 31 corresponds to IRQ 31.
• For NVIC_ACTIVE1, bit 0 corresponds to IRQ 32,
& bit 31 corresponds to IRQ 63. etc.

• If read bit: 0 = interrupt not active,

1= interrupt is active, or active & pending
NVIC Interrupt Priority registers
Define NVIC_PRI as 0xE000E400
Can access as NVIC_PRI[0] for NVIC_PRI0
Can access as NVIC_PRI[1] for NVIC_PRI1 etc

Set pending registers: NVIC_PRI0_R, NVIC_PRI1_R,

…, NVIC_PRI34_R
Base address: E000.E000, offset 0x400, 0x404, …,0x488

• Allows setting of priority for interrupts 0-138

• PRI registers provide 3-bit priority fields for each interrupt,
and each register holds priority fields for 4 interrupts
• PRI registers are byte accessible
• Priority values are 0-7, where the lower the value, the greater the priority of
the corresponding interrupt
• Values of reserved bits should be preserved when modifying registers (ie,
use non-destructive programming)

• Recall: If interrupt with lower priority occurs, current interrupt is suspended

until more important interrupt handled. Then other interrupt is finished.
(nested interrupts)
NVIC Interrupt Priority registers

Set priority registers: NVIC_PRI0_R, NVIC_PRI1_R,

…, NVIC_PRI34_R
Base address: E000.E000, offset 0x400, 0x404, …,0x488

PRIn register bit field Name Interrupt Number

Bits 31:29 INTD Interrupt [4n+3]

Bits 23:21 INTC Interrupt [4n+2]

Bits 15:13 INTB Interrupt [4n+1]

Bits 7:5 INTA Interrupt [4n]

Programmatically
Regnum = int(INTNUM/4); INTABCD=(INTNUM%4)
 Eg Setting Priority
Question
If we want a high priority (say 1) for UART 6, which register and bits should be set?

Solution
UART 6 = interrupt number 59

59/4 = 14 rem 3 (count is from 0(A),1(B),2(C),3(D))

14 is the register number
3 is the INT number (int D)

59 = 4 * 14 + 3 , therefore use NVIC_PRI14 bits 31:29,

and set value to 0x01 for these bits.

Using the <TM4C129.h> nomenclature:

NVIC->IP[59] = 1 ;
3 2

NVIC_PRI14

1 0
External GPIO Interrupts : Basic method
1. Disable ALL interrupts

2. Configure GPIO subsystem: typically a regular I/O port

3. Set GPIO registers to allow interrupts of the desired sense

4. Set NVIC to enable interrupts for port using designated interrupt

number and set priority (NVIC->ENn, NVIC->PRIn)

5. Enable ALL interrupts

6. The interrupt service routine should:

Perform the algorithm to handle the event
Clear the interrupt using the Interrupt Clear register.
Set the bit corresponding to the pin to clear the IRQ.
( eg GPIOx->ICR)