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  • Design 1

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    Srmito1
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    This document contains a diagram of a Zynq processing system with an AXI interconnect module connecting multiple AXI slave and master interfaces. It includes processing system blocks like the DDR memory controller and peripherals like Ethernet and USB. The AXI interconnect routes transactions between the processing system AXI ports and external AXI fullconnected and convolution modules.

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    design

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    design_1

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    This document contains a diagram of a Zynq processing system with an AXI interconnect module connecting multiple AXI slave and master interfaces. It includes processing system blocks like the DDR memory controller and peripherals like Ethernet and USB. The AXI interconnect routes transactions between the processing system AXI ports and external AXI fullconnected and convolution modules.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    30 views1 page

    Design 1

    Uploaded by

    Srmito1
    This document contains a diagram of a Zynq processing system with an AXI interconnect module connecting multiple AXI slave and master interfaces. It includes processing system blocks like the DDR memory controller and peripherals like Ethernet and USB. The AXI interconnect routes transactions between the processing system AXI ports and external AXI fullconnected and convolution modules.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    ps7_0_axi_periph

    S00_AXI
    S01_AXI
    S02_AXI
    S03_AXI
    S04_AXI
    S05_AXI
    ACLK
    ARESETN
    S00_ACLK
    S00_ARESETN
    S01_ACLK
    S01_ARESETN M00_AXI
    S02_ACLK M01_AXI

    S02_ARESETN
    S03_ACLK
    S03_ARESETN
    S04_ACLK
    S04_ARESETN
    S05_ACLK
    S05_ARESETN
    M00_ACLK
    M00_ARESETN
    convolution_0
    M01_ACLK
    M01_ARESETN
    s_axi_CTRL_BUS m_axi_INPUT_r
    ap_clk m_axi_OUTPUT_r
    AXI Interconnect
    fullconnected_0
    ap_rst_n interrupt

    m_axi_IN_r
    s_axi_CTRL Convolution (Pre-Production)
    rst_ps7_0_102M m_axi_W
    ap_clk
    m_axi_OUT_r
    ap_rst_n
    slowest_sync_clk mb_reset interrupt
    ext_reset_in bus_struct_reset[0:0]
    aux_reset_in peripheral_reset[0:0] Fullconnected (Pre-Production)

    mb_debug_sys_rst interconnect_aresetn[0:0]
    dcm_locked peripheral_aresetn[0:0]

    Processor System Reset

    processing_system7_0

    GMII_ETHERNET_0 DDR
    DDR FIXED_IO
    FIXED_IO
    SDIO_0
    USBIND_0
    ENET0_EXT_INTIN
    M_AXI_GP0
    M_AXI_GP0_ACLK
    TTC0_WAVE0_OUT
    TTC0_WAVE1_OUT
    TTC0_WAVE2_OUT
    FCLK_CLK0
    FCLK_RESET0_N

    ZYNQ7 Processing System

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