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Tpic 8101
Tpic 8101
TPIC8101
SLIS110C – APRIL 2003 – REVISED MARCH 2015
Simplified Schematic
Vref
VDD / 2 +
−
CH1P +
CH1N −
CH1FB Mux SAR
rd
3 Order AAF 10-Bit ADC <1:10>
CH2P + fS = 200 kHz
CH2N −
CH2FB
DSP
R2R
10-Bit DAC SPI
fS = 200 kHz +
Test Mode
− DSP Control
SDI
XIN
INT/HOLD
GND
SDO
VDD
OUT
XOUT
SCLK
CS
TEST
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPIC8101
SLIS110C – APRIL 2003 – REVISED MARCH 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 9
2 Applications ........................................................... 1 8.3 Feature Description................................................... 9
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 12
8.5 Programming........................................................... 14
4 Revision History..................................................... 2
5 Description (continued)......................................... 3 9 Application and Implementation ........................ 16
9.1 Application Information............................................ 16
6 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 16
7 Specifications......................................................... 4
10 Power Supply Recommendations ..................... 19
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
7.3 Recommended Operating Conditions....................... 4
11.2 Layout Example .................................................... 19
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics........................................... 5 12 Device and Documentation Support ................. 20
7.6 Timing Requirements ............................................... 7 12.1 Trademarks ........................................................... 20
7.7 Typical Characteristics .............................................. 8 12.2 Electrostatic Discharge Caution ............................ 20
12.3 Glossary ................................................................ 20
8 Detailed Description .............................................. 9
8.1 Overview ................................................................... 9 13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
5 Description (continued)
The data from the A/D enables the system to analyze the amount of retard timing for the next spark ignition
timing cycle. With the microprocessor closed-loop system, advancing and retarding the spark timing optimizes
the load/RPM conditions for a particular engine (data stored in RAM).
VDD 1 20 CH1P
GND 2 19 CH1N
Vref 3 18 CH1FB
OUT 4 17 CH2FB
NC 5 16 CH2N
NC 6 15 CH2P
INT/HOLD 7 14 TEST
CS 8 13 SCLK
XIN 9 12 SDI
XOUT 10 11 SDO
Pin Functions
PIN TYPE
DESCRIPTION
NAME NO. (PULLUP/PULLDOWN)
VDD 1 I 5-V input supply
GND 2 I Ground connection
Vref 3 O Supply reference generator with external bypass capacitor
OUT 4 O Buffered integrator output
5
NC (1) — No connection
6
INT/HOLD 7 I (pulldown) Selectable for integrate (high) or hold (low) mode (with internal pulldown)
CS 8 I (pullup) Chip select for SPI communications (active low with internal pullup)
XIN 9 I Inverter input for oscillator
XOUT 10 O Inverter output for oscillator
SDO 11 O Serial data output for SPI bus
SDI 12 I (pullup) Serial data input line
SCLK 13 I (pullup) SPI clock
TEST 14 I (pullup) Test mode (active low), open for normal operation
CH2P 15 I Positive input for amplifier 2
CH2N 16 I Negative input for amplifier 2
CH2FB 17 O Output of amplifier 2, for feedback connection
CH1FB 18 O Output of amplifier 1, for feedback connection
CH1N 19 I Negative input for amplifier 1
CH1P 20 I Positive input for amplifier 1
(1) These terminals are to be used for test purposes only and are not connected in the system application. No signal traces should be
connected to the NC terminals.
7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
(2) (3)
VDD Regulated input voltage −0.3 7 V
(2) (3)
VO Output voltage −0.3 7 V
VIN Input voltage (2) (3) −0.3 7 V
IIN DC input current on terminals CH1P, CH1N, CH2P, and CH2N (2) (3) 2 mA
VDCIN DC input voltage on terminals CH1P, CH1N, CH2P and CH2N (2) (3) 14 V
RθJA Junction-to-ambient thermal impedance 120 °C/W
PD Continuous power dissipation 200 mW
TA Operating ambient temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Absolute negative voltage on these terminals is not to go < –0.5 V.
(1) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each terminal.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(1) 150-mV input amplitude on the 4-MHz clock input only applies if the feedback network is completed. Without the feedback network, the
4-MHz signal should be at 0- to 5-V levels.
t2 t9
t3 t8
t1 t5 t1
t4
CS
SCLK
t7
t6
INT/HOLD
t10
Output Signal
Output Signal
8 Detailed Description
8.1 Overview
The TPIC8101 is designed for knock sensor signal conditioning in automotive applications. The device is an
analog interface between the engine acoustical sensors or accelerometers and the fuel management systems of
a gasoline engine. The two wide-band amplifiers process signals from the piezoelectric sensors. Outputs of the
amplifiers feed a channel select MUX switch and then a third-order antialiasing filter. This signal is converted
using an analog-to-digital conversion (10 bits with a sampling frequency of 200 kHz) prior to the gain stage.
Vref
VDD/2 +
CH1P +
CH1N −
CH2N −
CH2FB
Programmable
Programmable Programmable
Band-Pass Rectifier
Gain Integrator
Filter
DSP
R2R
10-Bit DAC + SPI
fs = 200 kHz Test Mode
− DSP Control
VDD GND OUT SDO SDI SCLK CS TEST INT/HOLD XIN XOUT
C
CH1N
−
R1
Knock Sensor 1 CH1P + CH1FB
Vref
CH2P + CH2FB
C R1
−
CH2N
Knock Sensor 2
R2
NOTE: The series capacitor C is not mandatory and may be removed in some application circuits
Table 2. Advanced SPI Mode Control Bytes and Expected Response (continued)
NO. Code Command (t) Data Response (t)
Inverted SPI configuration
6 0111 0001 Set SPI configuration to the advanced mode None
(MSB)10001110(LSB)
8.5 Programming
Table 3. Integrator Programming
Integrator Time Band-Pass Band-Pass
Decimal Value Decimal Value
Constant Frequency Gain Frequency Gain
(D4:D0) (D5:D0)
(µs) (kHz) (kHz)
0 40 1.22 2 32 4.95 0.421
1 45 1.26 1.882 33 5.12 0.4
2 50 1.31 1.778 34 5.29 0.381
3 55 1.35 1.684 35 5.48 0.364
4 60 1.4 1.6 36 5.68 0.348
5 65 1.45 1.523 37 5.9 0.333
6 70 1.51 1.455 38 6.12 0.32
7 75 1.57 1.391 39 6.37 0.308
8 80 1.63 1.333 40 6.64 0.296
9 90 1.71 1.28 41 6.94 0.286
10 100 1.78 1.231 42 7.27 0.276
11 110 1.87 1.185 43 7.63 0.267
12 120 1.96 1.143 44 8.02 0.258
13 130 2.07 1.063 45 8.46 0.25
14 140 2.18 1 46 8.95 0.236
15 150 2.31 0.944 47 9.5 0.222
16 160 2.46 0.895 48 10.12 0.211
17 180 2.54 0.85 49 10.46 0.2
18 200 2.62 0.81 50 10.83 0.19
19 220 2.71 0.773 51 11.22 0.182
20 240 2.81 0.739 52 11.65 0.174
21 260 2.92 0.708 53 12.1 0.167
22 280 3.03 0.68 54 12.6 0.16
23 300 3.15 0.654 55 13.14 0.154
24 320 3.28 0.63 56 13.72 0.148
25 360 3.43 0.607 57 14.36 0.143
26 400 3.59 0.586 58 15.07 0.138
27 440 3.76 0.567 59 15.84 0.133
28 480 3.95 0.548 60 16.71 0.129
29 520 4.16 0.5 61 17.67 0.125
30 560 4.39 0.471 62 18.76 0.118
31 600 4.66 0.444 63 19.98 0.111
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
VDD
OUT
4.7 µF
A/D
R2
CH1FB
3.3 nF
CS
CH1N
R1 SCLK
Knock Sensor 1
TPIC8101 SDI
CH1P
SDO
Microprocessor
Vref TEST
100 nF
INT/HOLD
CH2P
470 pF
XIN
R2
CH2FB 1 kΩ
3.3 nF XOUT
CH2N 1 MΩ
R1
Knock Sensor 2 GND
For this design example, use the parameters specified in Table 5. This example is for a resonant knock sensor.
Using Equation 4:
3 ms
WC 106 Ps
2 u S u 4.5 (6)
Using Equation 5:
S 4.5 V 0.125 V
AP ( ) u (106 Ps) u
8 (0.15 V) u (3 ms) (7)
AP = 0.38
Table 6 lists the parameters to program.
Figure 6 shows the input and output signals for this design example.
For a resonant knock sensor (as in the design example), the center frequency of the bandpass filter is set to the
resonant frequency of the knock sensor. For a flat-type knock sensor, the bandpass filter design equation can be
used to determine where the center frequency should be set.
The transfer function of the biquadratic bandpass IIR filter is:
b0 b2 u z 2
HBP (z) GBP u
a0 a1 u z 1 a2 u z 2
sin(Z)
With b0 D , b2 Da0 1 D , a1 2 u cos(Z) , a2 1 D , D
2uQ (8)
fcenter fcenter
Z u Su ,Q , and G(fc2 ) G(fc1) G(fcenter ) 3 dB
fsampling fc2 fc1
7270 kHz,
300 mVpp
INT, 3 ms
4.48 V
Output
11 Layout
VDD CH1P
To channel 1 sensor
GND CH1N
Expand GND plane to second VREF CH1FB
layer through vias, and use to
fill in spaces on top layer OUT CH2FB
NC CH2N
To channel 2 sensor
NC CH2P
INT/HOLD /TEST
XIN SDI
XOUT SDO
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 20-Apr-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Apr-2024
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC
13.0 2X
12.6 11.43
NOTE 3
10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4
0.33
TYP
0.10
0.25
SEE DETAIL A GAGE PLANE
1.27 0.3
0 -8 0.40 0.1
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10 11
(9.3)
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10 11
(9.3)
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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