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Chapter5 Memory Hierarchy
Chapter5 Memory Hierarchy
Source: internet
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Static RAM (SRAM) cell
Source: https://commons.wikimedia.org/wiki/File:SRAM_Cell_(6_Transistors).svg
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DRAM Technology
▪ Data stored as a charge in a capacitor
▪ Single transistor used to access the charge
▪ Must periodically be refreshed
▪ Read contents and write back
▪ Performed on a DRAM “row”
Bank
Column
Rd/Wr
Act
Pre
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Row
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Advanced DRAM Organization
▪ Bits in a DRAM are organized as a rectangular
array
▪ DRAM accesses an entire row
▪ Burst mode: supply successive words from a row
with reduced latency
▪ Double data rate (DDR) DRAM
▪ Transfer on rising and falling clock edges
▪ Quad data rate (QDR) DRAM
▪ Separate DDR inputs and outputs
▪ Cache memory X1 X1
present? X3 X3
000
111
001
010
011
100
101
110
▪ Direct mapped: only one choice
▪ (Block address) modulo (#Blocks in cache)
▪ #Blocks is a power of 2
▪ Use low-order address bits
MEMORY
Given 8-byte block (line)
→ offset of x = 2
→ offset of a = 5 …
x …
a …
…
…
x …
a …
…
Idx 0 Idx 1 Idx 2 Idx 3 Idx 4 Idx 5 Idx 6 Idx 7 Idx 0 Idx 7
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Addressing - Tag
31 0
Tag Index Offset
# bits # bits # bits
Cache
▪ Tag Tag 1 Tag 0
▪ Determined which block ID is
stored at specific index in a x
cache a
Miss/Hit ratio
▪ After executing the given piece Idx 0 Idx 1 Idx 2 Idx 3 Idx 4 Idx 5 Idx 6 Idx 7
of C code. What is miss/hit ratio?
MEMORY
▪ a = b + c; Tag 0 Tag 0 Tag 0 Tag 0 Tag 0 Tag 0 Tag 0 Tag 0 Tag 1 Tag 1 … Tag n
▪ d = a + i; a z …
d c i …
▪ g= h + z;
b g …
▪ b = a + c; h …
▪ d = i + h; Idx 0 Idx 1 Idx 2 Idx 3 Idx 4 Idx 5 Idx 6 Idx 7 Idx 0 Idx 7
▪ 26
▪ 22 Index V Tag Data
▪ 26 000 N
001 N
▪ 16 010 N
▪ 3 011 N
100 N
▪ 16 101 N
▪ 18 110 Y 10 Mem[10110]
111 N
▪ 26
▪ 22 Index V Tag Data
▪ 26 000 N
001 N
▪ 16 010 Y 11 Mem[11010]
▪ 3 011 N
100 N
▪ 16 101 N
▪ 18 110 Y 10 Mem[10110]
111 N
▪ 22 22
26
10 110
11 010
Hit
Hit
110
010
▪ 26
▪ 22 Index V Tag Data
▪ 26 000 N
001 N
▪ 16 010 Y 11 Mem[11010]
▪ 3 011 N
100 N
▪ 16 101 N
▪ 18 110 Y 10 Mem[10110]
111 N
▪ 22 16
3
10 000
00 011
Miss
Miss
000
011
▪ 26 16 10 000 Hit 000
▪ 26 000 Y 10 Mem[10000]
001 N
▪ 16 010 Y 11 Mem[11010]
▪ 3 011 Y 00 Mem[00011]
100 N
▪ 16 101 N
▪ 18 110 Y 10 Mem[10110]
111 N
▪ 26
▪ 22 Index V Tag Data
▪ 26 000 Y 10 Mem[10000]
001 N
▪ 16 010 Y 10 Mem[10010]
▪ 3 011 Y 00 Mem[00011]
100 N
▪ 16 101 N
▪ 18 110 Y 10 Mem[10110]
111 N
1021
1022
1023
20 32
18 8 4 Byte Data
Hit Tag offset
Index Block offset
18 bits 512bits
V Tag Data
256
entries
18 32 32 32
=
Mux
32
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Measuring Cache Performance
▪ Components of CPU time
▪ Program execution cycles
▪ Includes cache hit time
▪ Memory stall cycles
▪ Mainly from cache misses
▪ With simplifying assumptions:
Memory stall cycles
Memory accesses
= Miss rate Miss penalty
Program
Instructio ns Misses
= Miss penalty
Program Instructio n
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I-cache, D-cache
Data
Instruction Data
memory memory
IM REG ALU DM
Stall Stall …. Stall DM REG
1 1 1
Tag 2 Tag 2
Tag 2
0 set associative
1 Set Tag Data Tag Data Tag Data Tag Data
2 0
3 1
4 Eight-way set associative (fully associative)
5
data
data
data
data
data
data
data
Tag
Tag
Tag
Tag
Tag
Tag
Tag
Tag
Tag
6
7
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Associativity Example
▪ Compare 4-block caches
▪ Direct mapped, 2-way set associative,
fully associative
▪ Block access sequence: 0, 8, 0, 6, 8
▪ Direct mapped (100% Miss)
Block Cache Hit/miss Cache content after access
address index 0 1 2 3
0 0 miss Mem[0]
8 0 miss Mem[8]
0 0 miss Mem[0]
6 2 miss Mem[0] Mem[6]
8 0 miss Mem[8] Mem[6]
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Associativity Example
▪ 2-way set associative (80% Miss)
Block Cache Hit/miss Cache content after access
address index Set 0 Set 1
0 0 miss Mem[0]
8 0 miss Mem[0] Mem[8]
0 0 hit Mem[0] Mem[8]
6 0 miss Mem[0] Mem[6]
8 0 miss Mem[8] Mem[6]
22 8
Tag
Index
Index V Tag Data V Tag Data V Tag Data V Tag Data
0
1
2
253
254
255
22 32
= = = =
4-to-1 multiplexor
Hit Data
Application
Application
Application
Application
Application
Application
Application
Application
Guest Operating System Guest Operating System
(Linux) (Window)
VMWare Hypervisor
Physical Hardware
Disk addresses
Virtual address
31 30 29 28 27 15 14 13 12 11 10 9 8 321 0
Virtual page number Page offset
20 12
Valid Physical page number
Page table
18
If 0 then page is not
present in memory
29 28 27 15 14 13 12 11 10 9 8 321 0
Physical page number Page offset
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Physical address
Mapping Pages to Storage
Virtual page
Page table
number
Physical page or
Physical memory
Valid disk address
1
1
1
1
0
1
1
0
1 Disk storage
1
0
1
1 0 1
1 1 1
1 1 1
Physical memory
1 0 1
0 0 0
1 0 1
Page table
Physical page
Valid Dirty Ref or disk address
1 0 1
1 0 0
1 0 0 Disk storage
1 0 1
0 0 0
1 0 1
1 0 1
0 0 0
1 1 1
1 1 1
0 0 0
1 1 1
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TLB Misses
▪ If page is in memory
▪ Load the PTE from memory and retry
▪ Could be handled in hardware
▪ Can get complex for more complicated page table
structures
▪ Or in software
▪ Raise a special exception, with optimized handler
▪ If page is not in memory (page fault)
▪ OS handles fetching the page and updating the page
table
▪ Then restart the faulting instruction
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TLB Miss Handler
▪ TLB miss indicates
▪ Page present, but PTE not in TLB
▪ Page not preset
▪ Must recognize TLB miss before destination
register overwritten
▪ Raise exception
▪ Handler copies PTE from memory to TLB
▪ Then restarts instruction
▪ If page not present, page fault will occur
physical address
Virtual page number Page offset
20 12
▪ Need to translate
Valid Dirty Tag Physical page number
TLB =
=
▪ Complications due to 18 8 4 2
aliasing 8
12 Data
physical address
=
Cache hit
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Memory Protection
▪ Different tasks can share parts of their virtual
address spaces
▪ But need to protect against errant access
▪ Requires OS assistance
▪ Hardware support for OS protection
▪ Privileged supervisor mode (aka kernel mode)
▪ Privileged instructions
▪ Page tables and other state information only
accessible in supervisor mode
▪ System call exception (e.g., syscall in MIPS)
Ready Ready
Multiple cycles
per access