Verilog forSequentialCircuits

Verilog for Seque a Circuits e og o Sequential C cu s

Sequential circuits are modeled in an always block Example of an implied memory element
The gated D latch

Verilog assumes the value of Q must be maintained if Clk is 0 and therefore synthesizes a latch

Verilog for D Flip-Flop e og o p op

Sensitivity list needs to specify clock edge, not just change in level
Can specify: posedge or negedge

Verilog will use flip-flops to synthesize circuits that are edge-triggered

Verilog for T a d J Flip-Flops e og o and JK p ops

Negative edge triggered versions
Also provides complemented outputs

Verilog Example e og a p e

treated as g = (x1 & x2) | x3

x3 x1 x2 Q D Q g

D Clock

Q Q

Verilog Example: Reversed O de e og a p e e e sed Order

Order matters inside an always block!

x3

Q Q

x1 x2 Clock

Q Q

Blocking Assignments oc g ss g e s
The order of statements inside an always block can affect the synthesized design
All previous examples use blocking assignments
Verilog evaluates the assignments in an always block in the order in which they are written

This can cause unexpected designs

D Clock D Q Q Q1

D
treated as Q2 = D since Q1 = D

Q Q

Q2

Non-Blocking Assignments o oc g ss g e s
What if you wanted a cascaded design for the previous example?
The assignment to Q2 should be from the previous Q1 Need both assignments to occur in parallel on the same clock edge
The LHS of a non-blocking assignment is updated after all g RHS values for all assignments have been evaluated

D Clock

Q Q

Q1

Q Q

Q2

non-blocking assignment

Non-Blocking Example o oc g a p e

Compare this to the earlier example using blocking assignments

x3

Q Q

x1 x2 Clock

Q Q

Verilog Cod g Tips e og Coding ps

Use blocking assignments when designing combinational logic
Non-blocking is OK when doing finite state machine (FSM) design ( be covered later) g (to )

Use non-blocking assignments when designing sequential logic (including for latches) Do not mix blocking and non blocking assignments non-blocking in the same always block
Use separate always blocks for this, if needed

Adding Asynchronous C ea dd g sy c o ous Clear

The sensitivity list cannot mix edge triggered and level sensitive events
Must make reset edge-triggered, but on a different edge

Sy c o ous Clear Synchronous C ea

The only change is in the sensitivity list
ResetN overrides the input

Verilog for N-Bit Register e og o eg s e

Verilog for N-Bit Register With Load e og o eg s e oad

Add a load enable input

Verilog for 4-Bit Shift Register e og o S eg s e

Parallel output

One technique: build a simple 2X1 MUX controlled D flip-flop

Q3 D Q Q

Q2 D Q Q

Q1 D Q Q

Q0 D Q Q

Serial Shift/Load input inp t

Parallel input

Clock

Provide parallel access (including load) and shift right

4-Bit Shift Register: Co S eg s e Continued ued

A hierarchical design mixing behavioral and structural styles

N-Bit Shift Register: Behavioral S y e S eg s e e a o a Style

N-Bit Up Cou e Counter

Provide an n-bit up counter with asynchronous clear and an enable control

N-Bit Up Cou e With Load Counter oad

Provide an n-bit up counter with asynchronous clear, an enable control, and parallel load

N-Bit Up/Down Cou e With Load Up/ o Counter oad

Alternate Version o U/ Cou e e a e e s o of U/D Counter

blocking assignments are executed before non-blocking ones b f bl ki

Good Cod g S y e Coding Style

As a matter of good coding style
Do not mix blocking and non-blocking assignments in the same always block
It may work, but you may confuse y y y y yourself!

Use separate always blocks when you need both types Repeating earlier rules
Use blocking assignments for combinational logic Use non-blocking assignments for sequential logic, and latches

Best Version of U/ Cou e es e s o o U/D Counter

This style separates blocking and non-blocking non blocking assignments into separate always blocks