FPGA IMPLEMENTATION OF 8-BIT VEDIC DIVIDER

A Major Project report submitted to

JAWAHARLAL NEHRU TECHNOLOGICAL

UNIVERSITY
ANANTHAPUR, ANANTHAPURAMU
In partial fulfillment of the requirement for the award of degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted by
C. GUNASREE (209X1A0410)

CB. KODANDA RAMI REDDY (209X1A0437)

G. POOJITHA (209X1A0415)

Under the esteemed guidance of

Smt T.SWATI, M.Tech,(Ph.D)

Assistant Professor, ECE Department

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

G. PULLA REDDY ENGINEERING COLLEGE (AUTONOMOUS):

KURNOOL (Accredited by NBA of AICTE and NAAC of UGC with A

grade)

(AFFILIATED TO JNTUA,

ANANTHAPURAMU) 2023-

2024
 G. PULLA REDDY ENGINEERING COLLEGE (Autonomous), Kurnool

(Accredited by NBA of AICTE and NAAC of UGC with A grade)

(Affiliated to JNTUA, Anantapuramu) Kurnool-518007

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE
This is to certify that the major project work entitled

FPGA IMPLEMENTATION OF 8-BIT VEDIC DIVIDER

is the bonafide record of work carried out by

C.Gunasree 209X1A0410

CB.Kodanda Rami Reddy 209X1A0437

G.Poojitha 209X1A0415
Under my guidance and supervision in fulfillment of the requirements for the
award of degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING

PROJECT GUIDE HEAD OF THE DEPARTMENT

Smt T.SWATI, M.Tech,(Ph.D) Dr. S. NAGARAJA RAO,M.Tech, Ph.D, MISTE

Assistant Professor, Professor and Head of the Department,
Department of ECE, Department of ECE,
G. Pulla Reddy Engineering College, G. Pulla Reddy Engineering College,
(Autonomous), Kurnool. (Autonomous), Kurnool.
 AKNOWLEDGEMENT
We express our sincere thanks to our principal Dr. B. Sreenivasa Reddy garu, for
providing the facilities extended to work on the project during the project sessions.

We would like to express our sincere thanks to Dr. S. Nagaraja Rao garu, Head of the
Electronics and Communication Engineering Department, G. Pulla Reddy Engineering College
for providing requisite facilities and helping us providing such a good environment.

We are extremely grateful to our project guide, Smt T. Swati, Assistant Professor, ECE
Department, G. Pulla Reddy Engineering College, who has been a source of inspiration
throughout the course and for extending all support to us in the form of the technical literature
and excellent guidance.

We also extend our sincere thanks to the entire faculty and staff members of ECE
Department, who have been a source of information throughout the course and for extending all
support to us in the form of technical literature and excellent guidance.
 DECLARATION

We here by declare that the major project titled “FPGA IMPLEMENTATION OF

8-BIT VEDIC DIVIDER” is an authenticated work carried out by us as the students of
G. PULLA REDDY ENGINEERING COLLEGE (Autonomous), Kurnool, during 2023-2024
and has not been submitted elsewhere for the award of any degree or diploma in part or in full to
any institute.

C.GUNASREE
(209X1A0410)

CB. KODANDA RAMI REDDY

(209X1A0414)

G. POOJITHA
(209X1A0415)
 ABSTRACT

In this project, we present a highly efficient FPGA implementation of 8-bit Vedic

divider. The implementation is realized using the Verilog Hardware Description Language
(HDL). The 8-bit Vedic divider employing the Paravartya method is a unique computational
architecture inspired by ancient Vedic mathematical techniques. In this system, the
Paravartya method, a Vedic sutra-based approach for division, is adapted for use in an 8-bit
digital environment. The core idea of the Paravartya method involves repeated subtractions
and shifting operations to efficiently arrive at the quotient. This method is particularly well-
suited for binary representation, aligning with the digital nature of modern computing
systems.

The architecture of the 8-bit Vedic divider integrates the Paravartya

method through a combination of logic gates and shift registers. The input numbers are
processed through a series of stages, each mimicking the steps of the Paravartya method.
Subtraction and shifting operations are executed in a parallel fashion, optimizing the division
process. The utilization of Vedic sutras not only adds a historical and cultural dimension to
the design but also enhances the efficiency of the division process.
.
 CONTENTS PAGE NO
1. INTRODUCTION....................................................................................................1
1.1 BACKGROUND...............................................................................................4
1.2 PROBLEM STATEMENT...............................................................................4
1.3 MAIN OBJECTIVES........................................................................................5
2. LITERATURE REVIEW........................................................................................6
2.1 REVIEW OF RELATED LITERATURE........................................................6
3. INTRODUCTION TO VLSI...................................................................................9
3.1 PARAMETERS FOCUSED ON VLSI:...........................................................9
3.2 VLSI DESIGN FLOW....................................................................................10
3.3 BASICS OF FPGA AND ARCHITECTURE................................................12
3.4 FPGA ARCHITECTURE...............................................................................13
3.5 NEXYS A7 FPGA..........................................................................................15
4. PROJECT METHODOLOGY.............................................................................16
4.1 PARAVATYA SUTRA 8-BIT DIVISION ALGORITHM...........................16
4.2 FLOW CHART OF VEDIC DIVISION FOR PARAVARTYA METHOD: 18
4.3 VERILOG HDL..............................................................................................19
5. SOFTWARE TOOL..............................................................................................21
6. SIMULATION RESULTS....................................................................................33
6.1 DATA FLOW OF A DIAGRAM...................................................................33
6.2 DEVICE AND ROUTING.............................................................................34
6.3 SCHEMATIC OF DIVIDER..........................................................................35
6.4 PACKAGE OF FPGA.....................................................................................36
6.5: SIMULATED RESULTS..............................................................................39
6.6 RESULTS ON FPGA BOARD......................................................................40
6.7 COMPARISON OF RESULTS......................................................................41
7. ADVANTAGES & APPLICATIONS..................................................................44
7.1ADVANTAGES..............................................................................................44
7.2 APPLICATIONS............................................................................................45
8. CONCLUSION AND FUTURE SCOPE.............................................................46
8.1 CONCLUSION...............................................................................................46
8.2 FUTURE SCOPE:...........................................................................................46
9.REFERENCES........................................................................................................48
 Figure Page no.

Figure 1 Design Flow.......................................................................................................13

Figure 2 Field Programmable Gate Array........................................................................16
Figure 3 FPGA Architecture............................................................................................17
Figure 4 FPGA Logic Block............................................................................................17
Figure 5 Nexys A7 Feature Callout.................................................................................18
Figure 6 Flow Chart.........................................................................................................23
Figure 7 Vivado Start-Up Window..................................................................................28
Figure 8 Create Project Dialog.........................................................................................29
Figure 9 Enter Project Name...........................................................................................29
Figure 10 Select Zynq 7000 Part......................................................................................30
Figure 11 Create Project Summary..................................................................................31
Figure 12 Vivado Project Window..................................................................................31
Figure 13 Add Design Sources........................................................................................32
Figure 14 Add or create design sources using Add Source Dialog.................................32
Figure 15 Creation of Design Source File.......................................................................33
Figure 16 vedic appears in design sources.......................................................................33
Figure 17 Add Source to Design Constraints...................................................................34
Figure 18 Add or create design constraints using Add Source Dialog............................34
Figure 19 Creation of Constraints File............................................................................35
Figure 20 Double Click to Edit mba1.xdc.......................................................................35
Figure 21 Start Synthesis process and monitor the synthesis log....................................36
Figure 22 Start Implementation process and monitor the implementation log................36
Figure 23 Generate Bitstream..........................................................................................37
Figure 24 Powered on Blackboard...................................................................................38
Figure 25 Data Flow of Diagram.....................................................................................40
Figure 26 Device and routing inside it.............................................................................42
Figure 27 Complete schematic of divider........................................................................43
Figure 28 Package of FPGA............................................................................................44
Figure 29 Power Analysis................................................................................................46
Figure 30 Simulated Results............................................................................................47
Figure 31 Results on FPGA Board..................................................................................48
Figure 32Power usage of Long division..........................................................................50
Figure 33 Power usage of Vedic division........................................................................50

Table Page no

Table 1 Slice Logic..........................................................................................................45

Table 2 IO and GT specific..............................................................................................45
Table 3 Primitives............................................................................................................45
Table 4 Comparision of vedic division and long division...............................................49
 FPGA IMPLEMETATION OF 8-BIT VEDIC DIVIDER

1. INTRODUCTION

Dividers play a crucial role in modern technology across various

applications. In digital signal processing, dividers are fundamental for tasks like
frequency scaling and signal modulation, ensuring precise and efficient computations.
In microprocessor architectures, dividers contribute to arithmetic units, enabling the
execution of complex mathematical operations essential for algorithmic
implementations. Additionally, dividers are vital in communication systems for symbol
rate adjustments and data synchronization.

In financial technology, dividers facilitate accurate calculations for interest rates,

investment returns, and financial ratios. They are integral components in encryption
algorithms, contributing to secure cryptographic operations. Dividers also find
application in scientific simulations and numerical modeling, aiding researchers in
solving complex equations and simulating real-world scenarios.
Furthermore, dividers are essential in everyday technologies, from computing devices to
multimedia systems, contributing to tasks such as image processing, multimedia
compression, and data analysis. Their versatility makes dividers indispensable in
optimizing resource allocation, ensuring efficient data processing, and advancing
computational capabilities in the ever-evolving landscape of modern technology.
There are several methods or processes for performing division, each suited to different
scenarios or preferences. Here are some common types of division processes:
Long Division:
Long division is a traditional and widely taught method for dividing large numbers. It
involves a step-by-step process of dividing the digits of the dividend by the divisor,
determining the quotient digit by digit, and bringing down the next digit until the entire
dividend is divided.
Short Division:
Short division is a more compact and quicker method suitable for dividing smaller
numbers. It is similar to long division but involves fewer steps, making it more efficient
for simple calculations.
Synthetic Division:
Synthetic division is a specialized method for dividing polynomials by linear divisors. It

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is a shorthand technique that simplifies the process, particularly when dividing by linear
factors.
Bus Stop Method (Chunking):
The bus stop method, also known as chunking, is an informal division method that
involves breaking down the dividend into manageable "chunks" or groups. This method
is often used for mental calculations or when an exact quotient is not required.
Partial Quotients:
Partial quotients is a division method that involves breaking down the division problem
into a series of easier steps. Each step involves finding a partial quotient until the entire
division is complete.
Repeated Subtraction:
Repeated subtraction is a basic method where the divisor is subtracted repeatedly from
the dividend until the result is less than the divisor. The number of subtractions
represents the quotient.
Decimal Division:
The decimal division is a standard process for dividing numbers with decimal points. It
involves placing the decimal point in the quotient directly above the decimal point in
the dividend and proceeding with division as usual.
Matrix Division:
In linear algebra, matrix division involves finding the inverse of one matrix and then
multiplying it by another matrix. This is a common operation when solving systems of
linear equations.
Binary Division:
Binary division is used in computer science and digital electronics for dividing binary
numbers. The process is like decimal division but involves the binary number system.
Vedic Division (Paravartya Sutra):
As mentioned earlier, the Vedic division is an alternative division algorithm inspired by
ancient Indian mathematical techniques. The Paravartya Sutra is a specific Vedic
division method known for its speed and efficiency.
The choice of division method often depends on the context, the size and nature of the
numbers involved, and personal preference or familiarity with a particular technique.

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Different methods may be preferred for mental calculations, manual computations, or

implementation in algorithms and computer programs.
Vedic division, based on the ancient Indian mathematical technique of the Paravartya
Sutra, stands out due to its unique features and advantages:
Efficiency and Speed:
Vedic division is known for its speed and efficiency. The Paravartya Sutra provides a
method that allows for parallel computation, reducing the number of sequential steps
compared to traditional long division. This can result in faster division operations,
making it appealing for certain applications.
Simplicity and Ease of Learning:
The Vedic division method is often considered more intuitive and easier to learn than
some other division algorithms. Its simplicity makes it accessible to a wide range of
learners, including students and practitioners in various fields.
Parallelism in Hardware Implementation:
In the context of hardware implementations, such as FPGA designs, the parallel nature
of Vedic division aligns well with the parallel capabilities of these platforms. This can
lead to efficient use of hardware resources and improved performance in terms of speed
and throughput.
Adaptability to Various Number Systems:
The Vedic division algorithm is adaptable to different number systems, including signed
numbers and binary numbers. This versatility makes it applicable in diverse domains,
including digital signal processing and computer arithmetic.
Resource Optimization in Hardware Design:
When implemented in hardware, the Vedic division algorithm can potentially lead to
resource-efficient designs. This is crucial in applications where minimizing hardware
utilization is a key consideration, such as in embedded systems or resource-constrained
environments.
Cultural and Historical Significance:
The use of Vedic mathematics connects the algorithm to a rich historical and cultural
heritage. Some find value in exploring and preserving ancient mathematical techniques,
and the Vedic division method represents a unique contribution to this body of
knowledge.

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While Vedic division offers advantages, its applicability may depend on specific use
cases and the desired trade-offs between speed, complexity, and ease of
implementation. In certain scenarios, such as FPGA-based designs, the unique
characteristics of Vedic division can make it a compelling choice for efficient
arithmetic computation.

1.1 BACKGROUND

In the ever-evolving landscape of digital signal processing (DSP), the relentless pursuit
of computational efficiency stands as a defining challenge. This pursuit is particularly
pronounced in applications such as communication systems, image processing, and
cryptography, where the demand for accelerated arithmetic operations has become a
hallmark of technological progress. Among these fundamental arithmetic operations,
division holds a critical position, serving as a linchpin for algorithms and computations
that underpin the functionality of diverse digital systems.

Traditional division algorithms, while conceptually robust, are often characterized by

inherent trade-offs in terms of speed, power consumption, and resource utilization. The
necessity for addressing these challenges has led to a paradigm shift in the exploration
of unconventional approaches to division, with an emphasis on speed and efficiency. In
this context, the Vedic mathematics system emerges as a beacon of promise, offering
not only simplicity but also the potential for significantly enhanced computational
speed. The 8-Vedic Divider, a central focus of this project, represents a sophisticated
and novel algorithmic approach to division. By integrating the principles of Vedic
mathematics, this divider seeks to redefine the landscape of digital arithmetic,
particularly when implemented on the versatile platform of Field-Programmable Gate
Arrays (FPGAs). The inherent parallelism and configurability of FPGAs make them an
ideal canvas for crafting specialized arithmetic units, and the 8-Vedic Divider is poised
to harness these features to unlock unprecedented levels of division performance.

1.2 PROBLEM STATEMENT

In the realm of digital signal processing and arithmetic computation, there exists a
demand for efficient and high-performance division operations. Traditional division
algorithms may not always meet the criteria of speed and resource optimization required

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for modern applications. This project addresses the need for an optimized hardware
implementation of an 8-bit Vedic divider using the Paravartya Sutra.
The goal is to design and implement an FPGA-based solution that leverages the
parallelism inherent in Vedic division, providing a faster and resource-efficient
alternative to conventional division methods. The project involves the development of a
robust 8-bit Vedic divider using Verilog Hardware Description Language (HDL) for
synthesis on FPGA platforms. The project aims to surpass the performance metrics of
sequential division methods while demonstrating the versatility and adaptability of the
Vedic approach in FPGA-based systems.

1.3 MAIN OBJECTIVES

The primary objective of the FPGA implementation of an 8-bit Vedic divider is to

develop a hardware solution that harnesses the benefits of Vedic mathematics for
division operations. The key aims include enhancing the speed of 8-bit division through
parallel processing, optimizing FPGA resources to ensure efficiency, adapting the
algorithm for 8-bit numbers, and validating correctness and precision through
simulations and hardware testing. The implementation is expected to showcase
versatility by demonstrating applicability in digital signal processing and multimedia
systems, emphasizing the rapid and resource-efficient nature of the 8-bit Vedic division.
Additionally, the project intends to conduct a comparative analysis against conventional
sequential division methods, highlighting the FPGA-based Vedic divider's superior
speed and resource efficiency. Using the Verilog Hardware Description Language, the
project aims to synthesize and optimize the design for the targeted FPGA hardware,
ultimately contributing valuable insights to advance efficient arithmetic computation in
FPGA-based systems.

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2. LITERATURE REVIEW

2.1 REVIEW OF RELATED LITERATURE

1. In the year 2017, S. BhanuTej proposed the 8-bit Modified Vedic Paravartya
Divider with quotient in fractions. Overall, the paper presents a new and efficient
architecture for the Paravartya division that is well-suited for high-speed digital signal
processing applications. A modified Vedic Paravartya divider that can compute the
quotient in fractions. The proposed divider is implemented in a 8-bit configuration and
shows significant improvements in speed and area over conventional dividers. The key
contributions of the paper are A new architecture for Paravartya division that generates
8 partial quotient terms in parallel in each stage. A reduction in delay of 4.5ns compared
to the conventional serial implementation of the Paravartya sutra. A 62% reduction in
delay when compared with existing dividers like SRT, Newton-Raphson, and Nikhilam
dividers that produce quotient and remainder. The proposed divider is a promising
candidate for high-speed digital signal processing applications.

2. In the paper “Verilog implementation of double precision floating point division

using Vedic Paravartya sutra" by Molleti Rajani and P. Narayana Murthy, published in
IEEE Xplore. The paper discusses the related work on Vedic mathematics, floating-
point division algorithms, and FPGA implementations. The authors mention that Vedic
mathematics provides alternative algorithms for arithmetic operations that are often
more efficient than traditional algorithms. They also mention that the Paravartya sutra is
one such algorithm for division. Additionally, they discuss various FPGA-based
implementations of floating-point dividers and highlight the advantages of using Vedic
mathematics for this purpose. Overall, the paper presents a novel and efficient Verilog
implementation of a double-precision floating-point divider based on the Paravartya
sutra. The proposed divider demonstrates significant improvements in terms of area,
power consumption, and speed compared to traditional division algorithms, making it a
valuable contribution to the field of FPGA-based arithmetic design.

3. The paper “8-bit Modified Vedic Paravartya Divider with quotient in fractions" by
M. K. Sanju Vikasini and Binsu J. Kailath, published in IEEE Xplore. The paper
discusses the related work on Vedic mathematics and division algorithms. The authors
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mention that Vedic mathematics provides alternative algorithms for arithmetic

operations that are often more efficient than traditional algorithms. They also mention
that the Paravartya sutra is one such algorithm for division. Overall, the paper presents a
new and efficient architecture for the Paravartya division that is well-suited for high-
speed digital signal processing applications.

4. In the paper “Vedic Divider: Novel Architecture (ASIC) For High-Speed VLSI
Applications" by Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, and Anup
Dandapat presents a novel divider architecture based on Vedic mathematics, an ancient
Indian methodology with unique computational techniques. The proposed architecture
significantly reduces propagation delay and dynamic power consumption by eliminating
unnecessary recursion through Vedic division methodology. The functionality of the
circuits was verified, and performance parameters such as propagation delay and
dynamic power consumption were calculated using SPICE Spectre with 90nm CMOS
technology. The results demonstrate that the proposed architecture achieves a 45%
reduction in propagation delay and a 30% reduction in power consumption compared to
conventional divider architectures.

5. In the paper “High-Speed Vedic Divider Designs Using Carry Save Adders" by S. N.
Behera and S. Majumdar (2008). This sounds like an interesting contribution to the field
of Vedic divider designs, particularly focusing on achieving high-speed performance
using carry save adders. The use of carry save adders is significant in digital circuit
design, and it's intriguing to see their application in the context of Vedic dividers. The
reduction in propagation delay is a crucial factor in enhancing the speed and efficiency
of divider circuits, which can be particularly valuable in various applications, including
VLSI design and other areas requiring fast arithmetic operations. If you have access to
the paper, you may want to explore the details of the proposed design, the methodology
followed, and the experimental results that demonstrate the reduction in propagation
delay. Additionally, check for any comparisons with conventional divider designs and
discussions on the advantages and limitations of the proposed approach.

6. The paper "Low power divider using Vedic mathematics" by Dalal Rutwik Kishor
and V.S. Kanchana Bhaaskaran: Dividers are essential components in digital signal

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processing (DSP) systems. However, conventional dividers are often power-hungry and
time-consuming. This paper proposes a low-power and fast divider architecture based
on the ancient Indian Vedic mathematics. The proposed architecture utilizes Vedic
sutras (formulae) to reduce the number of multiplication operations required for
division. This results in significant power savings and improved speed compared to
conventional dividers. The proposed Vedic divider architecture achieves up to 52.93%
reduction in power consumption compared to conventional dividers. The proposed
divider is also faster than conventional dividers, with a reduction in latency of up to
40%. The proposed divider is implemented using industry-standard Cadence® software
using a 45nm technology library. The design has been validated on the FPGA Spartan-
3E kit.

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3. INTRODUCTION TO VLSI
VLSI (Very Large-Scale Integration) is a technology that involves packing thousands to
millions of transistors onto a single chip. It enables the creation of complex integrated
circuits, fostering the development of powerful electronic systems. VLSI design follows
a hierarchical approach, breaking down systems into manageable modules. This
technology encompasses both digital and analog components, with digital design
involving logic gates and analog design dealing with continuous signals. Key
parameters in VLSI projects include power consumption, performance, area utilization,
timing analysis, reliability, and cost. Achieving a balance between these factors is
crucial for economic viability. Testability is essential for manufacturing yield, with
built-in self-test methodologies commonly employed. Designs must be manufactured
within chosen semiconductor processes, considering variations and yield optimization.
Security is increasingly relevant, prompting considerations for hardware-level
protection. Economic and environmental impact, as well as sustainability, are emerging
concerns in VLSI projects. Overall, VLSI integrates diverse principles to create
efficient, high-performance, and cost-effective electronic systems.

3.1 PARAMETERS FOCUSED ON VLSI:

1. Power Consumption:
Power efficiency is a critical parameter in VLSI design. Lower power consumption is
desirable for both battery-powered devices and to reduce heat dissipation.
2. Performance:
Performance is measured by factors such as clock frequency, throughput, and response
time. VLSI designs aim to achieve high performance while meeting other constraints.
3. Area Utilization:
Efficient use of silicon area is essential. This involves minimizing the physical size of
the chip while maximizing the number of functional components.
4. Timing Analysis:
Timing analysis ensures that signals within the circuit meet setup and hold time
requirements. It involves considering the propagation delays of various components.

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5. Reliability and Robustness:

VLSI projects need to account for the reliability and robustness of the design under
various operating conditions, including temperature and voltage variations.
6. Cost:
Cost is a crucial factor, and VLSI projects aim to optimize the balance between
performance, features, and production cost.

3.2 VLSI DESIGN FLOW

VLSI Design is an iterative cycle. Designing a VLSI Chip includes a few problems such
as functional design, logic design, circuit design, and physical design. The design is
verified for accuracy by the process of simulation. If any design errors are found at any
stage of verification, at least one of the previous design steps must be repeated to correct
the error during the process of designing.

Figure 1 Design Flow

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1. System specification: The objective of the desired final product is written in this
step. During system specification, the designated cost of the system, its performance,
architecture, and how the system will communicate with the external world are to be
determined. During this step, the design specification should be provided by the users or
clients.
2. Architectural design: The basic architecture of the desired design must meet the
system specifications of the desired design. The architecture of the desired design is
decided and the layout for the same is designed by design engineers. Architectural
design includes the integration of analog and mixed-signal blocks, memory
management, internal and external communication, power requirements, and choice of
process technology and layer stacks.
3.Functional design or Behavioral design: It consists of refining the design
specification of the desired design in order to design the functional behavior of the
desired system. The main objective of this is to generate design a high-performance
architectural design within the cost requirements posed by the specifications.
4. Logic Design: In this step, the structure of the desired design is added to the
behavioral representation of the desired design. The main specifications to be
considered for logic design are logic minimization, performance enhancement, and
testability. Logic design must also consider the problems associated with test vector
generation, error detection, and error correction. Many logic synthesis tools have been
developed for the automation of the process of logic design.
5. Circuit Design: In this step, the logic blocks of the desired design are replaced by the
electronic circuits, which are consists of electronic devices such as resistors, capacitors,
and transistors. Circuit simulation of the desired design is done at this stage, in order to
verify the timing behavior of the desired system. Kirchhoff’s laws are used to know the
behavior of the electronic circuit in terms of node voltages and branch circuits. The
result of integrodifferential equations is then solved in discrete- time. SPICE is a well-
known program for circuit simulation.
6. Physical Design: In this step, the actual layout of the desired system is done, where
all the components will be placed in the circuit and all these components are
interconnected. The actual layout of the desired system can affect the area, correctness,
and performance of the final desired product. The correctness of the chip is also
controlled by the physical design. A circuit design that passes the test of a circuit
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a simulator may be faulty after it has been packaged. This is because of geometric
design rule errors. These design rules must be followed to ensure the correctness of the
chip fabrication. Errors such as short circuits, open circuits, open channels, etc. may
result if the design rules are not respected.
7. Fabrication: After the actual layout and verification of the desired design, the design
is sent for manufacturing. The handoff of the desired design to the manufacturing
process is called tape out. The generation of data for manufacturing is referred to as
streaming out. The desired design is onto the different layers of the design using the
photolithographic process. ICs are manufactured on round silicon wafers with a
diameter from 200mm to 300mm, these ICs are then tested and are marked as either
functional or defective ICs.
8. Packaging and Testing: After the fabrication of the desired design, functional chips
are then packed. Packaging is configured early in the desired design process and the
application along with the cost and form factor requirements. Packaged types may
include Dual In-Line Packaged (DIPs), Pin Grid Array (PGAs), and Ball Grid Arrays
(BGAs). After a die is positioned in the package cavity, its pins are connected to the
pins of the package, e.g., with wire bonding or more solid bumps (flip-chip). The
package of the desired design is then sealed and then sent to the end-users or clients.

3.3 BASICS OF FPGA AND ARCHITECTURE

The term FPGA stands for Field Programmable Gate Array and, it is a type of
semiconductor logic chip that can be programmed to become almost any kind of system
or digital circuit, like PLDs. PLDS are limited to hundreds of gates, but FPGAs support
thousands of gates. The configuration of the FPGA architecture is generally specified
using a language, i.e., HDL (Hardware Description language)

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Figure 2 Field Programmable Gate Array

which is like the one used for an ASIC (Application Specific Integrated Circuit).
FPGAs can provide several advantages over a fixed-function ASIC technology such as
standard cells. Normally, ASICs takes months to manufacture and the cost of them will
be thousands of dollars to obtain the device. But FPGAs are fabricated in less than a
second, the cost will be from a few dollars to a thousand dollars. The flexible nature of
the FPGA comes at a significant cost in area, power consumption, and delay. When
compared to a standard cell ASIC, an FPGA requires 20 to 35 times more area, and the
speed’s performance will be 3 to 4 times slower than the ASIC. This article describes
FPGA basics and FPGA architecture modules that include I/O pad, logic blocks, and
switch matrix. FPGAs are some of the new trending areas of VLSI. Therefore, these are
used in VLSI-based projects for electronic engineering students.

3.4 FPGA ARCHITECTURE

The general FPGA architecture consists of three types of modules. They are I/O blocks
or Pads, Switch Matrix/ Interconnection Wires, and Configurable logic blocks (CLB).
The basic FPGA architecture has two dimensional arrays of logic blocks with a means
for a user to arrange the interconnection between the logic blocks. The functions of an
FPGA architecture module are discussed below:
1. CLB (Configurable Logic Block) includes digital logic, inputs, and outputs. It
implements the user logic.
2. Interconnects provide direction between the logic blocks to implement the user logic.
3. Depending on the logic, the switch matrix provides switching between interconnects.
4. I/O Pads used for the outside world to communicate with different applications.

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Figure 3 FPGA Architecture

Figure 4 FPGA Logic Block

Logic Block contains MUX (Multiplexer), D flip flop, and LUT. LUT implements the
combinational logical functions; the MUX is used for selection logic, and D flip flop
stores the output of the LUT.
The basic building block of the FPGA is the Look Up Table-based function generator.
The number of inputs to the LUT varies from 3,4,6, and even 8 after experiments. Now,
we have adaptive LUTs that provide two outputs per single LUT with the
implementation of two function generators.
Xilinx Virtex-5 is the most popular FPGA, that contains a Look up Table (LUT) which
relates to MUX, and a flip flop as discussed above. Present FPGA consists of

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about hundreds or thousands of configurable logic blocks. For configuring the FPGA,
model sim, Xilinx Vivado, and Xilinx ISE software are used to generate a bitstream file
and for development. In our project, we are using the “Nexys A7 FPGA” board.

3.5 NEXYS A7 FPGA

The Nexys A7 board is a complete, ready-to-use digital circuit development platform

based on the latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx®.
With its large, high-capacity FPGA, generous external memories, and collection of
USB, Ethernet, and other ports, the Nexys A7 can host designs ranging from
introductory combinational circuits to powerful embedded processors. Several built-in
peripherals, including an accelerometer, temperature sensor, MEMs digital microphone,
a speaker amplifier, and several I/O devices allow the Nexys A7 to be used for a wide
range of designs without needing any other components.

Figure 5 Nexys A7 Feature Callout

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4. PROJECT METHODOLOGY

In this project, we harness the power of the Paravartya Sutra, a venerable

Vedic mathematical principle, to facilitate division operations within the Xilinx Vivado
software ecosystem. This ancient technique enables efficient and accurate division
without reliance on clock cycles, enhancing computational efficiency and algorithmic
elegance.

4.1 PARAVATYA SUTRA 8-BIT DIVISION ALGORITHM

1. The 8-bit Vedic Divider was implemented using the Paravartya Sutra as follows:
2. The 8-bit dividend and divisor were taken.
3. The quotient and remainder were initialized as 0.
4. Starting from the leftmost bit of the dividend, processing was initiated.
5. If the current quotient plus the divisor was less than or equal to 255, the divisor was
added to the quotient, and the corresponding quotient bit was set to 1; otherwise, it
was set to 0.
6. The dividend was shifted left by 1 bit.
7. Steps 3-5 were repeated until all bits of the dividend were processed.
8. The resulting quotient and remainder were obtained, representing the division result.
9. This approach exemplified the application of the Paravartya Sutra, simplifying
division through the consideration of complementary values.
The distinction between Vedic division and conventional division lies in the
methodologies and techniques employed during the division process. Vedic division,
inspired by the ancient Indian mathematical system known as Vedic mathematics, often
differs from traditional long-division methods in its approach and efficiency. Let's
explore the differences between Vedic and normal division in a passage:
Vedic Division vs. Conventional Division: Unveiling Distinctive Approaches
Division, a fundamental arithmetic operation, serves as the cornerstone of mathematical
computations. In the realm of division, two distinct methodologies, Vedic division, and
conventional division, offer contrasting approaches to the same mathematical task.

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Vedic Division: A Blend of Simplicity and Efficiency

Vedic division draws its roots from the ancient Indian mathematical system known as
Vedic mathematics. Characterized by its succinct sutras or aphorisms, Vedic
mathematics encompasses a range of techniques designed to streamline mathematical
operations. Vedic division is distinguished by its emphasis on simplicity and efficiency.

The hallmark of Vedic division lies in its sutras, or specific formulae, which guide the
division process. One such sutra is the Paravartya method, a technique that involves
successive subtractions and shifting operations. The elegance of Vedic division is
manifest in its ability to parallelize these operations, minimizing the computational
steps required to arrive at the quotient. This parallelism is particularly advantageous in
digital systems, where efficiency is paramount.

Conventional Division: The Time-Tested Algorithmic Approach

Conventional division, on the other hand, encompasses the familiar long-division

method taught in standard mathematical education. This method relies on a step-by-step
algorithmic process where each digit of the divisor is successively divided into the
dividend. While this approach is well-established and widely understood, it can be more
time-consuming and involves a larger number of steps compared to Vedic division.

In traditional long division, the focus is on a systematic reduction of the dividend

through sequential subtraction and shifting. The algorithmic nature of this method
provides a clear and methodical way to compute the quotient and remainder, but it may
not always optimize the computational process.

Comparative Analysis: Efficiency and Versatility

The key difference between Vedic division and conventional division lies in their
approaches to computational efficiency. Vedic division, with its emphasis on
parallelism and streamlined processes, is often more adept at minimizing computational
steps, making it particularly advantageous in digital and algorithmic contexts.
Conventional division, while tried-and-true, may involve a more step-intensive process.
In conclusion, the choice between Vedic division and conventional division depends

on the specific context and requirements of the computation at hand. While Vedic
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division introduces an innovative and efficient approach inspired by ancient

mathematical wisdom, conventional division remains a robust and universally
recognized method in mathematical education and practice.

4.2 FLOW CHART OF VEDIC DIVISION FOR PARAVARTYA METHOD:

Figure 6 Flow Chart

EXPLANATION OF FLOWCHART:
Operands: we took two 8-bit operands “Divisor” [A] and “Dividend” [B]
Inverter: Here inverter is used to complement the divisor except for MSB (Most
significant bit)
Multiplier: Multiplier is used to multiply the bits of dividend and complement bits of
divisor.
Adder: Adder adds the multiplier result and dividend which gives partial remainder and
quotient.
Incrementer: Incrementer is used to calculate the number of terms in the quotient,
initially it is set to 0.
Condition Check: If the partial remainder is greater than the divisor then the process
repeats until partial remainder is less than the divisor.
Result: Result consists of two parts Quotient and Remainder. Quotient is number of
terms the process is repeated and the remaining part is Remainder.

EXAMPLE: 1

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Assume input: dividend = 13 and divisor = 12

From the above example, To find out the quotient term, the formula = Number of terms in
dividend –
Number of terms in divisor + 1
So, quotient =2–2+1
=1
And remainder = 1
output: Quotient = 01 & Remainder = 01

EXAMPLE: 2

Assume input: dividend = 10 and divisor = 10

From the above example, To find out the quotient term, the formula = Number of terms
in dividend – Number of terms in divisor + 1
So, quotient =2–2+1
=1
And remainder = 1
Output: Quotient = 01 & Remainder = 00

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4.3 VERILOG HDL

Hardware Description Language (HDL) is a specialized programming language used for

designing and describing digital circuits and systems. It enables engineers to model
electronic systems at various abstraction levels, specifying both the behavior and
structure of hardware. HDLs, like Verilog and VHDL, provide a means to express logic
circuits, sequential operations, and complex systems in a format understandable to both
humans and synthesis tools. These languages support modular design, allowing
designers to break down complex systems into manageable components. HDLs are
crucial in the design and verification process, aiding in simulation, testing, and synthesis
for implementation on FPGAs or ASICs. HDLs capture the parallelism inherent in
digital systems, facilitating the representation of concurrent operations. Timing and
delay characteristics can be modeled, ensuring designs meet performance requirements.
HDLs also play a vital role in the creation of testbenches for validating the functionality
of digital circuits. Their flexibility and scalability make them essential tools in the field
of digital hardware design.
Verilog Hardware Description Language (HDL) is a powerful language used for the
design and verification of digital circuits and systems. Verilog is widely employed in
the field of Very Large-Scale Integration (VLSI) and digital system design.
1. Behavioral Modeling in Verilog:
Behavioral modeling in Verilog focuses on describing the functionality and operation of
a digital circuit or system. It employs constructs like always blocks and initial blocks to
represent sequential and concurrent behaviors. Behavioral modeling is primarily
concerned with what the circuit does rather than how it is implemented at the structural
level.
For example:
module Behavioral_Model (input a, b, output y);
always @ (a or b)
y = a & b;
endmodule
2. Structural Modeling in Verilog:
Structural modeling in Verilog involves describing a digital system by specifying the
interconnection of its components. This includes instances of logic gates, multiplexers,

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flip-flops, and other predefined modules. The structural approach is akin to a schematic
representation of the circuit. An example of structural modeling is as follows:
For example:
module Structural_Model (input a, b, output y);
and gate1(a, b, y);
endmodule

3. Data Flow Modeling in Verilog:

Data flow modeling in Verilog is a style that emphasizes how data flows through the
circuit. It involves the use of continuous assignment statements using the assigned
keyword. This style is well-suited for describing combinational logic. An example of
data flow modeling is:
For example:
module DataFlow_Model (input a, b, output y);
assign y = a & b;
endmodule
In the above three examples, the output y is continuously assigned the result of the
bitwise AND operation between inputs a and b.
Verilog HDL provides a versatile environment for modeling digital systems. Behavioral
modeling captures system functionality, structural modeling focuses on component
interconnection and data flow modeling emphasizes the flow of data through the circuit.
Engineers often use a combination of these modeling styles to comprehensively
describe and implement complex digital designs.

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5. SOFTWARE TOOL
Vivado, developed by Xilinx, is a robust and integrated design environment for
FPGA and SoC development. Serving as a comprehensive IDE, it facilitates hardware
description, synthesis, implementation, and debugging. Supporting a broad range of
Xilinx devices, Vivado enables designers to optimize their designs for specific FPGA
and SoC architectures. With high-level design entry options such as Verilog, VHDL,
and graphical block diagram entry through IP Integrator, it accommodates diverse
design methodologies. The tool incorporates an extensive IP library, streamlining the
integration of intellectual property blocks into designs to reduce development time.
Vivado's synthesis and optimization capabilities enhance performance, area utilization,
and power efficiency. Through its place-and-route tools, it maps designs onto FPGA
resources, optimizing for timing and meeting specified constraints.
STEP 1: CREATE A VIVADO PROJECT
1. Start Vivado
In Windows, you can start Vivado by clicking the shortcut on the desktop. After Vivado
is started, the window should look similar to the picture in Figure 1.

Figure 7 Vivado Start-Up Window

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2. Open Create Project Dialog

Click on “Create Project” in the Quick Start panel. This will open the New Project
dialog as shown in Figure 2. Click Next to continue.

Figure 8 Create Project Dialog

3. Set Project Name and Location

Enter a name for the project. In the figure, the project name is “Vedic_Algorithm”,
which isn’t a particularly useful name. It’s usually a good idea to make the project name
more descriptive, so you can more readily identify your designs in the future.

Figure 9 Enter Project Name

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4. Select Parts
Xilinx produces many different parts, and the synthesizer needs to know exactly what
part you are using so it can produce the correct programming file. To specify the correct
part, you need to know the device family and package, and less critically, the speed and
temperature grades (the speed and temperature grades only affect special-purpose
simulation results, and they have no effect on the synthesizer’s ability to produce
accurate circuits). You must choose the appropriate part for the device installed on your
board.

For example, the Blackboard uses a Zynq device with the following attributes:

Part Number xc7a100tcsg324-1

Family Zynq-7000
Package Csg324
Speed Grade -1

Figure 10 Select Zynq 7000 Part

5. Check the Project Configuration Summary

On the last page of the Create Project Wizard, a summary of the project configuration is
shown. Verify all the information in the summary is correct, and in particular make sure
the correct FPGA part is selected. If anything is incorrect, click back and fix it;

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otherwise, click Finish to finish creating an empty project.

Figure 11 Create Project Summary

6.Vivado Project Window

After you have finished with the Create Project Wizard, the main IDE window will be
displayed. This is the main “working” window where you enter and simulate your
Verilog code, launch the synthesizer, and program your board. The left-most pane is the
flow navigator that shows all the current files in the project, and the processes you can
run on those files. To the right of the flow navigator is the project manager window
where you enter source code, view simulation data, and interact with your design. The
console window across the bottom shows a running status log. Over the next few
projects, you will interact with all the panels.

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Figure 12 Vivado Project Window

Step 2: Edit The Project - Create source files

1. Design Sources
There are many ways to define a logic circuit, and many types of source files including
VHDL, Verilog, EDIF and NGC netlists, DCP checkpoint files, TCL scripts, System C
files, and many others. We will use the Verilog language in this course, and introduce it

Figure 13 Add Design Sources

gradually over the first several projects. For now, you can get familiar with some of the
basic concepts by reading the following.

To create a Verilog source file for your project, right-click on “Design Sources” in the
Sources panel and select Add Sources. The Add Sources dialog box will appear as
shown – select “Add or create design sources” and click next.

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Figure 14 Add or create design sources using Add Source Dialog

In the Add or Create Design Sources dialog, click on Create File, enter “mba” as
filename, and click OK. The newly created file will appear in the list as shown. Click
Finish to move to the next step.

Figure 15 Creation of Design Source File

Skip the Define Module dialog by clicking OK to continue.

2. Alternative: Download and Add the Source
Instead of creating a source file by using copy and paste as described above, you can
alternatively download the “mba.v” file and add it to your project using the Add
Sources button in Add Sources dialog.

Figure 16 Vedic appears in design sources

3. Constraints

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Design sources, like Verilog HDL files, only describe circuit behavior. You must also
provide a constraints file to map your design into the physical chip and board you are

working with. To create a constraint file, expand the Constraints heading in the Sources
panel, right-click on constrs_1, and select Add Sources.

Figure 17 Add Source to Design Constraints

An Add Sources dialog will appear as shown. Select Add or Create Constraints and
click Next to cause the “Add or Create Constraints” dialog box to appear.

Figure 18 Add or create design constraints using Add Source Dialog

Click on Create File, enter project1 for the filename, and click OK. The newly created
file will appear in the list as shown. Click Finish to move to the next step.

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Figure 19 Creation of Constraints File

Double-click “mbv1.xdc” to open the file, and replace the contents with the code below:
4. Alternative: Download and Add Constraints
Instead of creating an empty constraint file and using copy-and-paste to replace the
contents as described above, you can also download “mba1.xdc” the file and add it to
your project using the Add Files button in the Add Sources dialog.

Figure 20 Double-click to Edit mba1.xdc

Step 3: Synthesize, Implement, and Generate Bitstream

1. Synthesis

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After your Verilog and constraint files are complete, you can Synthesize the design
project. In the synthesis process, Verilog code is translated into a “netlist” that defines
all the required circuit components needed by the design (these components are the

programmable parts of the targeted logic device - more on that later). You can start the
Synthesize process by clicking on Run Synthesis button in the Flow Navigator panel as
shown.
When synthesis is running, you can select the log panel located at the bottom of Project
Manager to see a log of the currently running processes. Any errors that occur during
the synthesis process will be described in the log.

Figure 21 Start the Synthesis process and monitor the synthesis log

2. Implementation
After the design is synthesized, you must run the Implementation process. The
implementation process maps the synthesized design onto the Xilinx chip targeted by
the design. Click the Run Implementation button in the Flow Navigator panel as shown.
When the implementation process is running, the log panel at the bottom of the Project
Manager will show details about any errors that occur.

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Figure 22 Start Implementation process and monitor the implementation log

3. Generate Bitstream
After the design is successfully implemented, you can create a .bit file by clicking on
the Generate Bitstream process located in the Flow Navigator panel as shown. The
process translates the implemented design into a bitstream which can be directly
programmed into your board’s device.

Figure 23 Generate Bitstream

STEP 4: DOWNLOAD BITSTREAM

1. Open Hardware Manager
After the bitstream is successfully generated, you can program your board using the
Hardware Manager. Click Open Hardware Manager located at the bottom of Flow
Navigator panel, as highlighted in red light.
2. Connecting Your Board via USB
Connect your Blackboard to your Computer with a micro-USB cable. Make sure you
connect the micro-USB cable to the port labeled “PROG UART”. Turn on your board
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by moving the switch in the top-left corner to the on position. You’ll see a red LED
light up by the switch when it powers on. If your board doesn’t power on, check that the
blue jumper by the port labeled “EXTP” is set to “USB”. The figure shows a powered-
on Blackboard, with the correct jumper setting.

Figure 24 Powered on Blackboard

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6. SIMULATION RESULTS
6.1 DATA FLOW OF A DIAGRAM

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Figure 25 Data Flow of Diagram

The project was implemented using the Xilinx Vivado design suite. The divider was
designed using a pipelined architecture, in each stage different operations are performed
to get the valid quotient and remainder. Each module of the data flow diagram performs
a valid function.

6.2 DEVICE AND ROUTING

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Figure 26 Device and routing inside it

Partial result: This module calculates the partial result of the division by subtracting the
divisor from the dividend. The partial result is the remainder after the first subtraction.
RTL SUB: This module performs the subtraction operation. It takes two inputs, the
dividend, and the divisor, and outputs the remainder.
Remainder: This module stores the remainder after the first subtraction. It is used by the
RTL GEQ module to compare the remainder to the divisor.
RTL GEQ: This module compares the remainder to the divisor and generates a signal
indicating whether the remainder is greater than or equal to the divisor. This signal is
used by the RTL MUX module to select the partial result or the remainder as the output.
RTL MUX: This module selects the partial result or the remainder as the output,
depending on the signal from the RTL GEQ module. If the remainder is greater than or
equal to the divisor, then the partial result is selected as the output. Otherwise, the
remainder is selected as the output.
Quotient: This module stores the quotient of the division. It is updated each time the
RTL MUX module selects the partial result as the output.

6.3 SCHEMATIC OF DIVIDER

Figure 27 Complete schematic of divider

The schematic diagram in the image shows a circuit with the following components:

157 cells: These are the basic building blocks of the circuit. They can be batteries, solar

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cells, or other power sources.

32 input/output (I/O) ports: These are the points where the circuit interacts with the
outside world. For example, I/O ports can be used to connect sensors, actuators, and
displays.

228 nets: These are the connections between the components in the circuit.

Operands: This store 8-bit operands “Divisor” [A] and “Dividend” [B]

Inverter: This stage complements the divisor except MSB (Most significant bit)

Multiplier: This stage multiplies the bits of dividend and complements bits of the
divisor.

Adder: Adder adds the multiplier result and dividend which gives partial remainder and
quotient.

Incrementer: Incrementer is used to calculate the number of terms in the quotient,

initially it is set to 0.

Condition Check: If the partial remainder is greater than the divisor then the process
repeats, until partial remainder is less than divisor.

Result: Result consists of two parts Quotient and Remainder. Quotient is number of
terms the process is repeated and the remaining part is Remainder.
6.4 PACKAGE OF FPGA

Figure 28 Package of FPGA

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 Pins: The pins column shows the names of the I/O pins. The pins are named in a

 specific format, which includes the bank and the PIN. For example, the pin "AA1" is
in bank A and is PIN 1.

 Bank: The bank column shows the bank that the pin is located in. FPGAs are divided
into banks, which are groups of I/O pins. The banks are used to route the signals
between the I/O pins and the internal logic of the FPGA.
 Direction: The direction column shows the direction of the pin. The direction can be
input, output, or bidirectional. An input pin is a pin that receives data from an external
device. An output pin is a pin that sends data to an external device. A bidirectional pin
can both send and receive data.
 I/O Standard: The I/O standard column shows the I/O standard that the pin is using. The
I/O standard defines the electrical characteristics of the pin, such as the voltage level
and the drive strength.
 Used: The used column shows whether the pin is being used by the design. If a pin is
not being used, it is set to "No".
 Assigned To: The assigned to column shows the net that the pin is assigned to. A net is
a group of wires that are connected. The net name is typically the name of the signal
that is being carried on the wires.

The I/O planning report is a valuable tool for designing and implementing FPGA
circuits. It is important to make sure that the I/O pins are being used correctly and that
the I/O standards are correct for the devices that are being connected to the FPGA.

Site Type Used Fixed Available Util%

Slice LUTs 85 0 63400 0.13
LUT as Logic 85 0 63400 0.13
LUT as Memory 0 0 19000 0
Slice Registers 0 0 126800 0
Register as Flip 0 0 126800 0
Flop
Register as Latch 0 0 126800 0
F7 Muxes 0 0 31700 0
F8 Muxes 0 0 15850 0

Table 1 Slice Logic

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Site Type Used Fixed Available Util%

Bonded 32 0 210 15.24
Bonded IPADs 0 0 2 0
PHY_CONTROL 0 0 6 0
PHASER_REF 0 0 6 0
OUT_FIFO 0 0 24 0
IN_FIFO 0 0 24 0
IDELAYCTRL 0 0 6 0
IBUFDS 0 0 202 0
PHASER_OUT/PHASER_OUT_PHY 0 0 24 0
PHASER_IN/PHASER_IN_PHY 0 0 24 0
IDELAYE2/IDELAYE2_FINEDELAY 0 0 300 0
ILOGIC 0 0 210 0
OLOGIC 0 0 210 0

Table 2 IO and GT specific

Ref Name Used Functional Category

LUT4 50 LUT
LUT3 45 LUT
IBUF 16 IO
OBUF 16 IO
LUT6 2 LUT
LUT5 1 LUT
CARRY4 21 CarryLogic
LUT2 16 LUT
Table 3 Primitives

The table contains the list of functional categories of different components used in an
FPGA. The table lists the number of times each component was used in the design. Here
is a brief description of each component:
• FDRE: This component is a flip-flop that stores a single bit of information. It is used
to hold the state of a signal between clock cycles.
• LUT6: This component is a lookup table that can implement any 6-input Boolean
function. It is used to implement combinational logic in an FPGA.

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• LUT4: This component is a lookup table that can implement any 4-input Boolean
function. It is used to implement combinational logic in an FPGA.

• LUT3: This component is a lookup table that can implement any 3-input Boolean
function. It is used to implement combinational logic in an FPGA.
• LUT5: This component is a lookup table that can implement any 5-input Boolean
function. It is used to implement combinational logic in an FPGA.
• LUT2: This component is a lookup table that can implement any 2-input Boolean
function. It is used to implement combinational logic in an FPGA.
• FDSE: This component is a flip-flop that stores a single bit of information. It is used to
hold the state of a signal between clock cycles.
• LUT1: This component is a lookup table that can implement any 1-input Boolean
function. It is used to implement combinational logic in an FPGA.
• MUXF7: This component is a multiplexer that can select one of up to 128 inputs.
It is used to implement complex logic functions in an FPGA.

Figure 29 Power Analysis

6.5: SIMULATED RESULTS

Assume Input and its assignment:
Assume Input Divisor= 12 Output Quotient=1
Input Dividend=13 Output Remainder=1

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Figure 30 Simulated Results

6.6 RESULTS ON FPGA BOARD

Figure 31 Results on FPGA Board

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Description of Results:
RESULT-1: In the FPGA board we have considered 254 as dividend whose binary
number is 11111110 and 12 as divisor 00001100. The switches indicate the values of
the dividend and divisor, and the LEDs indicate the values of the remainder and
quotient. In this case, the quotient is 21 and the remainder is 2.
RESULT-2: In the FPGA board we have considered 80 as dividend whose binary
number is 001010000 and 24 as divisor 00011000. The switches indicate the values of
dividend and divisor, and the LEDs indicates the values of remainder and quotient. In
this case the quotient is 3 and the remainder is 8.

6.7 COMPARISON OF RESULTS

In this project, both Parvartya sutra and long division are implemented on the FPGA
board using the Xilinx Vivado software tool, which helped a lot to understand the
difference between the two division methods and which we should choose for more
efficiency and Fastness. This comparison helped us to realize why we should prefer
Paravartya Method and how efficient it is in terms of various factors compare to long
division method.

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FACTOR VEDIC DIVISION LONG DIVISION

Total on Chip Power 11.984W 12.265W

Dynamic Power 11.778W (98%) 12.050W (98%)

Device Static Power 0.205W 0.215W

Logic Power 0.670W 0.740W

Input Output Power 10.462W 10.620W

Slices 24 25

Look Up Tables 85 85

Delays --- ---

Look Up Table Utilization 0.13% 0.13%

I/O Utilization 15.24% 15.25%

Table 4 Comparison of Vedic division and long division

Note: This process does not involve any clock cycles, as the Paravartya Sutra method
operates without relying on a clock signal, so there will be no delays.

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Figure 32Power usage of long division.

Figure 33 Power usage of Vedic division.

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7. ADVANTAGES & APPLICATIONS

7.1ADVANTAGES
1. Reduced hardware complexity: Vedic dividers can be implemented using fewer logic
gates than conventional dividers, making them smaller and more compact.
2. Faster division speed: Vedic dividers achieve higher throughput than conventional
dividers due to their bit-serial nature, which means they perform division one bit at a
time.
3. Lower power consumption: Vedic dividers typically consume less power than
conventional dividers due to their simplicity.
4. Efficiency: The Vedic Divider uses a streamlined method inspired by ancient
mathematical techniques, making the division process more efficient and faster
compared to conventional methods.
5. Simplicity: The approach is intuitive and straightforward, reducing the complexity of
the division operation. This simplicity is advantageous for mental calculations and
digital systems.
6. Parallelism: The Paravartya method allows for parallel processing of division steps,
potentially speeding up the overall computation. This is particularly beneficial in digital
circuits where parallel operations enhance efficiency.
7. Ease of Mental Calculation: Vedic mathematics techniques are often designed for
mental calculations. While this may not be a significant advantage in automated
systems, it can be valuable for educational purposes or situations where mental
arithmetic skills are emphasized.
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8.Efficient Handling of Fractions: Vedic mathematics places a strong emphasis on

fractions and offers techniques that simplify the handling of fractional numbers. This
can be advantageous in applications where precise fractional results are essential.
Cultural and Educational Significance: Vedic mathematics has cultural and historical
roots, and using Vedic dividers can be a way to connect with this heritage. In
educational settings, introducing Vedic techniques may spark interest and engagement
among learners.

7.2 APPLICATIONS

1. Embedded Systems: These are small, specialized computers found in everyday

devices like smartphones, wearable gadgets, and even kitchen appliances. Vedic
dividers are ideal for these systems because they consume less power and require fewer
components, making them more efficient and compact.
2. VLSI (Very Large Scale Integration) Applications: This involves designing and
manufacturing integrated circuits, the tiny chips that power our electronic devices.
Vedic dividers are valuable in VLSI because they can perform division operations
quickly and efficiently, which is essential for processing signals and data in digital
systems.
3. Digital Signal Processing (DSP): This field deals with manipulating and analyzing
digital signals, like the audio you hear from your speakers or the images you see on
your screen. Vedic dividers are helpful in DSP because they can perform division
operations on these signals, which is necessary for filtering, modulation, and other
essential DSP tasks. Microcontrollers and Embedded Systems:
4. Real-Time Processing:
Applications that demand real-time processing, such as signal processing or control
systems, can benefit from the speed and efficiency of the 8-bit Vedic Divider. Its ability
to parallelize operations contributes to faster computation.
5. Low-Power Devices:
In battery-powered devices or energy-efficient systems, the 8-bit Vedic Divider's

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efficiency can be advantageous. It allows for quicker computations, reducing the time
the processor needs to be active and conserving power.
6. Educational Tools:
As a pedagogical tool, the 8-bit Vedic Divider can be used to teach students about
historical mathematical methods and their application in modern digital systems. It
provides a tangible link between ancient mathematical principles and contemporary
computing.

8. CONCLUSION AND FUTURE SCOPE

8.1 CONCLUSION

In conclusion, the FPGA implementation of the 8-bit Vedic divider using

the Paravartya Sutra project has successfully demonstrated an innovative and efficient
approach to division. By leveraging the ancient Vedic mathematical technique of
Paravartya, this project aimed to optimize the division process for an 8-bit architecture.
Through careful FPGA design and implementation, the project showcased how
traditional mathematical principles could be applied in a modern computing context,
highlighting the versatility and adaptability of Vedic mathematics. The utilization of
Paravartya Sutra contributed to faster and resource-efficient division operations
compared to conventional methods.
This project not only explored the intersection of ancient mathematical
wisdom and contemporary FPGA technology but also provided a practical
demonstration of how unconventional approaches can lead to improved computational
efficiency. The successful implementation of the 8-bit Vedic divider serves as a
testament to the potential synergy between historical mathematical techniques and
cutting-edge hardware design.

8.2 FUTURE SCOPE:

Future Scope of Vedic Dividers Using Paravartya Method Vedic mathematics, an

ancient system of mathematical techniques, offers several advantages over conventional

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methods, particularly in terms of speed and efficiency. The Paravartya method, one of
the Vedic sutras, is a powerful tool for division, and its implementation in architectures
holds immense potential for future applications. Several promising research directions
exist for Vedic dividers using the Paravartya methods such as Hardware Optimization,
Error Correction, Application-Specific Design, Integration with Other Vedic
Techniques.
The future of 8-bit Vedic dividers using the Paravartya method is bright, with potential
applications in various fields and promising research directions to further enhance their
performance and applicability.

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9.REFERENCES
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IEEE Int. Computer, Communication, Control and Power Engineering Conf. 1993,
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https://d-nb.info/1220892254/34?shem=ssusxt
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3043862_Division_algorithms_and_implementations
 R. Senapati, B. K. Bhoi and M. Pradhan, "Novel binary divider architecture for high
speed VLSI applications," 2013 IEEE Conference on Information & Communication
Technologies, Thuckalay, India, 2013, pp. 675-679,
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Transactions on Computers, vol. 46, no. 8, pp. 833-854, Aug. 1997, doi:
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 J. E. Robertson, "A New Class of Digital Division Methods," in IRE Transactions on
Electronic Computers, vol. EC-7, no. 3, pp. 218-222, Sept. 1958, doi:
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 J. E. Meggitt, "Pseudo Division and Pseudo Multiplication Processes," in IBM Journal
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10.1147/rd.62.0210.

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