ANITA REDDY KAJA

+91-7095202444

kanitareddy@gmail.com

www.linkedin.com/in/anita- reddy-kaja-vlsi-industry

PERSONAL DETAILS CAREER OBJECTIVE

Father Name:
Venkateswara Reddy
Mother Name: Lakshmi Devi
Date of Birth: 30/11/1987
Languages Known: Telugu | English
Experienced professional with 6 years of experience in
private-engineering college. Seeking an entry-level in
the field of VLSI with a strong will to prove my efficiency
and a highly motivated and hardworking individual with
a desire to learn new things.

PROFESSIONAL COURSE PROFESSIONAL EXPERIENCE

Advanced VLSI Desing and Worked as Assistant Professor in Newton' s College of
Verification Course Engineering & Technology, Macherla, Guntur (Dt)from
June 2009 to May 2011.
Institute : Maven Silicon, Bengaluru
Duration : June 2022 to Present Worked as Assistant Professor in Malineni Lakshmaiah
Womens Engineering College, Pulladigunta, Guntur(Dt)
from June 2012 to May 2016.
HOBBIES & INTERESTS
Cooking
EDUCATION
Art & Crafts
M.Tech -VLSI & Embedded Systems| 2013
Travelling St.Ann's College of Engineering & Technology.
Chirala,Andhra Pradesh,India.
Listening to music
CGPA: 7.25 | Percentage: 72.57%

PERSONAL TRAITS B.Tech-EIE | 2005-2009

Punctuality St.Ann's College of Engineering & Technology.
Chirala,Andhra Pradesh,India.
Accountability CGPA: 6.63 | Percentage: 62.99%

Flexibility Intermediate | 2003-2005

Sujatha Junior College.
Dedication Ponnur,Andhra Pradesh,India.
Percentage: 81%
Honesty
Primary & Secondary School - ICSE | 2003
St.Ann's English Medium School.
Ponnur,Andhra Pradesh, India.
Percentage: 60%
PROJECTS

AHB2APB BRIDGE IP CORE VERIFICATION

The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB
and the low performance APB buses.

ROUTER-RTL DESIGN AND VERIFICATION

The router accepts data packets on a single 8-bit port and routes them to one of the three output
channels, channel0, channell and channel2

POWER OPTIMIZED MULTI-BIT FLIP-FLOPS USING GATED DRIVER TREE

The underlying idea behind this project is to reduce the overall power consumption in multi-
bit flip-flops using gated driver tree.

DESIGN SKILLS
DIGITAL ELECTRONICS
Combinational & Sequential circuits, FSM

VERILOG PROGRAMMING
Data types, Operators, Processes, BA & NBA, Delays in Verilog, begin - end & fork join blocks,
looping & branching construct, System tasks & Functions, compiler directives, FSM coding,
Synthesis issues, Races in simulation, pipelining RTL & TB Coding.

ADVANCED VERILOG & CODE COVERAGE

Generate block, Continuous Procedural Assignments, Self-checking testbench, Automatic Tasks,
Named Events and Stratified Event Queue
Code Coverage: Statement and branch coverage, Condition & Expression Coverage, Toggle &
FSM Coverage

VERIFICATION SKILLS

UVM
UVM Objects & Components, UVM Factory & overriding methods, Stimulus Modelling, UVM
Phases, UVM Configuration, TLM,UVM Sequence, Virtual sequence & sequencer, Introduction to
RAL.

SYSTEM VERILOG
Interface and clocking block, Inheritance and Polymorphism, HVL Constraint randomization -
Inline, Distribution, Conditional, Soft and static constraints. Mailbox and semaphores,
Functional coverage, CRCDV and regression testing.

SYSTEM VERILOG ASSERTIONS

Types of assertions, assertion building blocks, sequences with edge definitions and logical
relationship. Sequences with different timing relationships. clock definitions, implication and
repetition operators, different sequence compositions, inline and binding assertions,
advanced SVA Features and assertion Coverage.

BASIC AND ADVANCED OBJECT ORIENTED PROGRAMMING

Handle assignments, Copying the object contents, Inheritance, polymorphism, static
properties and methods, virtual classes and parameterized classes.
ACHIEVEMENTS
Published paper on Power Optimized Multi-bit Flip-Flops using Gated Driver Tree in IJERT, Volume
2,ISSUE 5(MAY 2013)

DECLARATION
I hereby declare that above information provided is true to best of my knowledge and belief.

Date:
Place:
ANITA REDDY KAJA