Lecture 13
OUTLINE
• pn Junction Diodes (cont’d)
– Charge control model
– Small-signal model
– Transient response: turn-off
Reading: Pierret 6.3.1, 7, 8.1; Hu 4.4, 4.10-4.11
PN Junction Admittance
Reverse bias junction capacitance
•It is common to use reverse biased PN junction as a
capacitor
•important for circuit design
•similar to a parallel plate capacitor with depletion
region as insulator
W
capacitance/unit area
given by:
p n
Si
xp xn Cj =
W
PN Junction Admittance
Determining reverse bias capacitance
PN Junction Admittance
Forward Bias Junction Capacitance
•At forward bias, the quasi-neutral regions store charge and
more significant than the depletion region
•Charge stored equal to
npd pnd
injected
minority pn0
np0
carrier
Ln Lp
qVA
= q (npe − n0 ) qn pe = q n p0 e kT
Ln Ln Ln 2 qVA
Qdiff Cdiff = dQ = q Ln np0e nkT = Qdiff
2 2 2 dV 2kT Vthm
pn Junction Small-Signal Capacitance
2 types of capacitance associated with a pn junction:
dQdep
depletion capacitance CJ
− due to variation of depletion charge dVA
dQ
diffusion capacitance CD
dVA
–due to variation of stored
minority charge in the quasi-neutral regions
For a one-sided p+n junction Q = QP + QN QP so
dQP dI τ p I DC
CD = = τp = τ pG =
dVA dVA kT / q
Depletion Capacitance
C. C. Hu, Modern Semiconductor Devices for ICs, Figure 4-8
dQdep s
CJ =A
dVA W
What are three ways to reduce CJ?
Total pn-Junction Capacitance
C = CD + CJ
s
CD =
τI DC
kT / q
( )
e qVA / kT − 1 CJ = A
W
•CD dominates at moderate to high forward biases
•CJ dominates at low forward biases, reverse biases
PN Junction Admittance
Capacitance characteristics
ideal C • at forward bias, the two
ends of a diode are shorted
real Cj0 and the diode is no longer
an insulator
VA • Capacitance disappears
VBi
•To allow better fitting of the data, another parameter m is
introduced and the equation becomes
−m
V 1 1
C j = C j 0 1− A and m abrupt
V bi 3 2 junction
linear junction
Using C-V Data to Determine Doping
1 W2 2(Vbi − VA )
= 2 2 2
CJ
2
A s A q S N
Lecture 13, Slide 9
Example
If the slope of the (1/C)2 vs. VA characteristic is -2x1023 F-2 V-1,
the intercept is 0.84V, and A is 1 mm2, find the dopant
concentration Nl on the more lightly doped side and the
dopant concentration Nh on the more heavily doped side.
Solution: N l = 2 /( slope q s A2 )
= 2 /( 2 10 1.6 10
23 −19
10 −12
(
10 ))
−8 2
= 6 1015 cm −3
2 qV 0.84
kT N h N l ni kTbi 10 20 0.026 −3
Vbi = ln N = e = e = 1. 8 1018
cm
6 1015
2 h
q ni Nl
Example
If the slope of the (1/C)2 vs. VA characteristic is -2x1023 F-2 V-1,
the intercept is 0.84V, and A is 1 mm2, find the dopant
concentration Nl on the more lightly doped side and the
dopant concentration Nh on the more heavily doped side.
Solution:
PN Junction Admittance
Junction Conductance
•A diode can be regarded as a non-linear resistor
•The small signal resistance can be found from the slope of
the I-V characteristic curve
I gd=slope at a given bias
qV A
dI q
gd = = I0e kT
dVA kT
V
q I
or gd = (I + I 0 )
kT Vthm
• After a biasing point is defined, the conductance (resistance)
can be calculated
PN Junction Admittance
Circuit Model
• a way to communicate with circuit designers
• physical effects are not emphasized
RS
large signal
Cj Cdiff
or
RS
I
small signal gd = Cj Cdiff
Vthm
Speed of Diode
Small-Signal Model Summary
C = C J + CD
I DC = I 0 (e qVA / kT − 1)
A s
Depletion capacitance CJ =
W I DC
Conductance G
τI DC kT / q
Diffusion capacitance CD =
kT / q
R. F. Pierret, Semiconductor Device Fundamentals, p. 302
Extracting PN Junction Parameters
Typical electrical parameters in a data sheet
• These data is not obtained from theoretical calculations, but
physical measurements
• The process is call electrical parameter extraction
Extracting PN Junction Parameters
The parameter extraction process
•You first measure the diode characteristics in both log and
linear scale
•Then based on a model, find out all corresponding values of
the elements
I log(I)
RS given qVD
by 1/slope enkT −1
I = I0
VBD
V V
VF find I0 and n to make
the equation fit the
data
Transient Response of pn Diode
• Suppose a pn-diode is forward biased, then suddenly turned
off at time t = 0. Because of CD, the voltage across the pn
junction depletion region cannot be changed instantaneously.
The time delay in switching between
the FORWARD-bias and REVERSE-bias
states is due to the time required to
change the amount of excess minority
carriers stored in the quasi-neutral regions.
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 8.2