A Low Spurious and Small Step Frequency

Synthesizer Based on PLL-DDS-PLL Architecture

Meng Hu, Ling Wang, Xiaohong Tang
School of Electronic Engineering, University of Electronic Science and Technology of China
Chengdu, Sichuan, China, 610054
menge84@live.cn
AbstractThis paper describes a low spurious and small step
frequency synthesizer module based on PLL (Phase-Locked
Loop)DDS (Direct Digital Synthesis)-PLL structure, which is
controlled by the parallel port of the computer. The module
consists of four parts: the first PLL (PLL1), the DDS, the second
PLL (PLL2) and the control part. The spurious of this module is
ameliorated to some extent in comparison with traditional
synthesizer technologies using single PLL. The experimental
measurement of the actual module shows that the spurious is as
low as 65dBc. In addition, its frequency range is 2060MHz-
2160MHz, the frequency step size 10 kHz, the phase noise
90dBC/Hz@10kHz and the harmonics 40dBc.
Keywords-Phase-Locked Loop; Direct Digital Synthesis;
Frequency Synthesizer; Low Spurious; Small Step
I. INTRODUCTION
Nowadays, frequency synthesizers are widely used in
modern communication systems. There are many frequency
synthesis technologies [1], such as direct analogy synthesis
(DS), the DDS, the PLL and the mixture of the former
technologies, etc. The DS has advantages of fast hopping time
and high output frequency but it also has the disadvantages of
requiring large amount of hardware and high intermodulation
distortion [2]. The DDS can generate small frequency step sizes
and tune fast but has shortcomings of high spur levels and low
output frequency [3]. The PLL has to trade off between
frequency step size and phase noise [4]. In order to achieve
better performances, the research on the hybrid frequency
synthesis technology such as the DS-PLL, the DDS-PLL, the
DS-DDS and the DS-PLL-DDS, is very popular and
challenging [5-8].
In this paper, a PLL-DDS-PLL architecture is presented to
meet the demand of low spurious and small frequency step size.
The changeable output frequency of the first PLL acts as the
reference frequency of the DDS. If the output of the DDS
contains high-level spurs, the reference frequency of the DDS
can be changed to another to make the output spurs of the DDS
lower because the spurs appear randomly. Then, the output of
the DDS drives the PLL2 to obtain final signal.
II. OVERALL ARCHITECTURE
In Fig.1, the block diagram of the overall architecture is
presented, which consists of the PLL1, the DDS, the PLL2 and
the control part. The external oscillator whose output
frequency is 100MHz acts as the reference of the PLL1. In the
PLL1, the reference divider (R) is set to 5, so the phase-
detected frequency is 20MHz. The divider counter (M) can be
changed by the control part so that the output frequency of the
PLL1 can vary within the range between 480MHz and
540MHz with the frequency step of 20MHz. Then, the output
signal of the PLL1 is taken as the reference frequency (f1) of
the AD9858 (DDS chip of Analog Devices) [9]. The output
frequency of the DDS is within the range from 82.4MHz to
86.4MHz with the step of 400Hz. Moreover, the PLL2
generates signal whose frequency vary from 2060MHz to
2160MHz with the step of 10 kHz after the signal from the
DDS is inputted into the PLL2. Finally, the final output signal
can be obtained after filtering, amplification and isolation. In
addition, the control part is responsible for inputting data,
converting instructions and sending them to the phase detector
chip in the PLL1 and the AD9858.
Figure 1. Overall Architecture
III. NOISE ANALYSIS
In this section, the phase noise and the spurious of the
module will be discussed.
A. Phase Noise Analysis
In this module, the DDS has little effect on the phase noise
of the output because the phase noise of the DDS is very low
so that the phase noise is mainly determined by the phase-
locked loops. For the phase-locked loops, the phase noise of
the output is determined by the phase noise of the reference,
the phase noise of the voltage controlled oscillator (VCO), the
divider counter, the phase noise floor of digital phase detector
chip and loop bandwidth. In Fig.2, the relationship between
loop bandwidth and phase noise is described. Within the loop
bandwidth, the phase noise of the output signal is determined
by that of the reference signal and the multiplication times.
Out of the loop bandwidth, the phase noise of the output is
determined by that of the VCO [10]. So a loop bandwidth that
1-4244-2424-5/08/$20.00 2008 IEEE ICCS 2008 1471
makes the phase noise determined by the reference signal and
multiplication times equal that determined by the VCO is
usually chosen. In addition, the phase noise floor of the digital
phase detector chip should be paid attention to because the
phase noise of the output is sure to be higher than it through
fair and foul. The phase noise floor can be calculated by
Flooi NoimPNFli lgf

lg Nul
Where Floor is the phase noise floor, NormPNFlr is the
normalized phase noise floor of the phase detector chip, f

is the phase-detected frequency, and Mul is the multiplication

times. In this paper, two ADF4113 chips (digital phase
detector chip of Analog Devices) [11] are used in the PLL1
and the PLL2 respectively, whose normalized phase noise
floor is 215dBc/Hz. According to the former principles, the
final phase noise of the output is about 103dBc/Hz in theory,
which has a reserve of 13dB.
Figure 2. Typical Phase Noise Spectral Plot of a PLL
B. Spurious Analysis
Because the spurs of the phase-locked loops are much
lower than that of the DDS, the spurs generated by the DDS
will be mainly discussed in this part. In Fig.3, the simplified
block diagram of the conventional DDS is shown. It contains
four parts: phase accumulator, sine ROM (phase to amplitude
converter) table, digital to analogy converter (D/A-converter)
and low pass filter (LPF). The output spurs of the DDS are
mainly caused by phase truncation error of sine ROM table,
amplitude quantization error and digital to analog non-
linearity error of D/A-converter [12]. The phase truncation
error is caused by the number of words in the ROM, while the
amplitude quantization error is caused by the number of bits in
the D/A converter. For the fixed DDS chip, we can do nothing
to improve the amplitude quantization error and digital to
analog non-linearity error. But for the same output of the DDS,
the reference frequency can be changed to obtain a different
frequency tuning word (FTW) that makes the phase truncation
error much lower. This is the key to suppress the spur levels of
the output in this paper. For every final output signal, the
corresponding reference frequency of the DDS is selected to
maintain that the spur levels are lower than -65dBC.
Figure 3. Simplified Block Diagram of DDS
IV. THE CONTROL PART OF THE MODULE
The control part is very critical to the whole module. Its
main function is looking up the corresponding reference
frequency of the DDS for every output point, sending
instructions to the ADF4113 in the PLL1 and transmitting the
FTWs to the AD9858. Also, the control part must complete
auto-measurement of the module because there are 10
thousands points to measure. The control part consists of two
parts: the control part of single output and the control part of
auto swept-frequency and measurement. To fulfill the control,
a program is developed using the visual basic language [13,
14]. In Fig.4, the control window of single output is described.
After the desired output frequency inputted and the button
Load clicked, the corresponding reference frequency of the
DDS is found out, the instructions are sent to the ADF4113 in
the PLL1 and the corresponding FTW is transmitted to the
AD9858 by the parallel port of the computer. In Fig.5, the
control window of auto swept-frequency and measurement is
shown. After the button Measure is clicked, the frequency of
the output signal increases from the start frequency to the end
frequency with the frequency step size of 10 kHz, the screen
picture of the spectrum analyzer is shown on the right side of
the window and the measurement results are saved in the
given file of the computer. In addition, the control of the
ADF4113 in the PLL2 is executed by a MCU.
Figure 4. The Control Window of Single Output
Figure 5. The Control Window of Auto Swept-frequency and Measurement
1472
V. MEASUREMENT AND RUSULT ANALYSIS
The measurement of the module is divided into two parts:
adjusting each unit circuit separately and measuring the output
of the whole module. The measured spectrum of the module
will be analyzed in the following.
In Fig.6, the output spectrum of the PLL1 at 540MHz with
the span of 2 MHz is described. From the figure, the loop
bandwidth is about 500 kHz. In Fig.7, the phase-noise
frequency spectrum of the PLL1 output at carrier offset 10
kHz is shown. According to the figure, the phase noise is
110.7dBc/Hz@10kHz. Because the phase noise of the DDS
can be ignored, the phase noise of the final output is
110.7+20lg(2160/540)=98.7dBc/Hz@10kHz. (2)
From (2), the calculated phase noise of the final output is
8.7dB lower than the desired.

Figure 6. The Frequency Spectrum of the PLL1 Output at 540MHz
Figure 7. The Phase-noise Frequency Spectrum of the PLL1 Output at
540MHz
Frequency hopping of the DDS and the PLL2 are shown in
Fig.8 and Fig.9 respectively. The frequency step size of the
DDS is 400Hz, while the step of the PLL2 output is 10kHz
because the output frequency of the PLL2 is 25 times as large
as that of the DDS.
Figure 8. Frequency Hopping of the DDS
Figure 9. Frequency Hopping of the Final Output
In Fig.10, the frequency spectrum of the final output at
2060MHz is shown. From the figure, there are scarely any
spurs within the span of 500kHz, so the spur levels are sure to
be lower than -65dBc/Hz. In Fig.11, the phase-noise frequency
spectrum of the final output at carrier offset 10 kHz is
described. According to the figure, the phase noise of the final
output is lower than 90dBc/Hz@10kHz.
Figure 10. The Frequency Spectrum of the Final Output at 2060MHz
1473
Figure 11. The Phase-noise Frequency Spectrum of the Final Output
In Fig.12, the harmonics of the final output is shown. Its
apparently that the harmonics suppression is much lower than
40dBc.
Figure 12. Harmonics Suppression
VI. CONCLUSION
In this paper, a hybrid frequency synthesizer based on
PLL-DDS-PLL architecture is introduced. The computer
controlling the ADF4113 and the AD9858 is utilized in this
project so that its more convenient to adjusting the module.
Get across adjusting and testing, the frequency synthesizer
module achieved the goal that spur levels are all lower than
65dBc, phase noise lower than 90dBc/Hz@10kHz,
harmonics suppression lower than 40dBC and step size 10
kHz.
[1] D.P.Noel and T.A.Kwasniewski, "Frequency Synthesis: A Comparison
of Techniques," Electrical and Computer Engineering Conference
Proceedings. Canadian Conference on 25-28 Sept. 1994, vol.2, pp. 535-
538.
[2] Milan STORK, "Frequency Synthesizer Based on Coincidence Mixer,"
Radioelektronika, 2007. 17th International Conference, 24-25 April
2007, pp. 1-4.
[3] V.S.Reinhardt, "Spur Reduction Techniques in Direct Digital
Synthesizers," Proc.IEEE Int. Frequency Cont. Symp. 1993, pp.230-241
[4] Someshwar C. Gupta, "Phase-Locked Loops," Proceedings of the IEEE,
Vol. 63, NO. 2, February 1975, pp. 291-306
[5] A.Bonfanti, F. Amorosa, C. Samori, and A. L. Lacaita, "A DDS-Based
PLL for 2.4-GHz Frequency Synthesis," IEEE Transactions on Circuits
and Systems-: Analog and Digital Signal Processing, Vol. 50, No.12,
2003, pp. 1007-1010
[6] B. Makarenko, A. Kleiman, S.F. Dyubko, and E.A.Alekseev,
"MicroWave Frequency Synthesizers," MSMW' 2001 Symposium
Proceedings. Kharkov, Ukraine, June 4-9, 2001, pp. 885-886
[7] Seigo Oka and Thomas N. C. Wang, "On L-Band Double Loop,
Fractional-N Digital Synthesizer," 1997 Asia Pacific Microwave
Conference, pp. 325-327
[8] Yang Yumei, Zhang Yuxin and Zhou Zheng'ou, "High spectrum purity
signal source applied in X-band radar frequency criterion generator,"
Radar, 2001 CIE International Conference on, Proceedings, 15-18 Oct.
2001, pp.912 915
[9] AD9858 Technical Data Sheet, Anolog Devices, 2003.
[10] Dean Banerjee, PLL performance,simulation and design, Dog Ear
Publishing, LLC, 2001, Second Edition,pp. 3537.
[11] ADF4113 Technical Data Sheet, Analog Devices, 2005.
[12] Jouko Vankka, Spur Reduction Techniques in Sine Output Direct
Digital Synthesis, 1996 IEEE International Frequency Control
Symposium, pp. 951-959.
[13] Comrade Studio, Examples of Visual Basic 6.0 API Function
Development, Posts & Telecom Press, 2000.
[14] Qingfang Xu and Wanzhen Weng, Tutorial of Visual Basic 6 Drogram
Designs and Applications. Tsinghua University Press, 2007
1474